Abstract: A method for optimizing decoupling capacitance in a phase locked loop is provided. A representative power supply waveform having noise is input into a simulation of the phase locked loop; an estimate of jitter is determined; and an amount of the decoupling capacitance is adjusted until the jitter falls below a pre-selected value. Further, a computer system for optimizing decoupling capacitance in a phase locked loop is provided. Further, a computer-readable medium having recorded thereon instructions adapted to optimize decoupling capacitance in a phase locked loop is provided.

Abstract: A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.

Abstract: A system for verifying an integrated circuit design is provided. The system comprising: an I/O controller connected to one or more I/O cores, the I/O cores part of the integrated circuit design; an external memory mapped test device having a switch for selectively connecting one or more of the I/O cores to corresponding I/O driver models; a bus for transferring signals between the I/O controller and the switch; and a test operating system for controlling the switch.

Abstract: In a delay-power-source-coefficient determining step, a drain saturation current in a P-channel MOSFET is calculated on the basis of specified operating power-source voltage data and of saturation-current parameters such as the mobility of carriers and the thickness of a gate oxide film based on said specified operating power-source voltage data. Thereafter, a ratio of a drain saturation current in the P-channel MOSFET when a reference power-source voltage is applied thereto to the drain saturation current in the P-channel MOSFET when an operating power-source voltage is applied thereto, thereby determining a delay power-source coefficient. Next, in an effective-delay calculating step, effective-delay calculating means multiplies a delay time when the reference power-source voltage calculated by the delay calculating means is applied thereto by the delay power-source coefficient calculated by delay-power-source-coefficient determining means to determine a delay time at the operating power-source voltage.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: A method and computer system formally verifies a synthesis of integrated circuit designs that include pipeline registers. A hardware description language (HDL) representation of an integrated circuit is parsed. Components and connections of the HDL representation are identified. Pipeline register components of the HDL representation are removed. The removed pipeline register components are replaced with a conductor. Pipeline register components are added between output logic gates and output registers of the HDL representation to create a new HDL representation. Formal verification of the new HDL representation is performed using a verification tool.

Abstract: A method and apparatus are provided for solving a set of differential-algebraic equation arising in a circuit simulation is provided. A collocation method is applied to each differential-algebraic equation to discretize the set of differential-algebraic equations. A solution to the set of differential-algebraic equations based on the discretized differential-algebraic equation is then formed.

Abstract: The present invention, which may be implemented on a general-purpose digital computer, in certain embodiments includes novel methods and apparatus to provide accurate prediction for skew or delay analysis in complex multi-stage signal paths with mutual couplings between the stages. In some embodiments, single or multiple processors are utilized to implement the present invention.

Abstract: A method is provided for designing an integrated circuit that includes receiving a graphical description of the integrated circuit, extracting shapes relating to a specific circuit function from the graphical description of the integrated circuit, and partitioning the extracted shapes into a plurality of segments. The method may form an electrical representation of the integrated circuit for each of the plurality of segments and solve a matrix equation (Gv=i) for each of the plurality of segments based on the electrical representation.

Abstract: An HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist. Each module translated into the second RTL description may be also checked for compilation warning or error messages. If any warning or error messages are generated, the offending module(s) is modified to eliminate the warning or error messages.

Abstract: An independent current source and a voltage-dependent source are arranged at each of ports, and a voltage at each of the ports is calculated with a circuit analysis. A voltage source is arranged at each of the ports by using the calculated voltage value, and a current flowing in an analysis target is calculated with an electromagnetic wave analysis. An analysis time is incremented stepwise, and the calculation of the voltage at each of the ports and the calculation of the current flowing in the analysis target are repeated. As a result, an electromagnetic field intensity calculation can be made with high accuracy even for an analysis target where a plurality of ports exists between a circuit analysis model and an electromagnetic wave analysis model.

Abstract: Modeling a logic design includes displaying a menu comprised of different types of functional block diagrams, receiving an input selecting one of the different types of functional block diagrams, retrieving a selected functional block diagram, and creating a graphical representation of a logic design using the selected functional block diagram. The graphical representation is created by interconnecting the selected functional block diagram with one or more other functional block diagrams to generate a model of a logic design and defining the selected functional block diagram using simulation code if the functional block diagram is undefined when retrieved.

Abstract: A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

Abstract: A block dividing means (2) receives an original netlist (D1) defining a circuit to be simulated, selects a to-be-analyzed block specifying a device included in the circuit to be simulated based on input parameters provided from a parameter input means (1), divides the selected to-be-analyzed block into a plurality of to-be-analyzed sub-blocks, establishes an electric connection between the plurality of to-be-analyzed sub-blocks so as to provide a circuit configuration equivalent to the to-be-analyzed block, and finally outputs a modified netlist (D2) defining a new circuit to be simulated in which the to-be-analyzed block is replaced with the plurality of to-be-analyzed sub-blocks. A circuit simulation means (3) performs a circuit simulation on the new circuit to be simulated which is defined by the modified netlist (D2). A device for and method of simulation provides a simulation result which reflects the shape of the device in a short period of calculation time.

Abstract: A method for checking on cyclicity of a set of definitions employs a simple, non-computational definition of constructivity and a symbolic algorithm based on the new, simple to implement, formulation for variables with arbitrary finite types. This is accomplished by extending variable type to include the “undeterminable” value ⊥ (read as “bottom”). This formulation is non-computational and easily extensible to variables with any finite type. The formulation also handles definitions of indexed variables in the same manner. The set of definitions is then checked to determine whether any of the variables assume the value is ⊥.

Abstract: A method and system update a VHDL technology library (306) to incorporate correlated delay values by reading the VHDL technology library (306), inserting a tpd_super_rise_time generic declaration and a tpd_super_fall_time generic declaration for every VHDL gate model in the VHDL technology library (306), initializing other generic variables in every VHDL gate model in the VHDL technology library to an equation representing a correlation policy; and outputting an updated VHDL technology library. Then, the method and system bind correlated delay constants in a 3-dimensional variable data array structure to a VHDL technology library (306) using a VHDL package embedded with the correlation delay data.

Abstract: A method for simulating an array of flip flops including metastable effects. The method can also be used for synthesis. For simulation, a first set of values representing input values for a first rank of flip flops in the array is received. The first set of values includes a bit value for each flip flop in the first rank. An input for each flip flop in a second rank is computed by selecting between a bit value from the first set of values and a bit value from a second set of values, wherein the second set of values represents values previously held in the first rank. Each flip flop in the second rank thus receives a bit value from either the first set or the second set of values. A metastable boundary is thereby simulated between the first and second ranks of the array.

Abstract: A method and system select delay values from a VHDL standard delay file that correspond to an instance of a logic gate in a logic model. Then the system collects all the delay values of the selected instance and builds super generics for the rise-time and the fall-time of the selected instance. Then, the system repeats this process for every delay value in the standard delay file (310) that correspond to every instance of every logic gate in the logic model. The system then outputs a reduced size standard delay file (314) containing the super generics for every instance of every logic gate in the logic model.

Abstract: A modeling method and a simulation method enable a circuit board to undergo modeling without deterioration of simulation precision while describing with no matrix shape. A circuit simulator analyzes power/ground noise of a circuit board with single current change source. A process regards the circuit board as an aggregate of thin doughnut boards of concentric circle shape with the current change source as the center, subsequently, approximating the aggregate of the doughnut boards to be an aggregate of rectangular boards with respective circumferences of the doughnut boards as widths and respective cut-lengths of the same as lengths, then forming respective transmission line models taking respective rectangular boards of the aggregate of the rectangular boards as the transmission line, thus connecting respective transmission line models in series to make it a simulation model of the circuit board.

Abstract: Method and apparatus for detecting and analyzing effects of noise in a digital circuit that arises from a coupling of signals produced by switching of a first gate and a second gate in a timed relationship. Where each of a first gate and a second gate can switch within a selected switching time interval, the gate switching effects are combined and the second gate output signal is analyzed with reference to the first gate input signal. Otherwise, the gate switching effects are not combined. When the second gate output signal satisfies at least one of three criteria, this condition is interpreted as indicating that the second gate permits propagation of a noise pulse produced at the first gate.

Abstract: A mechanism is disclosed for recognizing and functionally abstracting a column of memory cells. According to one embodiment, a column of n (where n is an integer greater than 1) memory cells is identified in a description of a circuit. One of the n memory cells is selected as a representative memory cell. Then, the column of n memory cells is represented as a single-memory-cell column comprising the representative memory cell. The column is thereafter functionally abstracted to derive a logic-level representation of the memory cell. After that is done, n−1 additional instances of the logic-level representation are generated. In this manner, the column of n memory cells is functionally abstracted as a column of n logic-level representations of the representative memory cell.

Abstract: A co-simulation design system that runs on a host computer system is described that includes a hardware simulator and a processor simulator coupled via a interface mechanism. The execution of a user program is simulated by executing an analyzed version of the user program on the host computer system. The analysis adds timing information to the user program so that the processor simulator provides accurate timing information whenever the processor simulator interacts with the hardware simulator.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence.

Abstract: In a profile extraction method, a long channel profile is first extracted through an initial profile generating stage and a long channel profile extraction stage. In a following two-dimensional profile extraction stage, a two-dimensional channel profile extraction stage and a source/drain profile extraction stage are repeated to extract an optimized two-dimensional channel profile and an optimized source/drain profile. In the two-dimensional channel profile extraction stage, a two-dimensional channel profile is extracted from the gate length dependency of the threshold voltage. In addition, in the source/drain profile extraction stage, a source/drain profile is extracted from the substrate bias voltage dependency of the threshold voltage—gate length characteristics.

Abstract: A method and system for optimizing the execution of a collection of related modules by eliminating redundant modules from the collection. The collection of modules represent a set of related simulation experiments and are organized as generations of related module sequences having execution interdependencies. The method eliminates redundant modules in the collection by redefining execution interdependencies among the modules. Groups of equivalent modules are formed by comparing the modules within each generation to each other to determine which modules are equivalent. Modules having equivalent execution prerequisites and which will produce the same output given the same input are considered equivalent. In each group of equivalent modules, a single “target” module is selected to substitute for the others in the module execution sequences, and execution interdependencies are redefined to effect the substitution.

Abstract: Techniques and systems for analysis, diagnosis and debugging fabricated hardware designs at a Hardware Description Language (HDL) level are described. Although the hardware designs (which were designed in HDL) have been fabricated in integrated circuit products with limited input/output pins, the techniques and systems enable the hardware designs within the integrated circuit products to be comprehensively analyzed, diagnosed, and debugged at the HDL level at speed. The ability to debug hardware designs at the HDL level facilitates correction or adjustment of the HDL description of the hardware designs.

Abstract: In a method of extracting parameters of a diffusion model from object parameters to be used in a process simulation of a semiconductor manufacturing process, classifying the object parameters into a first through an N-th (N being a natural integer not smaller than 2) groups, the first group being used for classifying thereinto the most fundamental physical and least model-dependent parameters, the N-th group being used for classifying thereinto the least fundamental physical and most model-dependent parameters, and extracting successively the classified parameters in the first through the N-th groups in the order from the first to the N-th group.

Abstract: Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state.

Abstract: A circuit analyzing device comprises a wiring model information extracting section for generating wiring model information for each wiring of a circuit, a circuit simulation section for analyzing waveform propagation characteristics of each wiring model information that has been extracted by the wiring model information extracting section, a spectrum characteristic information calculating section, a linear simulation section, and an S parameter information calculating section.

Abstract: An image is used to diagnose an electric circuit having a multiplicity of elements. The image includes a network graph and a system of equations. The network graph contains dynamic elements for which voltage values can be preset. In order to handle such defaults correctly, statements are made to indicate the dynamic elements for which no values can be preset, and a subsidiary network graph is established in which the dynamic elements of the network graph are replaced by suitable current sources and by voltage sources. A DC-solvable system of equations is produced using the information from the network graph thus modified. The solution of the system of equations thus obtained corresponds to the defaults for the initial value of the original system.

Abstract: A hardware acceleration system for functional simulation comprising a generic circuit board including logic chips, and memory. The circuit board is capable of plugging onto a computing device. The system is adapted to allow the computing device to direct DMA transfers between the circuit board and a memory associated with the computing device. The circuit board is further capable of being configured with a simulation processor. The simulation processor is capable of being programmed for at least one circuit design.

Abstract: A simulation apparatus configured to estimate properties of a semiconductor device, comprising: a first calculating part configured to calculate a first value corresponding to a prescribed physical property value by taking a prescribed physical quantity into consideration, with regard to at least a partial region of said semiconductor device; a second calculating part configured to calculate a second value corresponding to said physical property value without taking said physical quantity into consideration, with regard to at least a partial region of said semiconductor device, and a visualizing part configured to display, in a prescribed form, a correlation between said first and second values.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: In a CAD-data management system for managing a plurality of types of CAD data: a plurality of CAD-data processing units are capable of processing a plurality of predetermined types of CAD data, respectively: a processing-request generation unit receives a manipulation input designating CAD data of one of the plurality of types, and generates a processing request corresponding to the manipulation input and being directed to one of the plurality of CAD-data processing units which is capable of processing CAD data of the one of the plurality of types; and a linkage processing unit executes processing defined in a function in conjunction with the one of the plurality of CAD-data processing units, where the function is predefined corresponding to the processing request.

Abstract: In a circuit simulation system, a simulator and part of device models and circuit models are stored in a server on the Internet, a user sends arbitrary circuit data to the server, the server carries out calculation using the circuit data received from the user and the device and circuit models stored therein, and then the server returns the results of calculation to the user.

Abstract: A method of synthesizing a circuit employs a technology parameter extraction circuit which is synthesized with constraints and simulated to derive values of performance parameters, and then, based on the derived values, a predetermined high-level circuit description of a second circuit is modified and then synthesized using the same constraints. Optional steps include the creation and substitution of a sub-circuit model to permit correct simulation, or substitution of an alternative sub-circuit to synthesize a second circuit that cannot otherwise be synthesized directly.

Abstract: A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (“SOI”) technology. The present invention uses a static noise analysis to evaluate an integrated circuit's response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.

Abstract: A distributed simulation system is described which is agnostic to the simulator program used in each node. That is, different nodes may include simulator programs which differ from each other (e.g. the instruction code comprising one of the simulator programs differs from the instruction code comprising another one of the simulator programs). For example, the different simulator programs may employ different event schedulers, if the different simulator programs are event-based, in one embodiment. As another example, the different simulator programs may be a mix of event-based and cycle-based simulators.

Abstract: A distributed simulation system is provided in which timesteps may be divided into a first phase (referred to as the zero time phase herein) and a second phase (referred to as the real time phase herein). In the first phase, each distributed simulation node in the system may process one or more received commands without causing the simulator to evaluate the model in that distributed simulation node. In the second phase, each distributed simulation node may cause the simulator to evaluate the model in response to a command supplying one or more signal values to the model. In one embodiment, the second phase may iterate the evaluation of the model for each command received which supplies signal values. Each iteration may optionally include transmitting a command including the output signal values produced by the model during that iteration.

Abstract: A data processing apparatus processes input data and outputs the processed data. The data processing apparatus includes a first processing section including a real-time learning section for learning in real time a processing method by which the input data and the output data corresponding to the input data are evaluated and the input data is processed according to the evaluation such that the output data is improved as time elapses; and a data processing section for adaptively processing the input data according to the processing method learned by the real-time learning section and outputting the output data; and a second processing section for processing preceding input data which has been input in time prior to focused input data which is processed by the first processing section, according to the focused output data corresponding to the focused input data and the evaluation of the focused output data to output the preceding output data corresponding to the preceding input data.

Abstract: A tool for automatically generating a reduced size circuit model including inductive interaction properties is provided. Such inclusion of inductive properties in the reduced size circuit model allows for a more complete and accurate circuit model than those created by conventional methods. Further, a technique for automatically generating a reduced size circuit model including inductive properties that uses less memory space and operates faster than conventional methods is provided.

Abstract: The present invention provides a system and method that provides a model that simulates response of a multi-port passive circuit over a broadband frequency range. Briefly described, one embodiment comprises determining a plurality parameters of a model corresponding to the multi-port passive circuit, determining a plurality of pole-residue-eigenvalues associated with the determined parameters, identifying at least one pole-residue-eigenvalue having a magnitude less than zero, changing a value of the at least one identified pole-residue-eigenvalue and recalculating at least one of the parameters after the setting the identified pole-residue-eigenvalue to at least zero.

Abstract: A novel test structure is described which can be used to accurately measure on-wafer impedances. For example, accurate measurements of the parasitic capacitances inside active devices such as Field Effect Transistors or the capacitance of interconnect lines with either the substrate or with each other can be made. The test technique involves frequency sweep S-parameter power measurements made in the range of 50 MHz to about 20 GHz. One or more identical copies of the DUT are connected on the wafer with one or more on-wafer inductances which are usually lumped, to form a two port circuit. The circuit is essentially a filter operating in the frequency range of 50 MHz to 20 GHz. Although filter circuits are normally designed to provide a flat response in the pass and stop bands, with as sharp a skirt as possible, the objective in designing this test circuit is to design a filter response with sharp inflection points that are uniquely dependent on the reactances that comprise the filter circuit.

Abstract: A method for determining compliance with design specifications is provided. In accordance with the method, a product is provided which is characterized by k parameters, k≧2, wherein, for n=1 to k, the nth parameter has a design specification PnDesign and an actual value of PnActual, and wherein dn=PnDesign−PnActual. The value of Δ Actual = [ ∑ n = 1 k ⁢   ⁢ d n 2 ] 1 / 2 is then determined. If &Dgr;Actual≦&Dgr;Design, where &Dgr;Design is the total design tolerance for the product, then the product is deemed to comply with design specifications.

Abstract: The present invention provides a method and apparatus for evaluating nodes in an integrated circuit to determine whether or not networks containing the nodes meet certain design criteria. The method and apparatus of the present invention are embodied in a rules checking system which evaluates the nodes in the integrated circuit to determine whether or not the networks in the integrated circuit comply with the design rules. Compliance with any particular rule is verified by performing one or more checks on the particular node being evaluated. Some checks require less time to perform than others. In some cases, the result of a single check can provide a determination as to whether or not the network containing the node being evaluated complies with the rule associated with the particular check. Furthermore, some checks are less expensive in terms of the amount of time required to perform them than other checks.

Abstract: A system and method which reduce a network cost of a domino circuit. The network costs of domino circuits can be reduced by utilizing the methods and systems disclosed. The domino circuit is represented as a mixed integer linear program. The mixed integer linear program is solved to determine an implementation that includes determining a final phase assignment that reduces the network cost.

Abstract: Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.

Abstract: A MOSFET simulation method for calculating a characteristic value of a MOSFET to be simulated by first numerically calculating the electric potential, electron density, hole density, and mobility inside the MOSFET from simulation conditions including various parameters of the MOSFET, and then using the electric potential, electron density, hole density, and carrier mobility is provided.

Abstract: A circuit comprising a plurality of gates and a plurality of control circuits. The plurality of gates may each have an output connected to an input of a next gate of the plurality of gates. The plurality of control circuits may be connected to a second input of one or more gates of the plurality of gates. The plurality of control circuits may simulate switching.