Abstract: The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.

Abstract: A network map is determined, either in the operating direction from the feed circuit to the load in the load circuit, or backward on the basis of the loads in the load circuit to the data for the feed circuit. The feed circuit and the load circuit are coupled to a virtual interface, at which secondary distribution panels can be interconnected. The schematic procedure, in conjunction with appropriate computation rules and visualization in a network map that is obtained, allows the configuration process to be carried out even by those who are unskilled.

Abstract: A method of circuit simulation of an overall circuit including at least one nonlinear component and a plurality of fixed linear components. The process begins by obtaining a netlist for the overall circuit. Next, one or more of the individual nonlinear components from the netlist are precharacterized. Generally the precharacterization is performed in advance of the circuit simulation and the results are stored in a table. The overall circuit is broken into one or more subcircuits. The number and size of the subcircuits will depend on the circumstances. The nonlinear components are substituted with equivalent linear components based on the precharacterization. A simulation matrix is built. Generally the matrix is carefully partitioned to reduce the number of calculations. A simulation is run for each of the subcircuits. Finally, the subcircuit simulations are combined to form the overall circuit simulation.

Abstract: Briefly, a system and a method of formal verification and failure analysis and rectification of models or designs, e.g., VLSI designs, of processors, circuits and logical systems. Embodinents of the system may include a multi-value annotation scheme for annotating different types of values of signals, and a post-annotation scheme for further analysis based on the annotated values. Some embodiments of the invention may optionally include a generator of counter-examples of a given length.

Abstract: The check system comprises the steps of: computing the optimum position and the optimum capacitance value of the bulk capacitor on a wiring printed circuit board mounting an IC which is an object of checkup, using simple mathematical expressions; determining if an actual capacitance value and an actual position of the bulk capacitor tentatively designed are nearly equal to the optimum value and optimum position computed; determining if the tentatively designed capacitance value of the bulk capacitor exceeds a value of a total sum of capacitance values of decoupling capacitors multiplied by a predetermined constant; and if the optimum conditions are not satisfied, displaying appropriate instructions to modify the tentative design value and position of the bulk capacitor to coincide with the optimum value and position.

Abstract: A fast transient simulator (71) of SOI MOS circuits uses fast and accurate SOI transistor table models (FIGS. 18, 19). The simulator uses a representation of a circuit with partitions (130). Each of partitions (130) is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage (Vy), the simulator (71) implements a transformation and uses body charge (Uy) as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models (FIGS. 18, 19) results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

Abstract: Disclosed are methods and apparatus for characterizing board test coverage. In one method, potentially defective properties are enumerated for a board, without regard for how the potentially defective properties might be tested. For each potentially defective property enumerated, a property score is generated. Each property score is indicative of whether a test suite tests for a potentially defective property. Property scores are then combined to characterize board test coverage for the test suite.

Abstract: Test benches, simulations, and scripts are invoked in parallel for testing multiple points in a circuit being synthesized in an Analog Mixed Signal environment. A simulation system for simultaneously optimizing performance characteristics in circuit synthesis uses a set of design parameters. At least one circuit model is used to incorporate the set of design parameters, each circuit model adapted to model a portion of the circuit pertaining to a performance characteristic. At least one analysis test bench is then connected to each circuit model. Each analysis test bench is adapted to model circuitry external to the circuit and control the type of analysis to be performed for each performance characteristic of the circuit.

Abstract: In an inventive circuit simulation method, simulation is performed utilizing a circuit simulator, based on a netlist prepared using mask layout data for a circuit, and parameters obtained from measurement data concerning the characteristic of each transistor. The parameters are extracted from the measurement data based on not only the transistor size but also a stress applied to the transistor. Therefore, the circuit simulation can be performed with precision and accuracy never before possible, in consideration of a change in the characteristic of the transistor which is caused by the stress applied thereto.

Abstract: A method and apparatus for evaluating an integrated circuit design to determine whether a pass FET is part of a RAM cell structure in the integrated circuit design. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a pass FET in the integrated circuit is part of a RAM cell structure of the integrated circuit. The rules checker program of the present invention evaluates each pass FET which is channel-connected at one of its terminals to a latch node and determines whether that pass FET is channel-connected at one of its other terminals to the drain or source terminal of at least one other pass FET. If so, the pass FET being evaluated is part of a RAM cell structure. In accordance with the preferred embodiment of the present invention, the rules checker program evaluates nodes in an integrated circuit to detect latch nodes.

Abstract: A placement tool that may import and export cell substitution and/or cell selection lists. The cell substitution and/or cell selection lists may be used by the placement tool to substitute and/or modify the placement design database, rather than the original schematic or behavioral database. This may eliminate the need to re-synthesize the circuit design during each design iteration. The present invention further contemplates providing a reset feature which may reset the circuit design database to a previous state, if desired.

Abstract: A method and system for performing simultaneous tests and avoiding task collisions using a hardware description language includes designating a timeslot for one or more of the simultaneous tests, associating the designated timeslot with one or more of the tasks to be performed in a test, determining if the designated timeslot is available before executing the tasks associated with timeslots and executing the tasks when the designated timeslots become available.

Abstract: A method for “match-delay” buffer insertion is provided to add delays at a node without changing the input capacitance of the node as seen by the upstream node. In one embodiment, a method for inserting a delay in a node in an electrical design associated with a logic gate includes: adding the delay at the node by adding a new logic gate before the node where the new logic gate is the same cell type as the logic gate and is positioned near the logic gate. The method may further include: determining if the delay can be added by adding a new logic gate before the node, and if a new logic gate cannot be added before the node, adding the delay by adding a new logic gate after the logic gate where a combination of the logic gate and the new logic gate giving the delay to be added.

Abstract: A circuit, gate, or device parameter simulation includes data on the initial conditions of manufacture, including illumination conditions on a stepper, material parameters for processing conditions, and chip layout. Optical effects and processing tolerances may be accounted for in the simulation of the final device performance characteristics. The circuit, gate, or device parameter simulation may incorporate optical proximity code software. Simulated active and passive components are generated by the circuit, gate, or device parameter simulation from the simulated patterned layers on the substrate. Feedback may be provided to the circuit, gate, or device parameter simulation to optimize performance.

Abstract: An aspect of the current invention is directed to a method for modeling behavior of a non-linear component with a first interconnect line in a system of a plurality of interconnect lines. The method contemplates modeling an interconnect lines as a plurality of segments. Each of the segments of the interconnect line are coupled together to form the interconnect line. A non-linear component is modeled as coupled to a line segment. The line segment has an electric coupling to the other line segments, possibly on different interconnect lines. A signal associated with the first interconnect line is precharacterized. The signal is indicative of the output of the non-linear component on the line segment. The signal is then input into a linearized simulation of the system of interconnect lines.

Abstract: The semiconductor device manufacturing system of the present invention comprises: insulating film determination unit for determining whether an insulating film is present on the substrate surface or not; in-insulating-film impurity concentration extraction unit for extracting the concentration of an impurity contained in the insulating film on the substrate surface; diffusion parameter determination unit for determining diffusion parameter values constituting the diffusion equation as a function of the concentration of the impurity contained in the insulating film; and in-substrate impurity profile extraction unit for extracting the impurity profile information in the substrate by solving the diffusion equation in which the diffusion parameter values are introduced.

Abstract: A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user.

Abstract: A method for calibrating a software model for a given structure of interest for a variable imposed by an adjacent structure. First determine the spatial extent of the variable imposed by the adjacent structure. Then assign a value to the spatial extent, which varies as a function of distance from the adjacent structure to the given structure. Finally, attach that value to the model of the given structure.

Abstract: A method and apparatus for optimizing production yield and operational performance of integrated circuits is provided. A nominal operating voltage is used to categorize integrated circuits into a plurality of performance categories, and the nominal operating voltage is adjusted for each performance category to optimize the yield within that performance category. Integrated circuits may be operated at different operating rates according to their performance categories. The operating rates of an integrated circuit may be controlled by programming a clock register for the integrated circuit. Correct programming of the clock register may be assured by programming a one-time-programmable device. A one-time-programmable device may also be used to program the nominal operating voltage once the optimal nominal operating voltage has been determined. A diagnostic program may be used to select optimum performance parameters for an integrated circuit.

Abstract: A fast simulation method for single and coupled lossy transmission lines is based on triangle impulse responses. The method is used in simulating systems which can consist of large number of lossy transmission lines with frequency-dependent parameters which are placed in a high-speed IC package design.

Abstract: The present invention presents methods for modeling the high frequency and noise characterization of MOSFETs. The models may be readily implemented as part of a SPICE or other simulation in a design flow. In particular, this invention is capable of providing a sub-circuit representation of a MOSFET that can accurately predicate a MOSFET's low frequency, high frequency, and noise characterizations. An interface is described through which a user may simultaneously optimize all of these characterizations. Further, methods are presented for building models that can predicate the variations in MOSFETs due to manufacturing processes and generate a corresponding corner model.

Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A method for exploring the behavior of a design model, the method including the steps of providing a design model represented as a Finite State Machine (FSM). The method further includes the step of providing a path specification of interest. The method further includes the step of exploring the behavior of the design in order to find and present a scenario in the design that meets the path specification.

Abstract: A technique for translating design test bench generated signals into an Automated-Test-Equipment compatible format using existing digital pattern conversion tools. The technique uses sigma-delta modulation technology to allow conversion of analog and mixed signal stimuli into digital representations that can be converted for use in the target tester using existing digital pattern conversion tools.

Abstract: The invention concerns a method for the automatic recognition of simulation configurations of integrated circuits under design comprising at least two components connected to one another directly or indirectly, for the functional verification of the circuits through simulation tests, characterized in that it comprises:

Abstract: When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Abstract: A system and method for automated design verification. A test bench stimulates a simulated design with test vectors. A coverage analysis tool monitors output data from the simulated design and identifies portions of the simulated design that remain to be tested. A test generator produces and sends test vectors to the test bench which exercise (i.e., test) the portions of the simulated design that the coverage analysis tool has indicated still remain untested. In the method, a first step executes a simulated design on a test bench. A second step interprets the simulated design as if this design were a state diagram composed of a set of basic blocks interconnected by transition arcs. A third step generates test vectors to exercise some of the basic blocks and transition arcs. A fourth step reports the basic blocks and transition arcs which have not been tested. A fifth step generates a new set of test vectors to exercise the as yet untested basic blocks and transition arcs.

Abstract: A high-level synthesis method is provided for synthesizing a register transfer level logic circuit based on a behavioral description in which processing behaviors are described. The method includes the steps of extracting information on a bus connection resource from the behavioral description, storing the information on the bus connection resource in a bus connection resource database, referencing the bus connection resource database, referencing a bus protocol library having a preloaded bus protocol, and automatically generating a target interface circuit based on a result of each of the bus connection resource database referencing step and the bus protocol library referencing step.

Abstract: An apparatus for, and method of, modeling a time-varying system and a computer-readable storage medium containing the apparatus or the method. In one embodiment, the apparatus includes: (1) a transfer function generator that develops, for the system, a linear, time-varying transfer function of a particular order and having separate scales corresponding to time variations in the system and an input thereto and (2) an approximator, coupled to the transfer function generator, that approximates the transfer function to yield a model of an order lower than the particular order.

Abstract: A process for processing a circuit design. One or more critical design paths of the circuit design are determined. These paths may for example be determined relative to timing and/or current utilization. Design elements of the paths may be grouped by type (e.g., FETs, wires). The circuit design may be optimized by processing a reduced set of design elements as determined by the critical paths and grouping. Optimization may include modifying FET design element width, or a routing path of a wire design element, along a critical path of the design, and comparing the new optimization relative to preselected design goals such as timing and power consumption.

Abstract: The present invention provides a method and computer readable medium with program instructions for automatically verifying bus transactions. The method includes: parsing a parameter code for the bus transactions, wherein the parameter code comprises a plurality of expected parameter values for the bus transactions; automatically integrating the parsed parameter code into a checking program; and automatically executing the checking program, wherein the checking program compares the plurality of expected parameter values with a plurality of actual parameter values for the bus transactions. The bus transaction verification method in accordance with the present invention automates the coding of expected parameter values for each test case into a checking program and automates the execution of the checking program, where the checking program compares the expected parameter values with the actual parameter values.

Abstract: The present invention presents techniques for considering whether the effects of cross-talk coupling and other noise exceed the noise tolerance of a circuit. One aspect of the present invention uses a set of parameters to represent this noise. An exemplary embodiment uses a triangle or trapezoidal approximation to a glitch based on a set of parameters: the peak voltage value, the width, the leading edge slope and the trailing edge slope. These values are then used as the input of a library to look up the corresponding noise tolerance parameter set values. In a variation, a set of formulae can provide the noise tolerance parameter set values. In an exemplary embodiment, the noise tolerance parameter set is taken to include the minimum peak value for the noise to be possibly harmful and the minimum width value for the noise to be possibly harmful.

Abstract: A unified simulation system is disclosed including multiple core design files, a control structure, a define file, and a compiler module. Each of the core design files includes a description of a corresponding core (i.e., functional block or unit) of an integrated circuit. The control structure associates each of multiple simulation levels with one or more of the core design files. The define file defines an active one of the multiple simulation levels. The compiler module uses the define file to determine the active simulation level, uses the control structure to determine the one or more core design files associated with the active simulation level, and uses the one or more core design files associated with the active simulation level to generate a simulation model of an integrated circuit. A user of the unified simulation system creating the define file can determine the simulation level achieved during subsequent simulation of the simulation model.

Abstract: An online Gaussian mixture learning model for dynamic data utilizes an adaptive learning rate schedule to achieve fast convergence while maintaining adaptability of the model after convergence. Experimental results show an unexpectedly dramatic improvement in modeling accuracy using an adaptive learning schedule.

Abstract: A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

Abstract: A method and apparatus for validating SoC (system-on-a-chip) design with high accuracy and speed and low cost. The [apparatus allows to use a] method [which] includes the steps of verifying individual cores to be integrated in an SoC by evaluating a silicon IC having a function and structure identical to that of each core constituting the SoC with use of test patterns generated based on simulation testbenches produced through a design stage of the cores; verifying interfaces between the individual cores, on-chip buses of the cores and glue logic by using the silicon ICs and simulation testbenches [developed by an SoC designer] and FPGA/emulation of the glue logic; verifying core-to-core timings and SoC level timing critical paths; and performing an overall design validation by using the silicon ICs and simulation testbenches of [an] the overall SoC [and application runs].

Abstract: A method for designing and mapping a power-bus grid in an integrated circuit. A floor plan is created by mapping wire segments of the power-bus grid to various metal layers of the IC core. Power zones which specify the current consumption of analog, digital, and memory block regions are also mapped to the IC core. A netlist of the floor plan design is generated and simulated, with the simulation returning current density and a voltage drop values in the wire segments with respect to the power zones. Calculated current density and voltage drop values are analyzed using a color map to indicate the current density and voltage drop levels of the wire segments. Power-bus wire segments are displayed in colors matched to the current density and voltage drop levels in the color map, helping the designer identify potential electromigration and voltage drop problems. The floor plan design can be modified if the calculated density and voltage drop values indicate potential electromigration or voltage drop problems.

Abstract: A system and method for testing the quality of a simulation model for the DUT (device under test) through temporal coverage of the testing and verification process. Temporal coverage examines the behavior of selected variables over time, according to a triggering event. Such a triggering event could be determined according to predefined sampling times and/or according to the behavior of another variable, for example. This information is collected during the testing/verification process, and is then analyzed in order to determine the behavior of these variables, as well as the quality of the simulation model for the DUT. For example, the temporal coverage information can be analyzed to search for a coverage hole, indicated by the absence of a particular value from a family of values.

Abstract: With highly heterogeneous groups or streams of minerals, physical segregation using online quality measurements is an economically important first stage of the mineral beneficiation process. Segregation enables high quality fractions of the stream to bypass processing, such as cleaning operations, thereby reducing the associated costs and avoiding the yield losses inherent in any downstream separation process. The present invention includes various methods for reliably segregating a mineral stream into at least one fraction meeting desired quality specifications while at the same time maximizing yield of that fraction.

Abstract: A comprehensive methodology for statistical modeling and timing of integrated circuits and integrated circuit macros is disclosed with a means for efficiently computing the sensitivities of coefficients of gate delay models to sources of variation. These sensitivities are used to determine the probability distribution of the delay and slew of each gate and wire, as well as the correlations between these delays and slews. Finally, these timing models are used in an inventive statistical static timing analysis method to predict the statistical performance of an integrated circuit or integrated circuit macro.

Abstract: Averilog-HDL source at the register-transfer level (RTL) is converted into a programming language executable on computer. Constructed in an analyzing of elements is a data structure corresponding to the elements of the verilog-HDL source. Created in an analyzing of a data-flow are a first data flow from a state register and a second flow from data-path register. Reconstructed in a reconstructing of a control-structure is the first data flow. Reconstructed in a reconstructing of a data-path is the second data flow so that the reconstructed second data is constituted only by circuitry operating in each state of the control structure. Each reconstructed data flow is mapped in each state of the control structure in a combining of the control-structure/data-flow, to output an behavior-level intermediate language. The intermediate language is converted into a programming language in a generating of an object-code.

Abstract: A circuit simulator is provided for simulating the operation of a circuit in the time domain by accounting for the physical fluctuation (noise) in the time domain. Each of the components (14) in the matrix (10) has associated therewith an active current generator which can be simulated by the simulator in the time domain. In parallel with this active current generator, a stochastic (random) process current generator is provided. This stochastic current generator for each element will utilize a Gaussian random number generator (with 0 mean and a variance equal to 1) that is scaled by the standard deviation (square root of the variance) of the physical noise process that exists within the device. Additionally, this Gaussian random number generator is scaled by a factor that accounts for the time step or discrete operation of the noise simulator.

Abstract: A system for modeling a lead-acid battery is disclosed. A system for modeling a lead-acid battery is also disclosed. An equivalent circuit model of a battery comprising an impedance circuit for simulating the electrochemical charging and discharging of the battery is also disclosed. A circuit for modeling a lead-acid battery having an RC network for simulating the impedance of cells of the battery is also disclosed. A method of modeling a lead-acid battery with an electrical circuit comprising a charging circuit, an electrochemical reaction circuit, and a voltage drop circuit is also disclosed. A method for constructing an equivalent electrical circuit model of a lead-acid battery is also disclosed.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: The invention includes combinatorial logic networks emulating ROMs (RECLNs) and an emulation method for ROMs, as well as emulating synchronous ROMs with RECLN's coupled to synchronizing interfaces. The invention includes methods and apparatus generating synthesizable RECLN descriptions, as well as, circuit descriptions, netlists, circuit layouts, mask sets, unpackaged integrated circuit wafers, integrated circuits, and systems products using the synthesizable RECLN descriptions and products derived therefrom. The invention also includes method and apparatus for doing business involving generation of synthesizable RECLN descriptions and/or the above mentioned derived products. The invention also includes creating installation mechanisms for synthesizable RECLN generation methods to create systems generating synthesizable RECLN descriptions.

Abstract: The present disclosure relates to a method for estimating input voltages to transistors in a transistor network. The method includes identifying an input signal, to transforming a netlist, identifying input parameters and simulating a plurality of interconnected transistors. The method also can include determining if a signal is internal to a signal net, disconnecting the driver of the signal net and estimate the load based on the load of the signal net. The method also relates to circuits, specifically integrated circuits, produced by the method taught. The method is particularly applicable to the design of circuits such as VLSI integrated circuits. The disclosure also relates to electrical products such as computer systems or integrated circuit boards including a circuit designed by the method taught.

Abstract: The invention allows the inclusion of cross-talk coupling and other noise in circuit simulation by considering the details a resultant glitch in more detail than just its peak value. A set of parameters represents the noise, with an exemplary embodiment using a triangle approximation to a glitch based on a set of three parameters: the peak voltage value, the leading edge slope and the trailing edge slope. These values are then used as the input stimulus to a given cell instance in the network in which the result propagated noise values, also in a triangle approximation, are determined by a simulation. The results can be stored as a library so that, given the parameters of the input noise and the particular cell, a simulation can determine the propagated noise through a look-up process. To reduce the space requirements of the library, the dimensionality of the look-up tables can be reduced through the introduction of a set of auxiliary functions to offset error from this reduction.

Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.

Abstract: Apparatus and methods for integrated circuit (IC) design, including management of the configuration, design parameters, and functionality of a design in which custom instructions or other design elements may be controlled by the designer. In one exemplary embodiment, a computer program rendered in an object-oriented language implementing the aforementioned methods for designing user-customized digital processors is disclosed. Design iteration, component encapsulation, use of human-readable file formats, extensible dynamic GUIs and tool sets, and other features are employed to enhance the functionality and accessibility of the program. Components within the design environment comprise encapsulated objects which contain information relating to interfaces with other components in the design, hierarchy, and other facets of the design process.

Abstract: A process for efficiently computing moments in an interconnected circuit begins by partitioning the circuit into sets of line-like two-port circuits. Next, capacitors are converted to equivalent current sources and inductors are converted to equivalent voltage sources. From a first port, any connected voltage source which is present in line is added to the port voltage source. Then, that voltage source combined with the connected resistor and the Thevenin equivalent circuit is converted to a Norton equivalent circuit. The current source created from the conversion is added to a current source in the circuit and the Norton equivalent circuit is converted back to a Thevenin equivalent circuit. The process is recursively performed until the opposite port is reached. The moment is then computed from the final Thevenin equivalent circuit by using the voltage and current at the port. The Thevenin-Norton-Thevenin recursive process is then repeated for the opposite port.