Function Generation Patents (Class 708/270)
  • Patent number: 8818771
    Abstract: According to the preferred embodiments, a system or method is provided that involves the programming of a computer or other processing device with a software, hardware or firmware configured to create a processing tool (i.e., referred to herein as a tool box) that can be configured to provide one or more operational function based on new mathematical principles described herein for the purposes of, e.g., synthesizing or analyzing shapes and the like.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 26, 2014
    Inventors: Johan Gielis, Diego Caratelli
  • Patent number: 8819099
    Abstract: A digital signal processor is provided in a wireless communication device, wherein the processor comprises a vector unit, first and second registers coupled to and accessible by the vector unit; and an instruction set configured to perform matrix inversion of a matrix of channel values by coordinate rotation digital computer instructions using the vector unit and the first and second registers.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: August 26, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Mihai Sima, Daniel Iancu, Hua Ye, Mayan Moudgill
  • Patent number: 8805908
    Abstract: An approximation processing method for approximating a point group using a curve or a surface defined by control points includes a step of forming an approximated curve (surface) using control points that retain features of a shape; a first calculation step of calculating a closest point closest to each of the data points on the approximated curve (surface); a second calculation step of calculating an error vector that joins the closest point, obtained in the first calculation step, to the data point; and a third calculation step of calculating a corrected control point by moving each of the control points based on the error vector obtained by the second calculation step. The step of forming an approximated curve (surface) and the first to third calculation steps are repeated to make the approximated curve (surface) respectively approximate the curve (surface) of an object configured by the data points.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: August 12, 2014
    Assignee: National University Corporation Yokohama National University
    Inventors: Takashi Maekawa, Yuu Nishiyama, Masayuki Morioka
  • Patent number: 8768993
    Abstract: A direct current compensation method for S-parameter rational functions reads S-parameters f(sk), which are generated at given frequency sk, from a storage unit. An S-parameter, which is generated at frequency sk=0 is supplemented into the S-parameters f(sk), upon the condition that there is no S-parameter which is generated at the frequency sk=0. An S-parameter ration function is generated according to the S-parameters f(sk). A DC level of the S-parameter rational function is compensated to generate a compensated S-parameter rational function.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: July 1, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Wen-Laing Tseng, Shen-Chun Li, Yu-Chang Pai, Shou-Kuo Hsu
  • Patent number: 8762436
    Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division. A reference frequency value and synthesized frequency value are accepted. In response to dividing the synthesized frequency value by the reference frequency value, an integer value numerator (n) and an integer value denominator (d) are determined, with n/d=I(N/D)=I+N/D=(I+1)?(D?N)/D), and where N/D<1. An accumulator creates a sum of (D?N) and a count from a previous cycle, and creates a difference between the sum and the denominator. The sum is compared with the denominator, and a first carry bit is generated. The complement of the first carry bit is added to a first binary sequence, and the first binary sequence is used to generate a k-bit quotient. The k-bit quotient is subtracted from (I+1) to generate a divisor.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: June 24, 2014
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Do, Simon Pang
  • Patent number: 8751552
    Abstract: Methods for generating complex waveforms, including step functions, impulse functions, and gate pulses are provided, as well as methods for generating modulated waveforms employing a number of known and newly developed modulation formats. The methods of the present invention employ a continuous linear function, wherein all output points are defined. Discontinuities and singularities are eliminated, yet pulses having nearly instantaneous transitions may be achieved. Thus, gate pulses step functions, binary waveforms and the like may all be generated from a single function, where they entire output range of the function is defined over a continuous input domain.
    Type: Grant
    Filed: September 20, 2010
    Date of Patent: June 10, 2014
    Assignee: The Pulse Perfect Corporation, Inc.
    Inventors: Robinson Gaudino Caputo, Luiz Gustavo Varella Figueiredo
  • Patent number: 8732223
    Abstract: A function that represents data points is derived by creating a matrix (e.g., a Hankel matrix) of an initial rank, where the matrix contains the data points. Singular values are derived based on the matrix, and it is determined whether a particular one of the singular values satisfies an error criterion. In response to determining that the particular singular value does not satisfy the error criterion, the rank of the matrix is increased and the deriving and determining tasks are repeated. In response to determining that the particular singular value satisfies the error criterion, values of parameters that approximate the function are computed.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: May 20, 2014
    Assignee: WesternGeco L.L.C.
    Inventor: Can Evren Yarman
  • Patent number: 8694566
    Abstract: This method for decomposing an anharmonic periodic signal, the general form of which may be expressed as x(t)=x0+x1 cos(?(t)), wherein ?(t) is the phase of the signal, is characterized in that it consists of: determining an expression of the phase equation F ? ( ? ) = ? ? ? t , determining an expression of the phase ?(t) as a function of de parameters (r, rk, ?1, pk) measuring the anharmonicity of the signal and its morphology, from p cosn and p sinn functions defined by: p ? ? cos n ? ( t , r ) = ? k = 1 ? ? cos ? ( kt ) ? r k k n ? ? and ? ? p ? ? sin n ? ( t , r ) = ? k = 1 ? ? sin ? ( kt ) ? r k k n .
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: April 8, 2014
    Assignee: Centre National de la Recherche Scientifique
    Inventor: Patrick Hanusse
  • Patent number: 8682950
    Abstract: An input polynomial, in symbolic form, is received, classified, pre-processed, and factored. The input polynomial is classified as a constant, a univariate polynomial, or a multivariate polynomial. Various pre-processing is performed depending on the classification. After the input polynomial is pre-processed, the remaining polynomial is factored using a polynomial factoring algorithm. By pre-processing the input polynomial, the complexity of the polynomial to be factored is reduced, which reduces the computational expense of the polynomial factoring algorithm.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: March 25, 2014
    Assignee: Microsoft Corporation
    Inventors: Xu Yang, Xiaolin Quan, Zhihui Ba, Dongmei Zhang
  • Patent number: 8676872
    Abstract: A recursive method for computing numerical values for mathematical functions includes providing a recursive Taylor series representation of a mathematical function f(x) of a variable x evaluated around a given operating point a. The recursive Taylor series representation includes a plurality of derivative derived terms that include ratios of derivatives of f(x) evaluated at the operating point a. Coefficient data is determined from ones of the derivative derived terms stored in a tangible memory device evaluated at the operating point a over a predetermined range. An approximation for the mathematical function f(x) is computed using the recursive Taylor series representation evaluated with the coefficient data.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: March 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: David Patrick Magee
  • Patent number: 8676871
    Abstract: A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: March 18, 2014
    Assignee: Intel Corporation
    Inventors: Alex Pineiro, Thomas D. Fletcher, Brian J. Hickmann
  • Patent number: 8655935
    Abstract: A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: February 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Mikio Hondou, Ryuji Kan, Toshio Yoshida
  • Patent number: 8655934
    Abstract: A regenerative frequency divider device including a plurality of multipliers, each of which has a first input port, a second input port and an output port; a first combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the multipliers; and a second combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of multipliers. Further, a first output signal generated by the first combiner is coupled to the second input port of at least two of the multipliers; and a second output signal generated by the second combiner is coupled to the second input port of at least two of the multipliers such that a complex signal is fed back to the multipliers performing the down conversion process. The present invention divider CRD can achieve superior output noise floor of ?180 dBc/Hz at multi-GHz frequencies.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: February 18, 2014
    Assignee: General Instrument Corporation
    Inventors: Branislav Petrovic, Maxim Ashkenasi, Andre Basovich
  • Patent number: 8650235
    Abstract: A function generator for a digital system includes a plurality of sub-function generators. Each sub-function generator has an input that receives a respective input value and has an output that provides a respective output value responsive to the respective input value. A case detector receives a system input value and selectively routes at least a first portion of the system input value to the input of at least one selected sub-function generator. The case detector selects the selected sub-function generator in response to at least a second portion of the system input value. The case detector further suppresses transitions of data on the input of at least one non-selected sub-function generator. The case detector further selects the respective output value provided by the at least one selected sub-function generator and provides the selected respective output value as a function generator output value.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: February 11, 2014
    Inventor: Arthur Torosyan
  • Patent number: 8650415
    Abstract: System, methods, and apparatuses produce simulated human physiological waveforms such as electrocardiograph (ECG) and blood pressure signals where the microcontroller and/or digital-to-analog converters may be switched to a lower power-consuming state by programmable instructions and switched on in response to a programmable sleep timer.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: February 11, 2014
    Assignee: PRONK Technologies, Inc
    Inventor: Karl Ruiter
  • Patent number: 8615540
    Abstract: An arithmetic logic unit (ALU) for use within a flight control system is provided. The ALU comprises a first register configured to receive a first operand, a second register configured to receive a second operand, and an adder coupled to the first register and the second register. The adder is configured to generate a sum of the first operand and the second operand and to generate intermediate sums that are used to determine a product of the first operand and the second operand.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: December 24, 2013
    Assignee: Honeywell International Inc.
    Inventors: Jason Bickler, Karen Brack
  • Patent number: 8615537
    Abstract: The invention related to a method for encoding information using non-linear evenly distributed functions, that comprises the following steps for building such a function: selecting a first natural integer n, a first set En of cardinal n, a group G operating on said first set En, a second natural integer q and a second set Eq of cardinal q; defining a set OG of the orbits of the group G operating on vectors of n elements in the set Eq, a function II that, for each vector of the n elements of the set Eq, associates the corresponding orbit and a second function ? allocating to each orbit of the group G a value of the set Eq; evenly distributing into a number q of sections the sums of the cardinals of the orbits of the group; defining a third function F comprising the first and second functions ?oII.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: December 24, 2013
    Assignee: Eads Secure Networks
    Inventor: Marc Mouffron
  • Patent number: 8572144
    Abstract: A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: October 29, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Benjamin Vigoda, Jeffrey Bernstein, Alexander Alexeyev
  • Patent number: 8572143
    Abstract: An output signal is generated from a received input data stream representing a sequence of digital data values. For each group of successive data values in the sequence of data values, a respective waveform pattern is assigned in dependence of the data content of the respective group of successive data values. The output signal is generated by generating the assigned respective waveform patterns corresponding to the input data stream.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: October 29, 2013
    Assignee: Agilent Technologies, Inc.
    Inventors: Thomas Dippon, Clemens Rabenstein
  • Patent number: 8548161
    Abstract: In the field of cryptography there is a need to reduce the time taken to cryptographically transform data text while maintaining the low memory requirements associated with conventional square-and-multiply modular exponentiation. A method of cryptographically transforming data text c comprises the step of generating an integer representation m of the data text c according to m=cd where d is a predetermined exponent. The step of generating the integer representation m includes generating a sequence of intermediate numbers, each intermediate number being based on two or fewer earlier numbers in the sequence. Generating a sequence of intermediate numbers includes retrieving a pre-stored instruction to determine which two or fewer earlier numbers in the sequence a given intermediate number is based on and the functional manipulation of the or each earlier number required to generate the given intermediate number.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: October 1, 2013
    Assignee: NXP B.V.
    Inventor: Bruce Murray
  • Patent number: 8521796
    Abstract: This disclosure relates to setting the iteration count of a Cordic module as a function of a signal characteristic of an input signal provided to the Cordic module.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: August 27, 2013
    Assignee: Infineon Technologies AG
    Inventor: Jianhui Hou
  • Patent number: 8521659
    Abstract: Discovering mixtures of models includes: initiating learning algorithms, determining, data sets including a cluster of points in a first region of a domain and a set of points distributed near a first line extending across the domain; inferencing parameters from the cluster and the set of points; creating a description of the cluster of points in the first region of the domain and computing approximations of a first learned mixture model and a second learned mixture model; determining a first and second probability, generating a confidence rating that each point of the cluster of points in the first region of the domain corresponds to the first learned mixture model and generating a confidence rating that each point of the set of points distributed near the first line correspond to the second learned mixture model, thus causing determinations of behavior of a system described by the learned mixture models.
    Type: Grant
    Filed: August 14, 2009
    Date of Patent: August 27, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Mark Alan Livingston, Aditya Maruti Palepu
  • Publication number: 20130212141
    Abstract: Aggregates are calculated from a data stream in which data is sent in a sequence of tuples, in which each tuple comprises an item identifier and a timestamp indicating when the tuple was transmitted. The tuples may arrive at a data receiver out-of-order, that is, the sequence in which the tuples arrive are not necessarily in the same sequence as their corresponding timestamps. In calculating aggregates, more recent data may be given more weight by a decay function which is a function of the timestamp associated with the tuple and the current time. The statistical characteristics of the tuples are summarized by a set of linear data summaries. The set of linear data summaries are generated such that only a single linear data summary falls between a set of boundaries calculated from the decay function and a set of timestamps.
    Type: Application
    Filed: March 26, 2013
    Publication date: August 15, 2013
    Applicants: Iowa State University Research Foundation, Inc, AT&T Intellectual Property I, L.P.
    Inventors: AT&T Intellectual Property I, L.P., Iowa State University Research Foundation, Inc
  • Patent number: 8484269
    Abstract: Aggregates are calculated from a data stream in which data is sent in a sequence of tuples, in which each tuple comprises an item identifier and a timestamp indicating when the tuple was transmitted. The tuples may arrive at a data receiver out-of-order, that is, the sequence in which the tuples arrive are not necessarily in the same sequence as their corresponding timestamps. In calculating aggregates, more recent data may be given more weight by a decay function which is a function of the timestamp associated with the tuple and the current time. The statistical characteristics of the tuples are summarized by a set of linear data summaries. The set of linear data summaries are generated such that only a single linear data summary falls between a set of boundaries calculated from the decay function and a set of timestamps. Aggregates are calculated from the set of linear data summaries.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: July 9, 2013
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Graham Cormode, Philip Korn, Srikanta Tirthapura
  • Patent number: 8483625
    Abstract: An RF transceiver apparatus comprises transmitter circuitry arranged to convert signals from a baseband frequency to RF transmission frequencies and receiver circuitry arranged to convert signals from RF reception frequencies to the baseband frequency. The transmitter and receiver circuitry each comprise three mixers arranged to convert a signals between the baseband frequency, a first intermediate frequency; a second intermediate frequency that is higher than the transmission frequencies; and a second intermediate frequency to the transmission frequency.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: July 9, 2013
    Assignee: Lime Microsystems Limited
    Inventors: Srdjan Milenkovic, Danny Webster, Ebrahim Bushehri, Ri{hacek over (s)}ard Kurylo
  • Patent number: 8478805
    Abstract: A method is provided for synthesizing signal frequencies using low resolution rational division decomposition in a frequency synthesis device. An integer numerator (n) and an integer denominator (d) ratio is reduced; n/d=IO(NO/DO)=IO+NO/DO=(IO+1)?(DO?NO)/DO, and where NO/DO<1 and NO and DO are integers. NO is reduced; NO=In(Nn/Dn)=In+Nn/Dn=(In+1)?(Dn?Nn)/Dn, where In, Nn, and Dn are integers, and Nn/Dn<1. In, Nn, and Dn are used to create a final numerator divisor. DO is reduced; DO=Id(Nd/Dd)=Id+Nd/Dd=(Id+1)?(Dd?Nd)/Dd, where Id, Nd, and Dd are integers, and Nd/Dd<1. Id, Nd, and Dd are used to create a final denominator divisor. Finally, IO, the final numerator divisor, and the final denominator divisor are used to create a final divisor.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: July 2, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Viet Do, Simon Pang
  • Patent number: 8473536
    Abstract: A method for providing an adiabatic RF pulse that is an inversion or refocusing pulse for a RF pulse sequence is provided. A linear phase frequency profile (Flp(?)) is determined for the adiabatic RF pulse. A quadratic phase is applied to the linear phase frequency profile for the adiabatic RF pulse to obtain F(?), wherein the applying the quadratic phase comprises setting F(?)=Flp(?)eik?2. A polynomial ? is set to equal a Fourier Transform (F(?)). A corresponding minimum phase ? polynomial is determined for the ? polynomial. (?,?) are set as inputs to an inverse Shinnar Le-Roux transform to generate an adiabatic RF waveform. The adiabatic RF waveform is truncated to produce the adiabatic RF pulse, wherein k>0.03?/(?5??p)/(N+1) and k<kmax, where kmax is a value at which the adiabatic RF pulse is truncated at 25% of a maximum RF amplitude.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: June 25, 2013
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Priti Balchandani, John M. Pauly, Daniel M. Spielman
  • Publication number: 20130144832
    Abstract: In the disclosed nondeterministic computing apparatus, a user problem to be solved is translated into an equivalent system of clause polynomial equations (CPEQS) in GF(2). A process for finding an inconsistency in CPEQS is disclosed, which performs elementary equation (or row) operations, such as Gaussian forward eliminations, for each variable v in CPEQS by treating different monomials as different single variables in v-order. The result is examined for two kinds of equations: an inconsistent equation 1=0 and an equation which left-hand side has constant monomial 1 and v occurs in all the other monomials such that v occurs at least once while its right-hand side is 0 to find v=1. To find v=0, a substitution of v with v?1 is performed on CPEQS in advance. If either 1=0, or, x=1 and x=0 simultaneously for some variable x in CPEQS, then CPEQS is inconsistent; otherwise CPEQS is consistent.
    Type: Application
    Filed: December 4, 2011
    Publication date: June 6, 2013
    Inventor: Aizhong Li
  • Patent number: 8417754
    Abstract: Techniques are generally described for generating an identification number for an integrated circuit (IC). In some examples, methods for generating an identification of an IC may comprise selecting circuit elements of the IC, evaluating measurements of an attribute of the IC for the selected circuit elements, wherein individual measurements are associated with corresponding input vectors previously applied to the IC, solving a plurality of equations formulated based at least in part on the measurements taken of the attribute of the IC for the selected circuit elements to determine scaling factors for the selected circuit elements, and transforming the determined scaling factors for the selected circuit elements to generate an identification number of the IC. Additional variants and embodiments may also be disclosed.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: April 9, 2013
    Assignee: Empire Technology Development, LLC
    Inventors: Miodrag Potkonjak, Farinaz Koushanfar
  • Publication number: 20130031151
    Abstract: Methods and apparatus disclosed herein operate, for example, to derive a non-ideal received signal from an ideal signal, to compute, from the non-ideal received signal, at least one probability density function of amplitude and time values representing deviations from the ideal signal, to derive at least one amplitude noise component and at least one timing jitter component from the at least one probability density function, and to generate a non-ideal waveform by applying the at least one amplitude noise component and the at least one timing jitter component to an ideal waveform.
    Type: Application
    Filed: August 6, 2012
    Publication date: January 31, 2013
    Inventor: Timothy Hollis
  • Patent number: 8359345
    Abstract: The use of the ordinary Poisson iterative reconstruction algorithm in PET requires the estimation of expected random coincidences. In a clinical environment, random coincidences are often acquired with a delayed coincidence technique, and expected randoms are estimated through variance reduction (VR) of measured delayed coincidences. In this paper we present iterative VR algorithms for random compressed sonograms, when previously known methods are not applicable. Iterative methods have the advantage of easy adaptation to any acquisition geometry and of allowing the estimation of singles rates at the crystal level when the number of crystals is relatively small. Two types of sonogram compression are considered: axial (span) rebinning and transaxial mashing. A monotonic sequential coordinate descent algorithm, which optimizes the Least Squares objective function, is investigated.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: January 22, 2013
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventor: Vladimir Y. Panin
  • Patent number: 8339295
    Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 25, 2012
    Assignee: Motorola Solutions, Inc.
    Inventors: Geetha B. Nagaraj, Nicholas G. Cafaro, Ralf Hekmann, Robert E. Stengel, Scott Miller
  • Patent number: 8285768
    Abstract: An apparatus for evaluating a mathematical function at an input value is provided. The apparatus includes a device for selecting a mathematical function, a device for inputting a value at which to evaluate the function, a device for identifying an interval containing the input value, the interval being described by at least one polynomial function, a device for retrieving at least one control point representing the polynomial function from at least one look up table, a device for deriving the polynomial function from the control points, a device for evaluating the function for the input value and a device for providing data representing the evaluated function at an output.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: October 9, 2012
    Assignee: Imagination Technologies Limited
    Inventor: Simon Fenney
  • Patent number: 8275819
    Abstract: Methods, apparatus, and articles of manufacture for performing calculations using reduced-width data are disclosed. In particular, an example method determines reduced-width data values associated with generating and evaluating functions. Some of the reduced-width data values are stored within instructions in an instruction memory during a compile phase and retrieved from instruction memory during a runtime phase.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 25, 2012
    Assignee: Marvell World Trade Ltd.
    Inventors: Ping T. Tang, Gopi K. Kolli
  • Publication number: 20120226726
    Abstract: Method and apparatus for processing continuous-time models (CTM) in a digital processing architecture is disclosed. The discrete state-space technique maps the CTM into the discrete-time model (DTM) and stores the states of the system in a sample time independent discrete state space set of matrices. The resulting state-space matrices can be processed in software or directly in hardware. The method disclosed is particularly suited to be used in automatic synthesis algorithms where a digital circuit is generated from an algorithm described in a high level language or model representation such as, for example, data flow or bond graph into a hardware description language (HDL), and the HDL model can be synthesized using system specific tools to generate an application specific integrated circuit (ASIC) or an FPGA configuration.
    Type: Application
    Filed: March 4, 2011
    Publication date: September 6, 2012
    Applicant: KYLOWAVE INC.
    Inventors: Julio C.G. PIMENTEL, Emad GAD
  • Patent number: 8239432
    Abstract: One or more embodiments are disclosed that involve computer implementable techniques for generating simulate-able waveforms without the need for repeatedly including and simulating a full channel model or testing the waveforms on a physical channel. Techniques according to such embodiments the invention comprise simulating the sending of a waveform across a channel and recording deviations from a simulated received waveform, which comprise differences between the ideal waveform as sent and the simulated received waveform. These deviations are then used to create simulate-able waveforms, which include the effects of noise and jitter, without the need for additional channel simulation. As an alternative to using channel simulation, deviations may also be collected from sending a waveform across a physical channel.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Timothy M. Hollis
  • Publication number: 20120130659
    Abstract: Embodiments of the present invention relate to analysis of large data sets using distributed polynomial interpolation. Particular embodiments compile such data sets from a large number of nodes. According to certain embodiments, a node gathers data for a certain time interval, and then approximates the gathered data with a polynomial. The node then sends its data in the form of the polynomial and an identification (ID), to a repository such as a database. For each node the polynomial may be queried from the database, and then the integral for the required interval calculated therefrom. Embodiments of the present invention may be particularly suited to allow real-time analytics of data collected from a large number of electrical power smart meters.
    Type: Application
    Filed: November 22, 2010
    Publication date: May 24, 2012
    Applicant: SAP AG
    Inventor: Leonardo Weiss F. Chaves
  • Patent number: 8176109
    Abstract: A calculating unit for reducing an input number with respect to a modulus, wherein the input number has input number portions of different significances, wherein the input number portions represent the input number with respect to a division number, wherein the modulus has modulus portions of different significances, and wherein the modulus portions represent the modulus with respect to the division number, includes a unit for estimating a result of an integer division of the input number by the modulus using a stored most significant portion of the number, a stored most significant portion of the modulus and the number, and for storing the estimated result in a memory of the calculating unit, and a unit for calculating a reduction result based on a subtraction of a product of the modulus and a value derived from the estimated result from the number.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: May 8, 2012
    Assignee: Infineon Technologies AG
    Inventor: Wieland Fischer
  • Patent number: 8156169
    Abstract: A signal processing method includes a first step of calculating a value indicating a value obtained by multiplying a ratio of the number of times of inputting the input signal having any one of values from p to m, where m is a maximum value of values of input signal which are subject to said signal processing and p is a value smaller than m and not a minimum value of the input signal, within a predetermined period to the number of times of inputting the input signal within the predetermined period, by the variable range of the converted value; and a second step of subtracting the calculated value from a maximum value within the variable range of the converted value or a value near the maximum value, wherein the input signal is converted according to the conversion characteristic specified based on a value obtained by subtraction.
    Type: Grant
    Filed: June 2, 2008
    Date of Patent: April 10, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Izumi Kanai
  • Publication number: 20120072476
    Abstract: An embodiment of the present invention is an identification circuit installed on an integrated circuit for generating an identification bit, comprising a first circuit to generate a first output signal that is based on random parametric variations in said first circuit, a second circuit to generate a second output signal that is based on random parametric variations in said second circuit, a third circuit capable to be operated in an amplification mode and in a latch mode, wherein in said amplification mode the difference between the first output signal and the second output signal is amplified to an amplified value and, wherein in said latch mode said amplified value is converted into a digital signal.
    Type: Application
    Filed: September 17, 2010
    Publication date: March 22, 2012
    Inventors: Marco BUCCI, Raimondo LUZZI
  • Patent number: 8140292
    Abstract: A method of automating a process for controlling a voltage waveform applied to an object is provided. A first waveform for applying to the object is received. A first FFT of the first waveform is calculated. A second waveform for input to the waveform generator is determined based on the first waveform. The determined second waveform is sent to a waveform generator. A third waveform is received that is measured across the object based on a waveform generated by the waveform generator. A second FFT of the received third waveform is calculated. The third waveform is compared with the first waveform to determine a convergence status of the third waveform. If the determined convergence status is not converged, an updated waveform is calculated based on the first FFT and the second FFT and the process is repeated with the updated waveform as the determined second waveform.
    Type: Grant
    Filed: September 18, 2007
    Date of Patent: March 20, 2012
    Assignee: Wisconsin Alumni Research Foundation
    Inventor: Amy Wendt
  • Publication number: 20120059865
    Abstract: An analysis method using a finite element method includes: selecting an analysis domain to be analyzed; dividing the analysis domain into elements as calculation objects; creating a matrix of each element; integrating a general function term as a product of a Galerkin weight function and a general function; creating simultaneous equations, based on the sum of matrices of respective elements and the sum of values obtained by integrating the general function term, and obtaining a numerical solution from the simultaneous equations. In integrating the general function term, the concept of a nodal domain defined based on a result of discretization of a second-order differential term according to a Galerkin finite element method is introduced, and the general function term using a typical value of the element is integrated.
    Type: Application
    Filed: September 1, 2011
    Publication date: March 8, 2012
    Applicant: AISIN AW CO., LTD.
    Inventors: Changcheng SHAO, Toshiya IINUMA
  • Publication number: 20120041728
    Abstract: According to the preferred embodiments, a system or method is provided that involves the programming of a computer or other processing device with a software, hardware or firmware configured to create a processing tool (i.e., referred to herein as a tool box) that can be configured to provide one or more operational function based on new mathematical principles described herein for the purposes of, e.g., synthesizing or analyzing shapes and the like.
    Type: Application
    Filed: June 21, 2011
    Publication date: February 16, 2012
    Inventors: Johan Gielis, Diego Caratelli
  • Publication number: 20120036171
    Abstract: A method and system of converting an ASCII timing report to a timing waveform to evaluate the behavior of an electrical signal in an ASIC is described. In the method, a timing report is read into memory, and selected timing points are extracted therefrom. A timing waveform is generated from the extracted timing points for display and review by a designer to evaluate whether a given external port or internal pin of the ASIC meets required timing specifications. To create a combined timing waveform, max and min timing waveforms are generated from selected timing points extracted from max and min timing reports. The x-y coordinates of the min timing waveform are shifted by an adjustment factor so as to align with x-y coordinates the max timing waveform, then a combined timing waveform is generated from the x-y coordinates of both the max and min timing waveforms.
    Type: Application
    Filed: August 9, 2011
    Publication date: February 9, 2012
    Inventor: Yossi Rindner
  • Publication number: 20120030269
    Abstract: Provided is a system for generating coefficient values. The system may include a base function generator and a series of accumulators including a leading and a last accumulator. In the series of accumulators, the data output of each accumulator, except the last, may be coupled to the data input of a successive adjacent accumulator. The base function generator may be configured to output, to the leading accumulator, a series of data values that may correspond to a base function that is a specified order derivative of a filter function. Each accumulator may be configured to: add a data value currently at its data input to a currently stored data value to produce an updated data value that may correspond to a respective value of a specified order integral of the base function; store the updated data value in the accumulator; and output the updated data value at its data output.
    Type: Application
    Filed: July 30, 2010
    Publication date: February 2, 2012
    Inventors: Hector Rubio, Garritt W. Foote
  • Publication number: 20120016920
    Abstract: A direct current compensation method for S-parameter rational functions reads S-parameters f(sk), which are generated at given frequency sk, from a storage unit. An S-parameter, which is generated at frequency sk=0 is supplemented into the S-parameters f(sk), upon the condition that there is no S-parameter which is generated at the frequency sk=0. An S-parameter ration function is generated according to the S-parameters f(sk). A DC level of the S-parameter rational function is compensated to generate a compensated S-parameter rational function.
    Type: Application
    Filed: March 2, 2011
    Publication date: January 19, 2012
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: WEN-LAING TSENG, SHEN-CHUN LI, YU-CHANG PAI, SHOU-KUO HSU
  • Publication number: 20110282925
    Abstract: An optimization system and method includes determining a best gradient as a sparse direction in a function having a plurality of parameters. The sparse direction includes a direction that maximizes change of the function. This maximum change of the function is determined by performing an optimization process that gives maximum growth subject to a sparsity regularized constraint. An extended Baum Welch (EBW) method can be used to identify the sparse direction. A best step size is determined along the sparse direction by finding magnitudes of entries of direction that maximizes the function restricted to the sparse direction. A solution is recursively refined for the function optimization using a processor and storage media.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 17, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: DIMITRI KANEVSKY, David Nahamoo, Bhuvana Ramabhadran, Tara N. Sainath
  • Publication number: 20110276613
    Abstract: A function generator for a digital system includes a plurality of sub-function generators. Each sub-function generator has an input that receives a respective input value and has an output that provides a respective output value responsive to the respective input value. A case detector receives a system input value and selectively routes at least a first portion of the system input value to the input of at least one selected sub-function generator. The case detector selects the selected sub-function generator in response to at least a second portion of the system input value. The case detector further suppresses transitions of data on the input of at least one non-selected sub-function generator. The case detector further selects the respective output value provided by the at least one selected sub-function generator and provides the selected respective output value as a function generator output value.
    Type: Application
    Filed: July 18, 2011
    Publication date: November 10, 2011
    Inventor: Arthur Torosyan
  • Publication number: 20110276947
    Abstract: Some embodiments provide a system that facilitates the evaluation of an equation. During operation, the system obtains one or more data-access functions to be used in the equation. Next, the system obtains an analysis context for the equation separately from the data-access functions. The analysis context may include one or more analysis parameters that specify one or more data sources and/or types of analysis to be used in evaluating the equation. Finally, the system evaluates the equation using the data-access functions and the data sources.
    Type: Application
    Filed: May 4, 2010
    Publication date: November 10, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: Christian M. R. Delbaere, Anil P. Balaram
  • Patent number: 8046397
    Abstract: A power function is approximated over an applicable data interval with polynomials determined by means of a Chebyshev minimax approximation technique. In some cases, multiple polynomials may be used to approximate the function over respective ranges of the desirable interval, in a piecewise manner. The appropriate polynomial that approximates the power function over the range of interest is derived and stored. When the power function is to be applied to a particular data value, the data value is first evaluated to determine where it lies within the applicable interval. The constants for the polynomial associated with that range of the interval are then retrieved and used to calculate the power of that data value.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: October 25, 2011
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Ian Ollmann