Abstract: Accessing a shared buffer can include receiving an identifier associated with a buffer from a sending process, requesting one or more attributes corresponding to the buffer based on the received identifier, mapping at least a first page of the buffer in accordance with the one or more requested attributes, and accessing an item of data stored in the buffer by the sending process. The identifier also can comprise a unique identifier. Further, the identifier can be passed to one or more other processes. Additionally, the one or more requested attributes can include at least one of a pointer to a memory location and a property describing the buffer.

Abstract: A multiprocessor system can directly transmit storage-state information in a multilink architecture. The multiprocessor system includes a first processor; a multiport semiconductor memory device coupled to the first processor; a nonvolatile semiconductor memory device; and a second processor coupled with the multiport semiconductor memory device and the nonvolatile semiconductor memory device in a multilink architecture, storing data, having been written in a shared memory area of the multiport semiconductor memory device by the first processor, in the nonvolatile semiconductor memory device, and directly transmitting storage-state information on whether the storing of the data in the nonvolatile semiconductor memory device has been completed, in response to a request of the first processor, without passing it through the multiport semiconductor memory device.

Abstract: Systems, methods, and computer readable medium for allocating physical storage in a disk array are disclosed. According to one aspect, the subject matter described herein includes a method for allocating portions of storage area of a storage array. The method includes receiving, from a requesting entity, a request for allocation of a portion of storage area of a storage array, the storage array comprising a plurality of storage entities and a plurality of data buses for transferring data to and from the plurality of storage entities, wherein the plurality of storage entities are organized into at least one logical unit, wherein each logical unit is subdivided into at least one slice. In response to receiving the request for allocation, at least one slice is selected for allocation for use by the requesting entity, based on anticipated system resource utilization during access to data to be stored in the storage array.

Abstract: High performance computing systems perform complex or data-intensive calculations using a large number of computing nodes and a shared memory. Disclosed methods and systems provide nodes having a special-purpose coprocessor to perform these calculations, along with a general-purpose processor to direct the calculations. Computational data transfer from the shared memory to the coprocessor incurs a data copying latency. To reduce this latency as experienced by the coprocessor, a complex computation is divided into work units, and one or more threads executing on the processor copy the work units from the shared memory to a local buffer memory of a computing node. By buffering these data for transfer from the local memory to coprocessor memory, and by ensuring that new data are copied while the coprocessor operates on older data, data copying latency is hidden from the coprocessor.

Abstract: In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.

Abstract: Various embodiments of systems and methods for memory access are provided. In one embodiment, a data segment is stored in a plurality of memory segments of at least one memory bank. The data segment stored in the memory segments is selected, where the data segment has a bit boundary that is arbitrarily misaligned with at least one memory segment boundary of the memory segments.

Abstract: A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: Embodiments are described for a method for controlling access to memory in a processor-based system comprising monitoring a number of interference events, such as bank contentions, bus contentions, row-buffer conflicts, and increased write-to-read turnaround time caused by a first core in the processor-based system that causes a delay in access to the memory by a second core in the processor-based system; deriving a control signal based on the number of interference events; and transmitting the control signal to one or more resources of the processor-based system to reduce the number of interference events from an original number of interference events.

Abstract: A storage system includes a first storage apparatus and a second storage apparatus. The first storage apparatus includes a capacity pool that is partitioned into multiple pool pages and includes a storage area of an external logical volume provided by at least one storage apparatus. The second storage apparatus provides first virtual volume which is a virtual logical volume comprising multiple first virtual areas. In a case of receiving a write request from the computer to a virtual area in the first virtual volume to which a page is not allocated, an unallocated pool page of the external logical volume is allocated to the virtual area. An authority to allocate the unallocated pool page of the external logical volume is assigned to the first storage apparatus.

Abstract: A technique for improving the performance of RCU-based searches and updates to a shared data element group where readers must see consistent data with respect to the group as a whole. An updater creates one or more new group data elements and assigns each element a new generation number that is different than a global generation number associated with the data element group, allowing readers to track update versions. The updater links the new data elements into the data element group and then updates the global generation number so that referential integrity is maintained. This is done using a generation number element that is referenced by a header pointer for the data element group, and which in turn references or forms part of one of the data elements. After a grace period has elapsed, the any prior version of the generation number element may be freed.

Abstract: Described herein are method and apparatus for scheduling access requests for a multi-bank low-latency random read memory (LLRRM) device within a storage system. The LLRRM device comprising a plurality of memory banks, each bank being simultaneously and independently accessible. A queuing layer residing in storage system may allocate a plurality of request-queuing data structures (“queues”), each queue being assigned to a memory bank. The queuing layer may receive access requests for memory banks in the LLRRM device and store each received access request in the queue assigned to the requested memory bank. The queuing layer may then send, to the LLRRM device for processing, an access request from each request-queuing data structure in successive order. As such, requests sent to the LLRRM device will comprise requests that will be applied to each memory bank in successive order as well, thereby reducing access latencies of the LLRRM device.

Abstract: In a shared memory process different threads may attempt to access a shared data variable in a shared memory. Locks are provided to synchronize access to shared data variables. Each lock is allocated to have a location in the shared memory relative to the instance of shared data that the lock protects. A lock may be allocated to be adjacent to the data that it protects. Lock resolution is facilitated because the memory location of a lock can be determined from an offset with respect to the data variable that is being protected by the lock.

Abstract: The invention provides a data access method of a memory device. In one embodiment, the memory device comprises a plurality of memories. First, a plurality of commands sequentially received from a host is stored in a command queue. A target command is then retrieved from the command queue. A target memory accessed by the target command is then determined. Whether the target memory is in a busy state is then determined. When the target memory is not in a busy state, access operations requested by the target command are then performed. When the target memory is in a busy state, a substitute command is selected from a plurality of subsequent commands stored in the command queue and access operations requested by the substitute command are performed, wherein the sequence of the subsequent commands in the command queue is subsequent to the target command.

Abstract: Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost.

Abstract: A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU) and a graphics processing unit (GPU) and a shared virtual memory supported by a physical private memory space of at least one heterogeneous processor or a physical shared memory shared by the heterogeneous processor. The CPU (producer) may create shared multi-version data and store such shared multi-version data in the physical private memory space or the physical shared memory. The GPU (consumer) may acquire or access the shared multi-version data.

Abstract: Disclosed herein are an apparatus and method for virtualizing Input/Output (I/O) devices. The apparatus includes a hardware device control unit, a guest Operating System (OS) unit, a virtual machine monitor unit, and a host OS unit. The hardware device control unit controls the I/O devices of a terminal. The guest OS unit runs a guest OS via a virtual machine. The virtual machine monitor unit includes shared memory and an event channel, stores an instruction and data, and transfers the stored instruction and the data to a host OS. The host OS unit performs the operation of assigning the shared memory to the virtual machine monitor unit, the operation of generating the event channel, and an operation corresponding to the I/O instruction, stores the results of performance of the operations, and performs control so that the results of the performance of the operations are sent to the guest OS unit.

Abstract: In one embodiment, a system and method is disclosed for changing the resource availability of a particular user in a manner calculated to add the least cost to the user. A cluster of partition servers are arranged, in one embodiment, with a master controller for keeping track at any point in time as to the different licensing costs involved with different methods of adding resource capacity. When a user requires additional capacity the system calculates which of several possible resource enhancements to initiate based upon a least cost analysis.

Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.

Abstract: An information processing system that determines whether static data is already loaded into shared memory when a request is made to load static data into shared memory from a process out of a plurality of processes. When the information processing system determines that static data is not loaded into shared memory, after loading the data into shared memory, it notifies the requesting process with information identifying the static data. When the information processing system determines that the static data is already loaded into shared memory, it notifies the requesting process with information identifying the static data.

Abstract: The disclosed system and method enhances performance of pipelined data transactions involving FIFO buffers by implementing a transaction length indicator in a transaction header. The length indicator in the header is formed by components coupled to a memory controller through FIFO buffers. The memory controller uses the length indicator to execute pipelined data transfers at relatively high speeds without causing additional inadvertent shifts or indexes in the FIFO buffer being read. The system and method can be applied to any memory type in general, and avoids the use of additional control signals or added complexity or size in the memory controller.

Abstract: Data including information regarding a display of the host device may be received. A display of a client device may correspond to the display of the host device. Information regarding the display of the host device may be received and evaluated identify the images in the display. The identified images may be stored in memory and associated with a uniform resource locator (URL). A bitstream describing the display may be generated in which each image is referenced using the associated URL. The bitstream may then be provided to a client device, where rendering of the bitstream results in a display corresponding to the host device. Rendering the display may include retrieving the images associated with the URLs in the bitstream.

Abstract: A single interconnect is provided between a first processor and a second processor, such that the first processor may access a common memory through the second processor while the second processor can be mostly powered off. The first processor accesses the memory through a memory controller using a standard dynamic random access memory (DRAM) bus protocol. Instead of the memory controller directly connecting to the memory, the access path is through the second processor to the memory. Additionally, a bidirectional communication protocol bus is mapped to the existing DRAM bus signals. When both the first processor and the second processor are active, the bus protocol between the processors switches from the DRAM protocol to the bidirectional communication protocol. This enables the necessary chip-to-chip transaction semantics without requiring the additional cost burden of a dedicated interface for the bidirectional communication protocol.

Abstract: According to an embodiment, a multi-core processor is capable of executing a plurality of tasks. The multi-core processor includes at least a first core and a second core. The first core and the second core are capable of accessing a shared memory area. The first core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the first core. The second core includes one or more memory layers in an access path to the shared memory area, the one or more memory layers including a local memory for the second core. The local memory for the first core and the local memory for the second core include memories with different unit cell configurations in at least one identical memory layer.

Abstract: Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.

Abstract: Various embodiments of the present invention allow concurrent accesses to a cache. A request to update an object stored in a cache is received. A first data structure comprising a new value for the object is created in response to receiving the request. A cache pointer is atomically modified to point to the first data structure. A second data structure comprising an old value for the cached object is maintained until a process, which holds a pointer to the old value of the cached object, at least one of one of ends and indicates that the old value is no longer needed.

Abstract: A method and system for providing a shared data resource coordinator within a storage virtualizing data processing system is disclosed. According to one embodiment of the present invention, a first node of a plurality of nodes is configured to process requests to access a shared data resource on behalf of the plurality of nodes, where the plurality of nodes includes a logical volume configuration server configured to present a logical volume to one or more logical volume configuration clients. A second node is then selected from the plurality of nodes and configured to process requests to access the shared data resource on behalf of the plurality of nodes.

Abstract: Embodiments of the invention provide a solution to optimize/minimize the total capacity of Gold Image within the entire datacenter which utilizes a scale-out type of storage systems. A method of server image provisioning comprises checking whether a gold image exists in a first storage system, the gold image being one of a real gold image or a virtual gold image; if no gold image exists in the first storage system, searching a remainder of the storage systems until a real gold image is found in a second storage system; after finding the real gold image in the second storage system, creating a virtual gold image in the first storage system, the virtual gold image in the first storage system being associated with the real gold image in the second storage system; and creating a snapshot volume in the first storage system based on the virtual gold image.

Abstract: A method begins by a processing module determining whether to convert data between a redundant array of independent disks (RAID) format and a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory to produce retrieved RAID data when the data is to be converted from the RAID format to the DSN format. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.

Abstract: A data management method of a nonvolatile memory device which includes a data cell area and a reference cell area includes selecting shared data from write data input to the memory device; generating reference data based on the shared data; and storing the write data in the data cell area and a first reference area of the reference cell area; and storing the reference data in a second reference area of the reference cell area.

Abstract: Lock-free communication storage request reordering enables reduced latency and/or increased bandwidth in some usage scenarios, such as a multi-threaded driver context operating with a device, such as a storage device (e.g. a Solid-State Disk (SSD)) enabled to respond to a multiplicity of outstanding requests.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A system, comprising: a plurality of modules, each module comprising a plurality of integrated circuits devices coupled to a module bus and a channel interface that communicates with a memory controller, at least a first module having a portion of its total module address space composed of first type memory cells having a first maximum access speed, and at least a second module having a portion of its total module address space composed of second type memory cells having a second maximum access speed slower than the first access speed.

Abstract: Apparatuses and methods for a distributed memory system including memory nodes are disclosed. An example apparatus includes a processor and a memory system coupled to the processor. The memory system is configured to receive instructions from the processor to access information stored by the memory system. The memory system includes a plurality of memory nodes, wherein each memory node of the plurality of memory nodes is coupled to at least one other memory node of the plurality of memory nodes, and each memory node of the plurality of memory nodes is configured to generate an internal message including instructions for an operation, the internal message to be provided to another memory node of the plurality of memory nodes to perform the operation.

Abstract: A single device that provides computing system-level functionality with non-volatile storage controller functionality. These functionalities can share the same electronics.

Abstract: Methods, systems, and software are provided herein that allow a user to store and retrieve data records. In one example, a method of storing data records is provided. The method includes initializing a shared write pointer to a first location in a shared memory of a data storage system, and receiving a plurality of data records transferred by a plurality of data sources for storage in the shared memory. The method also includes, beginning with a first of the plurality of data sources, writing in a cyclic sequence one of the plurality of data records for each of the plurality of data sources based on the shared write pointer, and incrementing the shared write pointer after each writing, and updating at least a header portion of the shared memory with the shared write pointer responsive to each writing.

Abstract: A method, system, and computer program product for providing lines of data from shared resources to caching agents are provided. The method, system, and computer program product provide for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.

Abstract: Tenant driven security in a storage cloud is provided. A method includes determining whether a tenant places a physical key into a slot associated with a hard disk provided by a service provider. The method further includes allowing the tenant to have access to the hard disk after determining that the tenant has placed the physical key into the slot.

Abstract: A mechanism is provided for multi-part aggregated variables in structured external storage. The shared external storage provides a serialized, aggregated structure update capability. The shared external storage identifies each local value for which a group value is needed by name. Each time a member writes out its value, the member specifies the name of the object, the member's current value, and the type of aggregate function to apply (e.g., minimum, maximum, etc.). The structured external storage in one atomic operation updates the member's value, recalculates the aggregate of all of the individual values, and returns the aggregate to the member. The advantage of this approach is that it requires only one write operation to the structured external storage. The update operation does not require locking, because the operation is atomic.

Abstract: A method of managing a memory of an apparatus, the apparatus executing one or more processes using the memory. The method comprises maintaining a plurality of lists of identifiers, wherein each list has an associated size value and an associated threshold corresponding to a maximum number of identifiers in that list, wherein each identifier identifies a corresponding region of the memory that had been allocated for a process but that is currently not required by any of the one or more processes, and wherein the size of a region of the memory identified by an identifier of a list equals the size value associated with that list.

Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.

Abstract: A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.

Abstract: An electronic device includes: a variable resistance element having a first electrode, a variable resistance layer, and a second electrode which are sequentially stacked therein; a spacer formed on the sidewall of the variable resistance element; and a conductive line covering the variable resistance element including the spacer.

Abstract: A technology can be provided for managing shared memory used by a plurality of compute nodes. An example system can include a shared globally addressable memory to enable access to shared data by the plurality of compute nodes. A memory interface can process memory requests sent to the shared globally addressable memory from the plurality of processors. A memory write module can be included for the memory interface to allocate memory locations in the shared globally addressable memory and write read-only data to the globally addressable memory from a writing compute node. In addition, a read module for the memory interface can map read-only data in the globally addressable shared memory as read-only for subsequent accesses by the plurality of compute nodes.

Abstract: Described herein is a system and method for retaining deduplication of data blocks of a resulting storage object (e.g., a flexible volume) from a split operation of a clone of a base storage object. The clone may comprise data blocks that are shared with at least one data block of the base storage object and at least one data block that is not shared with at least one data block of the base storage object. The data blocks of the clone that are shared with the base storage object may be indicated to receive a write allocation that may comprise assigning a new pointer to a indicated data block. Each data block may comprise a plurality of pointers comprising a virtual address pointer and a physical address pointer. As such, data blocks of the clone comprising the same virtual address pointer may be assigned a single physical address pointer. Thus, a new physical address pointer is assigned or allocated once to a given virtual address pointer of data blocks of a clone.

Abstract: Systems and methods for data sharing include generating at least one sharing plan with a cheapest cost and/or a shortest execution time for one or more sharing arrangements. Admissibility of the one or more sharing arrangements is determined such that a critical time path of the at least one sharing plan does not exceed a staleness level and a cost of the at least one sharing plan does not exceed a capacity. Sharing plans of admissible sharing arrangements are executed while maintaining the staleness level.

Abstract: Eager send data communications in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI composed of data communications endpoints that specify a client, a context, and a task, including receiving an eager send data communications instruction with transfer data disposed in a send buffer characterized by a read/write send buffer memory address in a read/write virtual address space of the origin endpoint; determining for the send buffer a read-only send buffer memory address in a read-only virtual address space, the read-only virtual address space shared by both the origin endpoint and the target endpoint, with all frames of physical memory mapped to pages of virtual memory in the read-only virtual address space; and communicating by the origin endpoint to the target endpoint an eager send message header that includes the read-only send buffer memory address.

Abstract: A storage system provides highly flexible data layouts that can be tailored to various different applications and use cases. The system dynamically balances performance with block sharing, based on service level objectives (SLOs). The system defines several types of data containers, including “regions”, “logical extents” and “slabs”. Each region includes one or more logical extents. Allocated to each logical extent is at least part of one or more slabs allocated to the region that includes the extent. Each slab is a set of blocks of storage from one or more physical storage devices. The slabs can be defined from a heterogeneous pool of physical storage. The system also maintains multiple “volumes” above the region layer. Each volume includes one or more logical extents from one or more regions. Layouts of the extents within the regions are not visible to any of the volumes.

Abstract: In an embodiment, a shared memory fabric is configured to receive memory requests from multiple agents, where at least some of the requests have an associated order identifier and a deadline value to indicate a maximum latency prior to completion of the memory request. Responsive to the requests, the fabric is to arbitrate between the requests based at least in part on the deadline values. Other embodiments are described and claimed.

Abstract: An electronic device comprising a semiconductor memory unit that may a variable resistance element configured to be changed in its resistance value in response to current flowing through both ends thereof; an information storage unit configured to store switching frequency information corresponding to a switching frequency which minimizes an amplitude of a voltage to be applied to both ends of the variable resistance element to change the resistance value of the variable resistance element and switching amplitude information corresponding to a minimum amplitude; and a driving unit configured to generate a driving voltage with the switching frequency and the minimum amplitude in response to the switching frequency information and the switching amplitude information and apply the driving voltage to both ends of the variable resistance element.

Abstract: A method and system are presented for providing deterministic inter-core, inter-process, and inter-thread communication between a reader and a writer. The reader and writer communicate by passing data through a shared memory using double buffering of double buffers. The shared memory includes a first double buffer and a second double buffer. Both double buffers include a first low level buffer and a second low level buffer. Using double buffering of the double buffers, both the reader and the writer may simultaneously access the shared memory.