Abstract: Various embodiments provide a file processing method and system. An exemplary file processing method can include receiving a request for opening a file, applying for a memory area corresponding to the file requested for opening and setting a property of the memory area as non-readable and non-writable. After receiving a request for reading the file, the memory area corresponding to the file requested for reading can be accessed. If the accessing fails for a failure reason that the property of the memory area is non-readable and non-writable, file data requested for reading can be obtained from a disk by calling a memory access exception handler function registered in an operating system. The obtained file data can be stored in the memory area. The property of the memory area can be set as readable and writable and the file data can be read from the memory area.

Abstract: Examples of techniques for pre-allocating save areas of memory of a computer processing system are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include initiating, by a host processing device, a control program. The method may further include, responsive to initiating the control program, pre-allocating, by the host processing device, a plurality of save areas for each of a plurality of processors, wherein the plurality of save areas are anchored in a fixed area of the memory for each of the plurality of processors.

Abstract: A method is performed by a first server on a chip (SoC) node that is one instance of a plurality of nodes within a cluster of nodes. An operation is performed for determine if a second one of the SoC nodes in the cluster has data stored thereon corresponding to a data identifier in response to receiving a data retrieval request including the data identifier. An operation is performed for determining if a remote memory access channel exists between the SoC node and the second one of the SoC nodes. An operation is performed for access the data from the second one of the SoC nodes using the remote memory access channel after determine that the second one of the SoC nodes has the data stored thereon and that the remote memory access channel exists between the SoC node and the second one of the SoC nodes.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for memory requests by a virtual machine. One of the methods includes initiating a migration process to move an application executing on a first device from the first device to a second device by copying pages of data, stored in a memory of the first device and used for the execution of the application, from the first device to the second device while continuing to execute the application on the first device, updating, by the first device, one or more bytes in at least one of the pages of data in response to executing the application on the first device during the migration process, stopping execution of the application on the first device, and copying the updated bytes from the first device to the second device to cause the second device to continue execution of the application.

Abstract: Disclosed embodiments are directed to systems and methods for assigning and selecting memory units for internal memory operations in data storage systems. The embodiments can improve the efficiency of garbage collection operations by directing dynamic data into memory units with a relatively lower P/E count, directing static and system data into memory units with a relatively higher P/E count, and not mixing static and dynamic data by packing static data into separate memory units from dynamic data. In one embodiment, after completion of garbage collection of blocks, the blocks are each assigned to one of a cool down list and an available memory unit list based on a size limit of the cool down list and a number of program-erase (P/E) operations performed on each block. The blocks are subsequently selected from the lists for write operations according to whether write data includes static or dynamic data.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for managing shared resources between multiple processing devices. The processor may include a first processing device comprising a first non-coherent hardware block (hb) including a non-coherent data and a second processing device comprising a second non-coherent hb including the non-coherent data. The processor may also include a first hb in communication with the first non-coherent hb and the second non-coherent hb to track and share the non-coherent data between the first and the second processing devices.

Abstract: Mechanisms are provided, in a data processing system having a processor and a transactional memory, for executing a transaction in the data processing system. These mechanisms execute a transaction comprising one or more instructions that modify at least a portion of the transactional memory. The transaction is suspended in response to a transaction suspend instruction being executed by the processor. A suspended block of code is executed in a non-transactional manner while the transaction is suspended. A determination is made as to whether an interrupt occurs while the transaction is suspended. In response to an interrupt occurring while the transaction is suspended, a transaction abort operation is delayed until after the transaction suspension is discontinued.

Abstract: Techniques are provided for more efficient multi-row atomic, consistent, isolated and durable (ACID)-compliant transactions with snapshot isolation semantics (or just “multi-row transactions” for short). In some embodiments, the techniques are implemented in a computing system that includes a client application, a lightweight in-memory lease-based lock service, a multi-row transaction orchestrator, and an underlying database system. The transaction orchestrator implements a read protocol and a write protocol that provides support to the client application for carrying out multi-row transactions against the underlying database system irrespective of whether the database system itself supports multi-row transactions. The transaction orchestrator explicitly maintains transaction-level locks obtained from the lease-based lock service as part of the transaction protocol.

Abstract: The translation of virtual guest addresses to host physical addresses in a virtualized computer system provides a compound page table that may simultaneously support nested-paging and shadow-paging for different memory regions. Memory regions with stable address mapping, for example, holding program code, may be treated using shadow-paging while memory regions with dynamic address mapping, for example, variable storage, may be treated using nested-paging thereby obtaining the benefits of both techniques.

Abstract: A method in an Optical Line Terminal (OLT) device for transmitting a flow control message to an Optical Network Unit/Terminal (ONU/T) device in a Passive Optical Network (PON) access network is provided. The OLT device is configured to receive alarm and/or Attribute Value Change (AVC) messages from the ONU/T device. The OLT device is also configured to temporarily store the alarm and/or AVC messages in a message queue. The OLT device generates a flow control message indicating that the ONU/T device is to stop transmitting alarm and/or AVC messages to the OLT device, when the number of alarm and/or AVC messages in the message queue exceeds a first threshold. Then, the OLT device transmits the flow control message to the ONU/T device(s). An OLT device for transmitting a flow control message to an ONU/T device, and an ONU/T device and related method for receiving a flow control message are also provided.

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

Abstract: A method for managing design files shared by multiple users is provided. A plurality of design files are stored in a design library. A lock table is moved to a memory of a first computer when information of the lock table indicates that the design files were locked by a first process corresponding to a first user, wherein the memory is only accessible to performance of the first process. The lock table is moved from the memory to a common memory of the first computer when one design file is locked by a second process corresponding to a second user. The first and second processes are being performed in the first computer. The lock table is moved from the memory to the design library when the one design file is locked by the second process corresponding to the second user, wherein the second process is performed in a second computer.

Abstract: A computing device having a non-uniform memory access (NUMA) architecture implements a method to attach a resource to an application instance that is unaware of a NUMA topology of the computing device. The method includes publishing the NUMA topology of the computing device, where the published NUMA topology indicates for one or more resources of the computing device, a NUMA socket associated with each of the one or more resources of the computing device.

Abstract: Hybrid transaction memory systems and accompanying methods. A transaction to be executed is received, and an initial attempt is made to execute the transaction in a hardware path. Upon a failure to successfully execute the transaction in the hardware path, an attempt is made to execute the transaction in a hardware-software path. The hardware-software path includes a software path and at least one hardware transaction.

Abstract: Technologies for facilitating inter-system-on-a-chip (SoC) communication include a first SoC, a second SoC, and a dedicated manageability controller network. The first SoC includes a first main processor, a first manageability controller, and a memory dedicated to the first manageability controller and having manageability controller firmware stored thereon. The first manageability controller is different from the first main processor and to control functions of the first SoC. The second SoC is different from the first SoC and includes a second main processor and a second manageability control, which is different from the second main processor and to control functions of the second SoC. The second SoC is to access the manageability controller firmware of the memory of the first SoC over the dedicated manageability network.

Abstract: According to various embodiments, a method and apparatus for providing a virtual appliance are described. The method includes: obtaining metadata of a specific virtual appliance based on a received request for obtaining the specific virtual appliance, the metadata describing information about virtual machines involved in the specific virtual appliance, determining an association relationship between the specific virtual appliance and at least one other virtual appliance according to the metadata, and providing resource information for obtaining the specific virtual appliance according to the association relationship, the resource information including a plurality of resource addresses, at least one of the plurality of resource addresses pointing to a storage location of the at least one other virtual appliance.

Abstract: A method for deploying an application task across a distributed operating system is described. The method comprises receiving a request to deploy an application task from a main operating system on a main system to a distributed operating system, wherein the main system comprises a master cell, wherein the distributed operating system comprises a plurality of individual virtual cells, each individual virtual cell comprising a microkernel architecture and a portion of the distributed operating system. The method comprises detecting, via the master cell, a resource availability of each of the individual virtual cells and determining which of the individual virtual cells comprises an infrastructure necessary to perform the application task.

Abstract: Programmable devices, hierarchical parallel machines and methods for providing state information are described. In one such programmable device, programmable elements are provided. The programmable elements are configured to implement one or more finite state machines. The programmable elements are configured to receive an N-digit input and provide a M-digit output as a function of the N-digit input. The M-digit output includes state information from less than all of the programmable elements. Other programmable devices, hierarchical parallel machines and methods are also disclosed.

Abstract: A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking includes creating output code, identifying read-only memory regions in the output code and creating a map that is provided to a security monitoring thread. The security monitoring thread executes as a transaction and determines if a transactional conflict occurs to the read-only memory region during parallel execution of a monitored thread in the output code.

Abstract: Method, system, and computer-readable medium for scheduling blocking tasks are disclosed. A method includes: executing each of a plurality of task functions in a respective coroutine; detecting a first blocking event for a first task function of the plurality of task functions during execution of the first task function; in response to detecting the first blocking event: setting a respective blocking state of the first task function to a pause state; pausing execution of the first task function; and placing the first task function among a group of paused task functions; and after pausing the execution of the first task function: identifying a second task function among the group of paused task functions for which a respective blocking state has been updated to a running state; removing the second task function from the group of paused task functions; and resuming execution of the second task function.

Abstract: A system and method is described for operating a computer memory system having a plurality of controllers capable of accessing a common set of memory modules. Access to the physical storage of the memory modules may be managed by configuration logical units (LUNs) addressable by the users. The amount of memory associated with each LUN may be managed in units of memory (LMA) from a same free LMA table maintained in each controller of the plurality of controllers. A request for maintenance of a LUN may be received from any user through any controller and results in the association of a free memory area with the LUN, and the remaining controllers perform the same operation. A test for misallocation of a free memory area is performed and when such misallocation occurs, the situation is corrected in accordance with a policy.

Abstract: The present disclosure is directed to gradual context saving in a data storage device. An example data storage device may comprise at least a non-volatile memory and a control module. The control module may cause context data to be gradually saved to the non-volatile memory based on monitoring write activity to the nonvolatile memory, wherein the context data may correspond to a current state of the data storage device. The control module may cause context data to be saved based on a budget ratio. For example, a budget ratio may compare an amount of total budget consumed (e.g., based a capacity of the data storage device, an amount of data stored in the data storage device, a target time-to-ready for the data storage device, etc.) to an amount of total context data that has already been written to the non-volatile memory.

Abstract: A software defined infrastructure (SDI) makes available a subset of a computer server's resources to a cloud solution or workload. Multiple subsets of resources can be combined in a SDI to provide a logical resource pool. This allows cloud administrators to create software defined infrastructures derived from the partial capacity of a collection of systems. The resources defined across the physical boundaries of a computer server can then be made available to host deployment of cloud workloads. The infrastructure resource pool can be selected upon deployment of a cloud workload.

Abstract: When a virtual machine writes to a page that is being shared across VMs, a share value is calculated to determine how different the page would be if the write command were implemented. If the share value is below a predefined threshold (meaning that the page would not be “too different”), then the page is not copied (as it would be in a standard copy-on-write operation). Instead, the difference between the contents of the pages is stored as a self-contained delta. The physical to machine memory map is updated to point to the delta, and the delta contains a pointer to the original page. When the VM needs to access the page that was stored as a delta, the delta and the page are then fetched from memory and the page is reconstructed.

Abstract: Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained frames for an address space against a threshold of freemained frames for the address space, freemained frames can be retained or rejected and/or the threshold can be adjusted.

Abstract: When a virtual machine writes to a page that is being shared across VMs, a share value is calculated to determine how different the page would be if the write command were implemented. If the share value is below a predefined threshold (meaning that the page would not be “too different”), then the page is not copied (as it would be in a standard copy-on-write operation). Instead, the difference between the contents of the pages is stored as a self-contained delta. The physical to machine memory map is updated to point to the delta, and the delta contains a pointer to the original page. When the VM needs to access the page that was stored as a delta, the delta and the page are then fetched from memory and the page is reconstructed.

Abstract: A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area.

Abstract: Embodiments include methods, systems and computer program products for providing an extendable job structure for executing instructions on an accelerator. The method includes creating a number of data descriptor blocks, each memory location addresses and a pointer to a next of the number of the data descriptor block. The method further includes creating a last data descriptor block having memory location addresses and a last block indicator. Based on determining that additional memory is required for executing instructions on the accelerator, the method includes modifying the last data descriptor block to become a data extender block having a pointer to one of one or more new data descriptor blocks and creating a new last data descriptor block.

Abstract: A processor module including a processor configured to share data with at least one further processor module processor; and a memory mapped peripheral configured to communicate with at least one further processor memory mapped peripheral to control the sharing of the data, wherein the memory mapped peripheral includes a sender part including a data request generator configured to output a data request indicator to the further processor module dependent on a data request register write signal from the processor; and an acknowledgement waiting signal generator configured to output an acknowledgement waiting signal to the processor dependent on a data acknowledgement signal from the further processor module, wherein the data request generator data request indicator is further dependent on the data acknowledgement signal and the acknowledgement waiting signal generator acknowledgement waiting signal is further dependent on the acknowledgement waiting register write signal.

Abstract: Systems, devices, and methods for capturing and displaying picture data including picture orientation information are described. In one innovative aspect, a method for transmitting media information is provided. The method includes obtaining picture or video information, said picture or video information including image data and orientation information of a media capture unit when the picture or video information is obtained. The method further includes encoding said picture or video information, wherein the orientation information is included in a first portion and the image data is included in a second portion, the second portion being encoded and the first portion being distinct from the second portion. The method also includes transmitting the first portion and the second portion.

Abstract: Systems, devices, and methods for capturing and displaying picture data including picture orientation information are described. In one innovative aspect, a method for transmitting media information is provided. The method includes obtaining picture or video information, said picture or video information including image data and orientation information of a media capture unit when the picture or video information is obtained. The method further includes encoding said picture or video information, wherein the orientation information is included in a first portion and the image data is included in a second portion, the second portion being encoded and the first portion being distinct from the second portion. The method also includes transmitting the first portion and the second portion.

Abstract: A device includes a memory that stores a first page table that includes a first page table entry, wherein the first page table entry further includes a physical address, an alternative location associated with the page table entry, and a physical page of memory associated with the physical address. A first processing unit is configured to: read the first page table entry, and determine the physical address from the first page table entry. The second processing unit is configured to: read the physical address from the first page table entry, determine second page attribute data from the alternative location, wherein the second page attribute data define one or more accessibility attributes of the physical page of memory for the second processing unit, and access the physical page of memory associated with the physical address according to the one or more accessibility attributes.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: Subject matter disclosed herein relates to a memory device, and more particularly to a multi-channel memory device and methods of selecting one or more channels of same.

Abstract: Described herein is a system and method for dynamically managing service-level objectives (SLOs) for workloads of a cluster storage system. Proposed states/solutions of the cluster may be produced and evaluated to select one that achieves the SLOs for each workload. A planner engine may produce a state tree comprising nodes, each node representing a proposed state/solution. New nodes may be added to the state tree based on new solution types that are permitted, or nodes may be removed based on a received time constraint for executing a proposed solution or a client certification of a solution. The planner engine may call an evaluation engine to evaluate proposed states, the evaluation engine using an evaluation function that considers SLO, cost, and optimization goal characteristics to produce a single evaluation value for each proposed state. The planner engine may call a modeler engine that is trained using machine learning techniques.

Abstract: The present invention relates to a method for enabling a machine-to-machine (M2M) gateway to measure the position of an M2M device, and an apparatus therefore, and the method includes the steps of: receiving a request for generating a first resource representing the way of obtaining positional information form a first M2M device; if the generation request contains the information for indicating commonly based positional measurement, determining the device closest to the first M2M device; and setting the positional information of the closest device as the positional information for the first m2M device, wherein if the M2M gateway does not have network topological information, or at least one M2M device connected to the m2M gateway does not have positional information, the M2M topological information, and the at least one M2M device connected to the M2M gateway has positional information, the device having the minimum number of hops from the first M2M device among the at least one M2M device is determined as th

Abstract: The present invention relates to a method of controlling the operation of a processing device in a first mode or in a second mode. The processing device has a first execution environment and a second execution environment. The method comprises, upon detection of a switch between said first and second modes, setting in the first execution environment a value of a shared variable to an initial value, upon detection of a request of execution of instructions in the second execution environment, updating the value of said shared variable to a value different from the initial value, and reading a current value of the shared variable and causing the processing device to operate in the first mode or in the second mode depending at least on the current value of the shared variable.

Abstract: A storage control device that controls a physical storage device in a storage system, the storage control device includes: a receiving section configured to receive a command from the storage system including the physical storage device and a virtual storage device, the physical storage device configured to store data in a physical volume, the virtual storage device configured to intervene between a host device and the physical storage device and store data to be transmitted and received between the host device and the physical storage device as a virtual portable volume; a determining section configured to determine a type of the command; and a control section, if the command is an ejection command indicating an outside management of a first physical volume specified by the ejection command, configured to perform data protection setting on the first physical volume.

Abstract: Systems (100) and methods (300) for synchronizing operations of processors (102, 104). The methods involve: receiving by an electronic circuit (106) a first request (250) from a first processor for writing first data (262) to or reading first data from a first address (260) in a first data store (122), and subsequently a second request (252) from a second processor for writing second data (266) to or reading second data from a second address (264) in a second data store (124); comparing values of the first and second addresses to each other and values of the first and second data to each other; and concurrently communicating an asynchronous ready signal (254) from the electronic circuit to the processors when the values of the addresses and data respectively match each other. The asynchronous ready signal causes operations of the processors to be synchronized in time with each other.

Abstract: A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data elements, and a third register. A decoder to decode a packed instruction to identify the first and second registers as source registers and the third register as a destination register. And to decode a pack instruction to identify a fourth and a fifth register each having 16-bit data elements. At least one functional unit, responsive to the packed instruction, to store a result in the third register including only half of all data elements of each of the first and second registers, including only corresponding data elements from corresponding positions in the first and second registers, and responsive to the pack instruction to store a result that is to include an 8-bit data element for each 16-bit data element in the fourth and fifth registers.

Abstract: An integrated networked storage and switching apparatus comprises one or more flash memory controllers, a system controller, and a network switch integrated within a common chassis. The integration of storage and switching enables the components to share a common power supply and temperature regulation system, achieving efficient use of available space and power, and eliminating added complexity of external cables between the switch a storage devices. Additionally, the architecture enables substantial flexibility and optimization of network traffic policies for both network and storage-related traffic.

Abstract: A method of on-device access using a container application to manage a sub application provisioned on a computer device by set of stored instructions executed by a computer processor to implement the steps of: receive a communication for the sub application by a first service programming interface (SPI) of the container application, the communication sent by a on-device process over a first communication pathway of a device infrastructure of the computer device utilizing interprocess communication (IPC) framework of the device infrastructure, the first communication pathway provided external to the first SPI; retransmit the communication by the first SPI to a second SPI of the sub application over a second communication pathway that bypasses the IPC framework, the second communication pathway internal to the first SPI; receiving a response to the communication by the first SPU from the second SPI over the second communication pathway; and directing the response to the on-device process over the first communic

Abstract: An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped into modules, wherein each module has at least two processor cores grouped therein; a plurality of level 1 (L1) caches, each L1 cache directly accessible by one of the processor cores; a level 2 (L2) cache associated with each module, the L2 cache directly accessible by each of the processor cores associated with its respective module; a shared unified cache to store data and/or instructions for each of the processor cores in each of the modules; and a cache management module to manage the cache lines in the shared unified cache using a first cache line eviction policy favoring cache lines which are shared across two or more modules and which are accessed relatively more frequently from the modules.

Abstract: A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.

Abstract: Using hardware transactional memory (HTM) for queue operations includes invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use HTM, determining whether a data processing system executing the virtual machine supports HTM, and responsive to determining that the data processing system does support HTM, detecting, using a processor and within the first operation, a call to a second operation that is that is configured, in byte code, to return an indication of a failed hardware transaction. Responsive to detecting the second operation, a machine code implementation of the first operation that includes a machine code implementation of the second operation is generated. The machine code implementation of the second operation is an implementation of the first operation that does use HTM.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: Using hardware transactional memory (HTM) for queue operations includes invoking a first operation for a concurrent linked queue of an interpretive program using a Just-In-Time (JIT) compiler of a virtual machine, wherein the first operation does not use HTM, determining whether a data processing system executing the virtual machine supports HTM, and responsive to determining that the data processing system does support HTM, detecting, using a processor and within the first operation, a call to a second operation that is that is configured, in byte code, to return an indication of a failed hardware transaction. Responsive to detecting the second operation, a machine code implementation of the first operation that includes a machine code implementation of the second operation is generated. The machine code implementation of the second operation is an implementation of the first operation that does use HTM.

Abstract: Memory page de-duplication in a computer system that includes a plurality of virtual machine partitions managed by a hypervisor, where each virtual machine is assigned a different dedicated memory partition, may include: identifying, by the hypervisor, a plurality of identical memory pages in memory of one or more dedicated memory partitions; assigning, by the hypervisor, one of the identical memory pages as a master page; mapping, for each virtual machine having an identical memory page, each of the identical memory pages to the master page; and directing, by the hypervisor, reads of the memory page to the master page.

Abstract: A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.

Abstract: Embodiments of systems, apparatuses, and methods for performing guest logical memory address to host physical memory address translation are described. In some embodiments, a system receives the guest logical memory address and determines an index page reference from the guest logical memory address. The system further retrieves a page index corresponding to the virtual machine. In addition, the system retrieves a first part of the host physical memory address from index page using the page index and a second part of the host physical memory address from the guest logical memory address. The system generates the host physical memory address from the first and second parts of the host physical memory address.