Abstract: The various aspects leverage the novel observation that the number of call sites in code is directly correlated with the code's compile time and provide methods implemented by a compiler operating on a computing device (e.g., a smartphone) for performing inline throttling based on a projected number of call sites in the code that would exist after performing inline expansion. The various aspects enable the compiler to improve the performance of the generated code by aggressive inlining while carefully managing increases in compile time, thereby decreasing the power required to compile the code while increasing performance of the computing device. Thus, by inlining enough call sites to reduce the costs of handling calls while accounting for the costs of inlining, the various aspects provide for an effective balance of short compile times and effective code performance.

Abstract: A method for synchronizing parallel applications in a partitioned asymmetric multi-processing system having multiple independent levels of security is provided. Synchronized access to a shared data memory region is provided for a first application through a first instance of a para-virtualized user library linked against a first application in a first domain having a first security level. Synchronized access is provided to the shared data memory region for a second application in parallel with the first application through a second instance of the para-virtualized user library linked against the second application in the first domain. The second instance of the para-virtualized user library also accesses the synchronization structure. Access is prevented to the shared data memory region and the synchronization structure by other applications in one or more other domains having other levels of security per domain.

Abstract: An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration. This facilitates provision of guest access in virtualized operating systems, and/or the mixing of translation formats to better match the data access patterns being translated.

Abstract: Hibernation/resume time is reduced, and a low-power information processing device and a method for driving the information processing device are provided. In an information processing device in which a virtual environment is created, in hibernation during which part of a main storage unit is stopped while data in the main storage unit is retained, data stored in the main storage unit is saved to a non-volatile memory, and whether another data shares a common block with the data saved to the non-volatile memory is determined in hibernation during which part of the main storage unit is stopped while the other data in the main storage unit is retained. In the case where there is a common block, the common block of the other data is not saved to the non-volatile memory, and the information on the common block is retained in the non-volatile memory.

Abstract: Embodiments of the invention broadly described, introduce systems and methods for enabling the searching of encrypted data. One embodiment of the invention discloses a method for generating a searchable encrypted database. The method comprises receiving a plurality of sensitive data records comprising personal information of different users, identifying one or more searchable fields for the sensitive data records, wherein each searchable field is associated with a subset of the personal information for a user, generating a searchable field index for each of the one or more searchable fields, and encrypting the sensitive data records using a database encryption key.

Abstract: A memory sub-system includes a main memory, a storage device, a control unit, and a common interface unit. The control unit is configured to control the main memory and the storage device. The common interface unit is operatively coupled to the control unit, and is configured to access the main memory and the storage device through the control unit in response to a request received from a host.

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract: A system for ensuring that serialization is maintained between separate transactions while searching and/or modifying a variable length queue is system includes a computer processor and logic executable by the computer processor. The logic is configured to implement a method. The method includes searching, by a processing device, a queue using a transaction. A first sequence number is retrieved from a queue header and a second sequence number is retrieved from local storage for the transaction. The first sequence number is compared with the second sequence number according to embodiments. The search of the queue is resumed using an address of a next element saved from a previous transaction responsive to the first sequence number matching the second sequence number. The search of the queue is restarted at a first element responsive to the first sequence number not matching the second sequence number.

Abstract: A method of ensuring that serialization is maintained between separate transactions while searching and/or modifying a variable length queue includes searching a queue using a transaction. A first sequence number is retrieved from a queue header and a second sequence number is retrieved from local storage for the transaction. The first sequence number is compared with the second sequence number according to embodiments. The search of the queue is resumed using an address of a next element saved from a previous transaction responsive to the first sequence number matching the second sequence number. The search of the queue is restarted at a first element responsive to the first sequence number not matching the second sequence number.

Abstract: Apparatuses, systems, methods, and computer program products for auto-commit memory are presented. A monitor module determines that a triggering event for an auto-commit memory has occurred. An identification module identifies a triggered commit action for an auto-commit memory. An auto-commit memory module performs a triggered commit action for an auto-commit memory in response to a triggering event occurring.

Abstract: Freeing memory safely with low performance overhead in a concurrent environment is described. An example method includes creating a reference count for each sub block in a global memory block, and each global memory block includes a plurality of sub blocks aged based on respective allocation time. A reference count for a first sub block is incremented when a thread operates a collection of data items and accesses the first sub block for a first time. Reference counts for the first sub block and a second sub block are lazily updated. Subsequently, the sub blocks are scanned through in the order of their age until a sub block with a non-zero reference count is encountered. Accordingly, one or more sub blocks whose corresponding reference counts are equal to zero are freed safely and with low performance overhead.

Abstract: Systems and methods for implementing a distributed shared memory (DSM) in a computer cluster in which an unreliable underlying message passing technology is used, such that the DSM efficiently maintains coherency and reliability. DSM agents residing on different nodes of the cluster process access permission requests of local and remote users on specified data segments via handling procedures, which provide for recovering of lost ownership of a data segment while ensuring exclusive ownership of a data segment among the DSM agents detecting and resolving a no-owner messaging deadlock, pruning of obsolete messages, and recovery of the latest contents of a data segment whose ownership has been lost.

Abstract: Techniques for selectively utilizing memory available in a redundant host system of a cluster are described. In one embodiment, a cluster of host systems, with at least one redundant host system, with each host system having a plurality of virtual machines with associated virtual machine (VM) reservation memory is provided. A portion of a data store is used to store a base file, the base file accessed by all the plurality of virtual machines. A portion of the memory available in the redundant host system is assigned as spare VM reservation memory. A copy of the base file is selectively stored in the spare VM reservation memory for access by all the plurality of virtual machines.

Abstract: Apparatuses and methods for reducing capacitance on a data bus are disclosed herein. In accordance with one or more described embodiments, an apparatus may comprise a plurality of memories coupled to an internal data bus and a command and address bus, each of the memories configured to receive a command on the command and address bus. One of the plurality of memories may be coupled to an external data bus. The one of the plurality of memories may be configured to provide program data to the internal data bus when the command comprises a program command and another of the plurality of memories is a target memory of the program command and may be configured to provide read data to the external data bus when the command comprises a read command and the another of the plurality of memories is a target memory of the read command.

Abstract: A lookup engine of a transactional memory (TM) has multiple hardware lookup structures, each usable to perform a different type of lookup. In response to a lookup command, the lookup engine reads a first block of first information from a memory unit. The first information configures the lookup engine to perform a first type of lookup, thereby identifying a first result value. If the first result value is not a final result value, then the lookup engine uses address information in the first result value to read a second block of second information. The second information configures the lookup engine to perform a second type of lookup, thereby identifying a second result value. This process repeats until a final result value is obtained. The type of lookup performed is determined by the result value of the preceding lookup and/or type information of the block of information for the next lookup.

Abstract: The entirety or a part of free space of a second storage device included in a host computer is used as a cache memory region (external cache) outside of a storage apparatus. If Input/Output (I/O) in the host computer is Write, a Write request is transmitted from the host computer to a storage apparatus, the storage apparatus writes data associated with the Write request into a main cache that is a cache memory region included in this storage apparatus, and the storage apparatus writes the data in the main cache into a first storage device included in the storage apparatus. The storage apparatus writes the data in the main cache into an external cache included in the host computer. If the I/O in the host computer is Read, the host computer determines whether or not Read data as target data of the Read exists in the external cache. If a result of the determination is positive, the host computer reads the Read data from the external cache.

Abstract: A processing device processes data with use of one or more data blocks shared with a plurality of external processing devices. The device includes a processor, and a shared data storage unit that stores, respectively in one or more storage areas thereof, one or more data blocks to be shared with one or more external processing devices. An output unit outputs, when the processor makes an access request to write data in a part of one of the data blocks, a block identifier identifying the one of the data blocks, and the data pertaining to the access request. An input unit judges whether to share external data outputted from one of the external processing devices, based on a block identifier outputted from the one of the external processing devices, and only when judging affirmatively, causes the shared data storage unit to store the external data.

Abstract: The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.

Abstract: A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

Abstract: A method of operation of a real-time data-pattern analysis system includes: providing a memory module, a computational unit, and an integrated data transfer module arranged within an integrated circuit die; storing a data pattern within the memory module; transferring the data pattern from the memory module to the computational unit using the integrated data transfer module; and comparing processed data to the data pattern using the computational unit.

Abstract: Reducing an amount of memory used by a virtual machine. A system includes multiple virtual machines that share common pages of memory. The number of private pages associated with each virtual machine is minimized by ensuring that pages that a guest operating system regards as now free or zeroed are efficiently mapped by the hypervisor to a shared zero page. Upon a hypervisor determining that one or more guest physical frame numbers are assigned to free memory pages, the hypervisor updates mapping data to map the one or more guest physical frame numbers to a shared zero page within the machine frame.

Abstract: The specification and drawings present a new apparatus, method and software related product for using a cache/central cache module/device (instead of e.g., system DRAM) which can serve multiple memory modules/devices. Each memory/IO module/device connected to the same memory network (e.g., via hub, bus, etc.) may utilize memory resources of this cache module/device either in a fixed manner using pre-set allocation of resources per the memory module/device, or dynamically using run-time allocation of new resources to an existing module/device per its request or to a new module/device connecting to the memory network (e.g., comprised in a host device) and possibly requesting memory resources.

Abstract: Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

Abstract: A computer system includes a first processor, a second processor, and a common memory connected to the second processor. The computer system is switched from a high performance mode, in which at least a portion of the first processor and at least a portion of components on the second processor are active, to a low power mode, in which at least a portion of the first processor is active and the components on the second processor are inactive. All central processing unit (CPU) cores on the second processor are quiesced. Traffic from the second processor to the common memory is quiesced. Paths used by the first processor to access the common memory are switched from a first path across the second processor to a second path across the second processor.

Abstract: A method and apparatus for compiling software written to be executed on a microprocessor that supports at least one hardware transactional memory function is provided. A compiler that supports at least one software transactional memory function is adapted to include a runtime system that maps between the at least one software transactional memory function and the at least one hardware transactional memory instruction.

Abstract: A memory managing apparatus manages a memory shared by processors. The apparatus includes an allocator, an updater and a releaser. The allocator secures a memory area in the memory allocated to each processor based on a request of each processor and registers reference counters corresponding one-to-one to the processors. The updater adds 1 to a value of the reference counter corresponding to the processor managing the memory area when the memory area is allocated to each processor and subtracts 1 from the value of the reference counter corresponding to the processor managing the memory area when the memory area is released from the processor to which the memory area is allocated. The releaser releases the memory area from the processor to which the memory area is allocated when a sum of the values of the reference counters in the memory area updated by the updater is 0.

Abstract: Technologies described herein generally describe technologies for managing addressable memories in a heterogeneous multicore chip. Technologies may be adapted to determine whether swapping a first data segment and a second data segment is suitable. The first data segment may be stored in a first addressable memory, and the second data segment may be stored in a second addressable memory. If the swapping is determined to be suitable, then the technologies may be adapted to swap the first data segment and the second data segment. As a result of the swap, the first data segment will be stored in the second addressable memory, and the second data segment will be stored in the first addressable memory. The technologies may also be adapted to update corresponding swap status indicators to indicate that the first data segment and the second data segment have moved.

Abstract: Described are systems and methods for managing data transfer from a communication device to a communication network over a wireless connection comprising determining that a requesting process on the communication device is authorized to establish a protected connection to the communication network; and, configuring a network interface on the communication device to allow data packets to be transmitted from the requesting process to the communication network over the protected connection, wherein the network interface is associated with the protected connection.

Abstract: Even when a configuration in which instances of plural kinds of storage management software having equivalent functions are arranged to cooperatively manage a large-scale storage system is adopted, to prevent occurrence of a management inoperability and configuration information inconsistency and enable the same management operation and information reference as those performed when all management target objects are managed by a single instance. In the present invention, a representative management computer serving as a representative among management computers is determined. The representative management computer collects, from storage apparatuses and host computers, information concerning the management target objects and configuration summary information including a relation type among the objects and determines, on the basis of the configuration summary information, management target objects which each of the management computers should take charge of.

Abstract: Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint comprising a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task, the compute nodes coupled for data communications through the PAMI and through data communications resources including a deterministic data communications network, including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endpoints.

Abstract: Illustrative embodiments include a method for preprovisioning using a mutated template. A subset of templates is selected from a set of templates that can be provisioned to a data processing system, a template in the set of templates including data to create a virtual machine on the data processing system. The mutated template is constructed using the subset of templates. A manifest is constructed such that a template in the subset of templates can be reconstructed from the mutated template using the manifest. Instead of the subset of templates, the mutated template is preprovisioned to the data processing system.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for distributed memory allocation. The system identifies a consumer thread which allocates substantially more memory blocks than it deallocates and a producer thread which deallocates substantially more memory blocks than it allocates. The system establishes a dedicated channel for direct allocation and deallocation between the consumer thread and the producer thread.

Abstract: Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task; the compute nodes coupled for data communications through the PAMI and through data communications resources including at least one segment of shared random access memory; including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers through a segment of shared memory; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endp

Abstract: Fencing data transfers in a parallel active messaging interface (‘PAMI’) of a parallel computer, the PAMI including data communications endpoints, each endpoint including a specification of data communications parameters for a thread of execution on a compute node, including specifications of a client, a context, and a task; the compute nodes coupled for data communications through the PAMI and through data communications resources including at least one segment of shared random access memory; including initiating execution through the PAMI of an ordered sequence of active SEND instructions for SEND data transfers between two endpoints, effecting deterministic SEND data transfers through a segment of shared memory; and executing through the PAMI, with no FENCE accounting for SEND data transfers, an active FENCE instruction, the FENCE instruction completing execution only after completion of all SEND instructions initiated prior to execution of the FENCE instruction for SEND data transfers between the two endp

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

Abstract: Technologies are described for restarting an application while maintaining data in memory (e.g., using shared memory). For example, shared memory can be associated with an application. The shared memory can also be associated with a holder process to maintain the shared memory from the time the application stops to the time the application starts again. When the application starts, the shared memory can be associated with the started application. In addition, restart of in-memory databases can be provided using shared memory. For example, in-memory data can be maintained when a database process or database management system stops and starts (e.g., during a restart).

Abstract: A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.

Abstract: The systems and methods described herein may be used to implement a shared dynamic-sized data structure using hardware transactional memory to simplify and/or improve memory management of the data structure. An application (or thread thereof) may indicate (or register) the intended use of an element of the data structure and may initialize the value of the data structure element. Thereafter, another thread or application may use hardware transactions to access the data structure element while confirming that the data structure element is still part of the dynamic data structure and/or that memory allocated to the data structure element has not been freed. Various indicators may be used determine whether memory allocated to the element can be freed.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices.

Abstract: Systems and methods are described including dynamically configuring a shared buffer to support processing of at least two video read streams associated with different video codec formats. The methods may include determining a buffer write address within the shared buffer in response to a memory request associated with one read stream, and determining a different buffer write address within the shared buffer in response to a memory request associated with the other read stream.

Abstract: A system for providing model level protection for resources holding data accessed by multiple tasks in a model is discussed. The protection occurs at the model level so that the protection mechanism does not interfere with model dynamics. Resources concurrently accessed by multiple tasks are identified so that a unified protection mechanism can be applied to the resource. A user interface may be provided which enables the selection of a particular type of protection mechanism for the data in the resource. User supplied protection mechanisms may also be implemented.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data processing and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.).

Abstract: A storage module may include a controller configured to communicate with a memory having a plurality of memory dies. The controller may include a plurality of bond pads, where each bond pad is configured to communicate a same type of memory signal, and where each bond pad is electrically connected to at least one but less than all of the plurality of memory dies. A core of the controller may identify a memory die that it wants to communicate a memory signal and an associated bond pad with which to communicate the memory signal.

Abstract: An asymmetrical processing multi-core system used in a network device is provided. A sub processing core within the asymmetrical processing multi-core system facilitates a main processing core of the asymmetrical processing multi-core system in processing tasks, thereby improving an overall performance of the entire network device and causing the network device to operate more facilely. Different from a conventional processing method, the asymmetrical processing multi-core system does not require moving or copying a large amount of processed packet data, and thus a large amount of memory bandwidth is saved and the power consumption is reduced.

Abstract: A method for efficiently managing memory resources in a computer system having a graphics processing unit that runs several processes simultaneously on the same computer system includes using threads to communicate that additional memory is needed. If the request indicates that termination will occur then the other processes will reduce their memory usage to a minimum to avoid termination but if the request indicates that the process will not run optimally then the other processes will reduce their memory usage to 1/N where N is the count of the total number of running processes. The apparatus includes a computer system using a graphics processing unit and processes with threads that can communicate directly with other threads and with a shared memory which is part of the operating system memory.

Abstract: The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.

Abstract: A first communication apparatus includes a first central processing core; and a first memory. The first communication apparatus executes load distribution based on a first load amount of the first communication apparatus and a second load amount of a second communication apparatus that includes a second central processing core and a second memory. The first communication apparatus executes first load distribution when the first communication apparatus and the second communication apparatus perform wireless communication. The first communication apparatus executes second load distribution when the first communication apparatus and the second communication apparatus perform wired communication.

Abstract: A computerized method for sharing removable storage media in a network, the method comprising associating, in an index entry, a first piece of removable storage media in a first storage device with at least a first storage policy copy and a second storage policy copy; copying, to the first piece of removable storage media, data associated with the first storage policy copy; and copying, to the first piece of removable storage media, data associated with the second storage policy copy.

Abstract: Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of non-volatile storage media, will have the fastest access at a given time; and (ii) read-writing (that is, reading and/or writing) data by the virtual input/output system of a high importance page to the non-volatile storage media estimated to have the fastest access time.