Abstract: Using a set of non-volatile storage media and a virtual input/output system operating in a memory sharing environment, by: (i) estimating which non-volatile storage medium, of the set of non-volatile storage media, will have the fastest access at a given time; and (ii) read-writing (that is, reading and/or writing) data by the virtual input/output system of a high importance page to the non-volatile storage media estimated to have the fastest access time.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: An automatic mutual exclusion computer programming system is disclosed which allows a programmer to produce concurrent programming code that is synchronized by default without the need to write any synchronization code. The programmer creates asynchronous methods which are not permitted make changes to shared memory that they cannot reverse, and can execute concurrently with other asynchronous methods. Changes to shared memory are committed if no other thread has accessed shared memory while the asynchronous method executed. Changes are reversed and the asynchronous method is re-executed if another thread has made changes to shared memory. The resulting program executes in a serialized order. A blocking system method is disclosed which causes the asynchronous method to re-execute until the blocking method's predicate results in an appropriate value. A yield system call is disclosed which divides asynchronous methods into atomic fragments.

Abstract: A method and system for self-sizing dynamic cache for virtualized environments is disclosed. The preferred embodiment self sizes unequal portions of the total amount of cache and allocates to a plurality of active virtualized machines (VM) according to VM requirements and administrative standards. As a new VM may emerge and request an amount of cache, the cache controller reclaims currently used cache from the active VM and reallocates the unequal portions of cache required by each VM. To ensure cache availability, a quick reclamation amount of cache is immediately available to each new VM as it makes the request begins operation. After reallocation, the newly created VM may rely on a guaranteed minimum quota of cache to ensure performance.

Abstract: A controller process loads a module based on a user-generated script into itself. The controller process also generates a shared memory mapping using offset pointers as opposed to absolute pointers. The controller process loads the module and the shared memory mapping into target processes indicated by the user-generated script in order to probe the target processes.

Abstract: A system, method and medium may provide determination of a first plurality of a plurality of data records assigned to a first processing unit, identification of a first record of the first plurality of data records, the first record associated with a first key value, generation of a first dictionary entry of a first dictionary for the first key value, storage of a first identifier of the first record as a tail identifier and as a head identifier in the first dictionary entry, storage an end flag in a first shared memory location, the first shared memory location associated with the first record, identification of a second record of the first plurality of data records, the second record associated with the first key value, replacement of the tail identifier in the first dictionary entry with a second identifier of the second record, and storage of the first identifier in a second shared memory location, the second shared memory location associated with the second record.

Abstract: A method to store objects in a memory cache is disclosed. A request is received from an application to store an object in a memory cache associated with the application. The object is stored in a cache region of the memory cache based on an identification that the object has no potential for storage in a shared memory cache and a determination that the cache region is associated with a storage policy that specifies that objects to be stored in the cache region are to be stored in a local memory cache and that a garbage collector is not to remove objects stored in the cache region from the local memory cache.

Abstract: A multimedia platform is discussed, which includes a first stacking unit including a first substrate and a multimedia processor, wherein the first substrate and the multimedia processor are stacked on the first stacking unit, a pattern and a via hole are formed on the first substrate, and the multimedia processor is mounted on top of the first substrate; a second stacking unit including a second substrate and a plurality of storage devices, wherein the second substrate and the plurality of storage devices are stacked on the second stacking unit, a pattern and a via hole being formed on the second substrate, and the plurality of storage devices are mounted on top of the second substrate; and at least one solder ball arranged on the first stacking unit, the at least one solder ball allowing the first substrate to be coupled to the second substrate.

Abstract: A system includes a memory device including a real memory and a tracking mechanism configured to track relationships between multiple virtual memory addresses and real memory. The system further includes a processor configured to perform the below method and/or execute the below computer program product. One method includes mapping a first virtual memory address to a real memory in a memory device and mapping a second virtual memory address to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory. One computer storage medium includes a computer program product for performing the above method.

Abstract: At least one virtual machine implemented on a given physical machine in an information processing system is able to detect the presence of one or more other virtual machines that are also co-resident on that same physical machine. More particularly, at least one virtual machine is configured to avoid usage of a selected portion of a memory resource of the physical machine for a period of time, and to monitor the selected portion of the memory resource for activity during the period of time. Detection of a sufficient level of such activity indicates that the physical machine is also being shared by at least one other virtual machine. The memory resource of the physical machine may comprise, for example, a cache memory, and the selected portion of the memory resource may comprise one or more randomly selected sets of the cache memory.

Abstract: Methods and systems are provided for mapping a memory instruction to a shared memory address space in a computer arrangement having a CPU and an APD. A method includes receiving a memory instruction that refers to an address in the shared memory address space, mapping the memory instruction based on the address to a memory resource associated with either the CPU or the APD, and performing the memory instruction based on the mapping.

Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

Abstract: A first virtual memory address is mapped to a real memory in a memory device, and a second virtual memory address is mapped to the real memory. Here, the first virtual memory address is authorized to modify data in the real memory and the second virtual memory address is not authorized to modify the data in the real memory.

Abstract: A multi-ported memory that supports multiple read and write accesses is described herein. The multi-ported memory may include a number of read/write ports that is greater than the number of read/write ports of each memory bank of the multi-ported memory. The multi-ported memory allows for at least one read operation and at least one write operation to be received during the same clock cycle. In the event that an incoming write operation is blocked by the at least one read operation, data for that incoming write operation may be stored in a cache included in the multi-port memory. That cache is accessible to both write operations and read operations. In the event than the incoming write operation is not blocked by the at least one read operation, data for that incoming write operation is stored in the memory bank targeted by that incoming write operation.

Abstract: System for working with shared memory includes a plurality of contexts, each having executable processes writing and reading data; a ring buffer in the shared memory for writing and reading data by the contexts; a software primitive manages access attempts by the contexts to the ring buffer. Each context, upon writing to the ring buffer, is allocated an amount of space up to a maximum available at that moment. The software primitive guarantees consistency of the data written to the ring buffer. The software primitive permits simultaneous writing into the buffer by multiple contexts. After finishing writing to the buffer, the context updates a state of the buffer by decrementing the count of the active writers and/or by shifting the permitting pointers for communicating with writers and readers. A context can read from the buffer only data is marked as valid for reading by the context that wrote that data.

Abstract: Provided are a device and computer readable storage medium for programming a memory module to initiate a training mode in which the memory module transmits continuous bit patterns on a side band lane of the bus interface; receiving the bit patterns over the bus interface; determining from the received bit patterns a transition of values in the bit pattern to determine a data eye between the determined transitions of the values; and determining a setting to control a phase interpolator to generate interpolated signals used to sample data within the determined data eye.

Abstract: Methods and systems are disclosed for providing resource sharing in a computing environment using file descriptor isomorphism. The methods and systems may perform a method in a computing environment having processor systems executing processes. The method may include receiving a request from a first process to access a first resource. Further, the method may include generating a first Global File Descriptor (GFD) that references a first entry in a GFD table, the first GFD entry including a reference to a first entry in a resource descriptor table pointing to the first resource. Based on the request, at least one GFD field associated with the first GFD entry is configured. Thus, methods and systems may manage access by the first process to the first resource using the first GFD entry.

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract: A memory module having reduced access granularity. The memory module includes a substrate having signal lines thereon that form a control path and first and second data paths, and further includes first and second memory devices coupled in common to the control path and coupled respectively to the first and second data paths. The first and second memory devices include control circuitry to receive respective first and second memory access commands via the control path and to effect concurrent data transfer on the first and second data paths in response to the first and second memory access commands.

Abstract: A technology for implementing a method for distributed memory operations. A method of the disclosure includes obtaining distributed channel information for an algorithm to be executed by a plurality of spatially distributed processing elements. For each distributed channel in the distributed channel information, the method further associates one or more of the plurality of spatially distributed processing elements with the distributed channel based on the algorithm.

Abstract: A multi-core processor system includes a memory controller that includes multiple ports and shared memory that includes physical address spaces divided among the ports. A CPU acquires from a parallel degree information table, the number of CPUs to which software that is to be executed by the multi-core processor system, is to be assigned. After this acquisition, the CPU determines the CPUs to which the software to be executed is to be assigned and sets for each CPU, physical address spaces corresponding to logical address spaces defined by the software to be executed. After this setting, the CPU notifies an address converter of the addresses and notifies the software to be executed of the start of execution.

Abstract: There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the contents of the caches can be synchronized without scanning all cache blocks. A cache synchronization control method for a multiprocessor that has a plurality of processors having a cache, and a storage device shared by the plurality of processors, the method comprises: before a task is executed, a first step of writing back input data of the task to the storage device by a processor that manages the task and deleting data corresponding to the input data from its own cache by a processor other than the processor; and after the task is executed, a second step of writing back output data of the task to the storage device by a processor that has executed the task and deleting data corresponding to the output data from its own cache by a processor other than the processor.

Abstract: A system and method for supporting targeted stores in a shared-memory multiprocessor. A targeted store enables a first processor to push a cache line to be stored in a cache memory of a second processor. This eliminates the need for multiple cache-coherence operations to transfer the cache line from the first processor to the second processor. More specifically, the disclosed embodiments provide a system that notifies a waiting thread when a targeted store is directed to monitored memory locations. During operation, the system receives a targeted store which is directed to a specific cache in a shared-memory multiprocessor system. In response, the system examines a destination address for the targeted store to determine whether the targeted store is directed to a monitored memory location which is being monitored for a thread associated with the specific cache. If so, the system informs the thread about the targeted store.

Abstract: A method, system and computer program product for managing requests for deferred updates to shared data elements while minimizing grace period detection overhead associated with determining whether pre-existing references to the data elements have been removed. Plural update requests that are eligible for grace period detection are buffered without performing grace period detection processing. One or more conditions that could warrant commencement of grace period detection processing are monitored while the update requests are buffered. If warranted by such a condition, grace period detection is performed relative to the update requests so that they can be processed. In this way, grace period detection overhead can be amortized over plural update requests while being sensitive to conditions warranting prompt grace period detection.

Abstract: Technologies relating to efficient memory management for parallel synchronous computing systems are disclosed. Parallel synchronous computing systems may include, for example, a host, a memory management subsystem, and an array of processing units adapted to execute in parallel. Memory management may be implemented at least in part via the memory management subsystem. A memory management subsystem may include one or more memory subsystem layers deployed between the host and the array of processing units. Each memory subsystem layer may have a local memory accessible by entities (whether the host or another layer) above the memory subsystem layer; and a memory controller adapted to manage communications between the entities (whether another layer or the processing units in the array) below the memory subsystem layer.

Abstract: Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.

Abstract: Administering inter-core communication via shared memory may be carried out in a system in which each core is associated with a mailbox in a shared memory region. Such administration may include constructing a mailbox latency table describing latency of writing data from each core to each mailbox; constructing a locking latency table describing latency of each core in acquiring a lock for each of the mailboxes; identifying, from the tables, groups of a cores having mailbox and locking latency within a predefined range of acceptable latency values; and for each identified group of cores, establishing, for every pair of cores in the group of cores, a private channel, including pinning, for each private channel established for a pair of cores, one local memory segment per core.

Abstract: A multi-processor system includes a first processor, a second processor communicable with the first processor, a first non-volatile memory for storing first codes and second codes to respectively boot the first and second processors, the first memory communicable with the first processor, a second volatile memory designated for the first processor, a third volatile memory designated for the second processor, and a fourth volatile memory shared by the first and second processors.

Abstract: An exemplary storage apparatus of the invention includes storage devices for storing data of block I/O commands and file I/O commands and a controller including a block cache area and a file cache area. The controller creates block I/O commands from file I/O commands and accesses the storage devices in accordance with the created block I/O commands. In a case where the file cache area is lacking an area to cache first data of a received first file I/O command, the controller chooses one of a first cache method that newly creates a free area in the file cache area to cache the first data in the file cache area and a second cache method that caches the first data in the block cache area without caching the first data in the file cache area.

Abstract: Provided is a method of permitting the reordering of a visibility order of operations in a computer arrangement configured for permitting a first processor and a second processor threads to access a shared memory. The method includes receiving in a program order, a first and a second operation in a first thread and permitting the reordering of the visibility order for the operations in the shared memory based on the class of each operation. The visibility order determines the visibility in the shared memory, by a second thread, of stored results from the execution of the first and second operations.

Abstract: Techniques for reacting to events in a switch module. Embodiments provide a plurality of predefined load/store operations stored in a first memory buffer of the switch module. An execution buffer capable of storing load/store operations within the switch module is also provided. Responsive to detecting that a first predefined event has occurred, embodiments copy the plurality of predefined load/store operations from the first memory buffer to the execution buffer for execution. Upon detecting the plurality of predefined load/store operations within the execution buffer, the plurality of predefined load/store operations within the execution buffer are executed.

Abstract: An adaptive memory system is provided for improving the performance of an external computing device. The adaptive memory system includes a single controller, a first memory type (e.g., Static Random Access Memory or SRAM), a second memory type (e.g., Dynamic Random Access Memory or DRAM), a third memory type (e.g., Flash), an internal bus system, and an external bus interface. The single controller is configured to: (i) communicate with all three memory types using the internal bus system; (ii) communicate with the external computing device using the external bus interface; and (iii) allocate cache-data storage assignment to a storage space within the first memory type, and after the storage space within the first memory type is determined to be full, allocate cache-data storage assignment to a storage space within the second memory type.

Abstract: A memory device includes an on-board processing system that facilitates the ability of the memory device to interface with a plurality of processors operating in a parallel processing manner. The processing system includes circuitry that performs processing functions on data stored in the memory device in an indivisible manner. More particularly, the system reads data from a bank of memory cells or cache memory, performs a logic function on the data to produce results data, and writes the results data back to the bank or the cache memory. The logic function may be a Boolean logic function or some other logic function.

Abstract: Various embodiments relating to performing multiple computations are provided. In one embodiment, a computing system includes an off-chip storage device configured to store a plurality of stream elements and associated tags and a computation device. The computation device includes an on-chip storage device configured to store a plurality of independently addressable resident elements, and a plurality of parallel processing units. Each parallel processing unit may be configured to receive one or more stream elements and associated tags from the off-chip storage device and select one or more resident elements from a subset of resident elements driven in parallel from the on-chip storage device. A selected resident element may be indicated by an associated tag as matching a stream element. Each parallel processing unit may be configured to perform one or more computations using the one or more stream elements and the one or more selected resident elements.

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating, a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to hypervisor, allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: Provided are techniques for allocating logical memory corresponding to a logical partition in a computing system; generating a S/W PFT data structure corresponding to a first page of the logical memory, wherein the S/W PFT data structure comprises a field indicating that the corresponding first page of logical memory is a klock page; transmitting a request for a page of physical memory and the corresponding S/W PFT data structure to a hypervisor; allocating physical memory corresponding to the request; and, in response to a pageout request, paging out available logical memory corresponding to the logical partition that does not indicate that the corresponding page is a klock page prior to paging out the first page.

Abstract: Embodiments described herein are directed to providing scalability to software applications. A computer system partitions a portion of data stored in a directory services system into multiple different data partitions. Each data partition includes a primary writable copy and at least one secondary read-only copy of the data. The computer system receives a client request for a portion of the data that is stored in the directory services system and accesses various stored partition mappings to determine which of the different data partitions includes the requested data. The computer system also accesses a dynamic copy locator to determine which of the read-only copies of the indicated partition to access and provide the accessed primary writeable copy of the indicated partition and the determined read-only copy to the client in a virtualized manner so that the client is not aware of the data partitions.

Abstract: An apparatus includes a device programmer, coupled to a plurality of semiconductor fuses disposed on a die, configured to program the plurality of semiconductor fuses with compressed configuration data for a plurality of cores disposed separately on the die. The device programmer has a virtual fuse array and a compressor. The virtual fuse array is configured to store the configuration data for the plurality of cores. The configuration data includes a plurality of data types. The compressor is coupled to the virtual fuse array and is configured to read the virtual fuse array, and is configured to compress the configuration data by employing a plurality of compression algorithms to generate the compressed configuration data, where the plurality of compression algorithms correspond to the plurality of data types.

Abstract: Methods and apparatus relating to provide bimodal functionality between a coherent link and memory expansion are described. In one embodiment, a processor is coupled to one or more agents via a coherent interconnect. The processor is also coupled to one or more Dual Inline Memory Modules (DIMMs) via a link logic. The logic supports read or write commands directed at the one or more DIMMs based on a single bit of data. Other embodiments are also disclosed and claimed.

Abstract: A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

Abstract: Various systems and methods for sharing data in a virtual environment are disclosed. For example, one method involves receiving a request to access data. The request can be received from a first virtual machine of a plurality of virtual machines. The method then involves retrieving a signature for the data where the signature is stored in a deduplicated data store. Next, the method involves detecting whether the signature is included in a map. In order to do so, the method compares the signature with entries in the map. The entries in the map identify data stored in RAM. The data is also stored in the deduplicated data store. If the signature is found in the map, the method involves granting the request to access the data. Otherwise, the method involves creating a new entry in the map and adding the signature to the new entry.

Abstract: To provide delayed updating of shared data, a concept of dualistic sequence information is introduced. In the concept, if during local modification of data, a modification to the data is published by another user, a local deviation is created, and when the modification is published, it is associated with an unambiguous sequence reference and the local deviation.

Abstract: A system for writing data includes a memory, at least one memory controller and control logic. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a threshold amount. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

Abstract: Systems and methods are provided for managing performance of a computing device having dissimilar memory types. An exemplary embodiment comprises a method for interleaving dissimilar memory devices. The method involves determining an interleave bandwidth ratio comprising a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio. Memory address requests are distributed from one or more processing units to the dissimilar memory devices according to the interleave bandwidth ratio.

Abstract: A method of servicing a command sent from a host device file system (HDFS) within a host device (HD) by a local storage device (LSD) in communication with the HD is described. The method includes receiving a first command at the LSD instructing the LSD to execute an operation on associated logical addresses. If the first command is associated with at least a first set of logical addresses, the method includes servicing the first command by the LSD at least by way of sending a second command to a device (RD) external to the LSD that instructs the RD to execute an operation on memory locations within the RD. If the first command is not associated with the first set of logical addresses, the method includes servicing the first command by the LSD only by way of operations executed by the LSD on memory locations within the LSD.