Abstract: Methods and apparatuses for parallel processing data are disclosed. One method includes reading items of data from a memory using at least memory access address, confirming items of data with the same memory address among the read items of data, and masking the confirmed items of data other than one of the confirmed items of data. A correction value is generated for the memory access address using the confirmed items of data, and an operation is performed on data that has not been masked using the confirmed items of data and the correction value. Data obtained by operating on the data that has not been masked is stored as at least on representative data item for the data items with the same memory address. A schedule of a compiler of a processor is adjusted by performing bypassing of memory access address alias checking for at least one memory access address.

Abstract: A method includes generating least-recently-used location information for a shared set-associative multi-access cache and next-to least-recently-used location information for the shared set-associative multi-access cache. The method includes concurrently accessing a shared set-associative multi-access cache in response to a first memory request from a first memory requestor and a second memory request from a second memory requestor based on the least-recently-used location information and the next-to least-recently-used location information. The method may include updating the least-recently-used location information and the next-to least-recently-used location information in response to concurrent access to the shared set-associative multi-access cache according to the first memory request and the second memory request.

Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Abstract: Storage systems track free blocks using various data structures and maps. For instance, free block maps may contain data blocks with values that indicate whether a block is free or not. When an operation results in a block being freed, the relevant data block in the maps must be written during an I/O operation to update the value. Large numbers of updates my occur after an operation that frees a large numbers of blocks, which can lead to performance degradation. Accordingly, disclosed are systems and methods for deferring updating of free block data tracking structures using logs.

Abstract: Methods and systems for implementing a secure migratable architecture having improved performance features over existing virtualization systems are disclosed. One method includes allocating a portion of a memory for use by a process, the process including a firmware environment representing a virtual computing system having a second computing architecture different from a first computing architecture of a computing system on which the process is executed. The method includes associating area descriptors with each of a plurality of memory areas within the portion of the memory used by the process, and receiving a request within the firmware environment to store data within a first memory area of the plurality of memory areas, the first memory area defined by a first area descriptor of the area descriptors, the request being associated with a plurality of memory addresses within the first memory area.

Abstract: According to one embodiment, a method for controlling a nonvolatile memory includes allocating a first system block to a physical block included in one of the first and second parallel operation elements. The first system block is used by a first CPU controlling the nonvolatile memory but is not used by a second CPU controlling the nonvolatile memory. The method includes allocating a second system block to a physical block included in the other of the first and second parallel operation elements. The second system block is used by the second CPU but is not used by the first CPU.

Abstract: A computer implemented method and apparatus comprises detecting a file content update on a first client computer system, the file to be synchronized on a plurality of different types of client computer systems in a plurality of formats. The method further comprises associating a security policy with the file, wherein the security policy includes restrictions to limit one or more actions that can be performed with the file, and synchronizing the file to a second client computing system while applying the security policy to provide controls for enforcement of the restrictions at the second client computer system.

Abstract: Provided are systems and methods for distributing ordering tasks in a computing system that includes master and target devices. In some implementations, a computing device is provided. The computing device may include a master device that is operable to initiate transactions. The computing device may further include a target device that is operable to receive transactions. In some implementations, the master device may be configured to transmit one or more transactions to the target device. The master device may further asynchronously indicate to the target device a number of transactions to execute. The master device may further asynchronously receive from the target device a number of transactions executed. The master device may then signal that at least one transaction from the one or more transactions it sent has completed.

Abstract: Workload, preferably as one or more partitions, is migrated from a source server to one or more target servers by computing a respective projected performance optimization for each candidate partition and target, the optimization being dependent on a projected processor-memory affinity resulting from migrating candidate workload to the candidate target, and selecting a target to receive a workload accordingly. A target may be pre-configured to receive a workload being migrated to it by altering the configuration parameters of at least one workload currently executing on the target according to the projected performance optimization.

Abstract: Approaches for launching an application within a virtual machine. In response to receiving a request to launch an application, a device instantiates, without human intervention and based on a policy, a virtual machine in which the application is to be launched. The policy determines which resources of a device, such as a mobile device or computer system, are accessible to the virtual machine. The policy may, but need not, determine whether the virtual machine has access to a type of resource which obligates the user of the device to make a monetary payment for the user of the resource.

Abstract: An apparatus and method are disclosed for filtering an audio signal. The apparatus includes an analysis filter bank, a high frequency reconstructor or parametric stereo processor, and a synthesis filter bank. The analysis filterbank receives real-valued time domain input audio samples and generates complex valued subband samples. The high frequency reconstructor or parametric stereo processor modifies at least some of the complex valued subband samples. The synthesis filter bank receives the modified complex valued subband samples and generates time domain output audio samples. The analysis filter bank comprises analysis filters that are complex exponential modulated versions of a prototype filter with an arbitrary phase shift to reduce a complexity of the filter bank.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and second bit lines are electrically connected to one ends of the first and second memory cells, respectively. In retry reading, a voltage applied to the first bit line is different from a voltage applied to the second bit line.

Abstract: Workload, preferably as one or more partitions, is migrated from a source server to one or more target servers by computing a respective projected performance optimization for each candidate partition and target, the optimization being dependent on a projected processor-memory affinity resulting from migrating candidate workload to the candidate target, and selecting a target to receive a workload accordingly. A target may be pre-configured to receive a workload being migrated to it by altering the configuration parameters of at least one workload currently executing on the target according to the projected performance optimization.

Abstract: Embodiments disclose techniques for sharing a context for a coherent accelerator in a kernel of a computer system. According to one embodiment, a request is received from a first application to perform an I/O operation within a kernel context. The request specifies a first effective address distinct to the first application. The first effective address specifies a location in a first effective address space and a first effective segment identifier. The first effective address is remapped to a second effective address. The second effective address specifies a location in a second effective address space of the kernel context and a second effective segment identifier. A virtual address mapping to a virtual address space within the kernel context is determined. The virtual address is translated to a physical memory address.

Abstract: Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

Abstract: A memory swapping method and a data processing system using the same, the memory swapping method including receiving queue information for a memory swapping task from a host device; performing part of the memory swapping task in a storage device based on the queue information; receiving a command corresponding to the queue information from the host device after performing of the part of the memory swapping task is completed; and performing a remaining part of the memory swapping task according to the command by using a result of the part of the memory swapping task that had been previously performed.

Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a remote processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.

Abstract: A method for switching between access methods while a data set is open includes attempting, on behalf of a first system, to gain access to a data set. The method further determines whether the data set is already open by a second system. In the event the data set is already open, the method uses a first access method to access the data set. In the event the data set is not already open, the method uses a second access method to access the data set. In certain embodiments, the first access method is an RLS (Record Level Sharing) access method and the second access method is a base VSAM (Virtual Storage Access Method) access method. A corresponding system and computer program product are also disclosed.

Abstract: A technique allows for memory bounds checking for dynamically generated code by using transactional memory support in a processor. The memory bounds checking includes creating output code, identifying read-only memory regions in the output code and creating a map that is provided to a security monitoring thread. The security monitoring thread executes as a transaction and determines if a transactional conflict occurs to the read-only memory region during parallel execution of a monitored thread in the output code.

Abstract: A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

Abstract: A wind turbine is provided. The wind turbine includes a plurality of control systems. The wind turbine further includes a reflective memory system. The plurality of control systems is coupled with the reflective memory system. Each of the plurality of control systems may include a respective memory of the reflective memory system. In response to data being written into one of the respective memories, the reflective memory system may automatically replicate the data to other respective memories.

Abstract: In a computer supporting Transactional Memory (TM) Transaction Execution (TX), use of speculative branch prediction is programmably suspended during TX, and programmably resumed. The branch prediction suspension may cause the execution of one or more instructions following the branch instruction to stall in the pipeline until branch conditions and branch target addresses are resolved.

Abstract: Some audio processing methods may involve receiving audio data corresponding to a plurality of audio channels and determining audio characteristics of the audio data, which may include transient information. An amount of decorrelation for the audio data may be based, at least in part, on the audio characteristics. If a definite transient event is determined, a decorrelation process may be temporarily halted or slowed. Determining transient information may involve evaluating the likelihood and/or the severity of a transient event. In some implementations, determining transient information may involve evaluating a temporal power variation in the audio data. Explicit transient information may or may not be received with the audio data, depending on the implementation. Explicit transient information may include a transient control value corresponding to a definite transient event, a definite non-transient event or an intermediate transient control value.

Abstract: In one embodiment, an apparatus comprises a decompression engine to perform a non-speculative decode operation on a first portion of a first compressed payload comprising a first plurality of codes; and perform a speculative decode operation on a second portion of the first compressed payload, wherein the non-speculative decode operation and the speculative decode operation share at least one decode path and the non-speculative decode operation is to utilize bandwidth of the at least one decode path that is not used by the non-speculative decode operation.

Abstract: A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.

Abstract: A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.

Abstract: A tool for use in a wellbore comprising a seal assembly and a cone member configured to force the seal assembly radially outward into engagement with the wellbore. A shear thickening fluid is disposed within an area formed between the seal assembly and the cone member. The shear thickening fluid is configured to prevent relative movement between the cone member and the seal assembly when the shear thickening fluid is changed from a substantially fluid state to a substantially solid state due to a sudden force applied to the shear thickening fluid, by release of a sheared mechanism for example.

Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.

Abstract: Functionality is disclosed herein for monitoring an execution environment to determine if the execution environment is in an approved configuration. Memory used by the execution environment may be scanned from outside of the execution environment to determine whether the execution environment is in an unapproved configuration. The scanning may include examining the memory for abnormalities or other irregular or unapproved data. When the execution environment is in the unapproved configuration, actions may be performed that change how the execution environment accesses resources or performing other types of functionality.

Abstract: Image data output from an image capturing unit is input to an image processing circuit, and the image processing circuit is connected in cascade to another image processing circuit. With the image processing circuit, a portion of the image data for which processing is shared is processed by the image processing circuit, the processed image data is multiplexed by a multiplexing unit with another portion of the image data to be processed by the other image processing circuit, and is transmitted to the other image processing circuit by an output IF unit. The other image processing circuit processes its share of the image data and displays it along with the processed image data received from an image processing unit.

Abstract: A page table is a data structure used by a virtual memory system in a computer system to store the mapping between virtual addresses and physical addresses. Embodiments herein use a tree to map a virtual memory address space in the page table. The tree may be an N-ary tree where N is a power of two (e.g., 2, 4, 8, 16, etc.). The tree may include multiple levels that each correspond to a different page table size. For example, an octree includes eight different entries for each child node which may include per-thread sub-entries. Child nodes in the first level of the octree may each correspond to a 512 GiB page, while child nodes in the second level, however, may each have eight entries that correspond to a 64 GiB page. In this manner, an N-ary tree may be used to support a computing system with varying page sizes.

Abstract: A system includes an input/output adapter that includes a multi-source selector coupled to a flow-through input, an elastic first-in-first-out (FIFO) structure, a completion queue, and an output bus. A controller is operatively connected to the input/output adapter. The controller is operable to select the flow-through input to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure is empty. The elastic FIFO structure is selected to pass through the multi-source selector to the output bus based on determining that the elastic FIFO structure includes at least one entry. The completion queue is selected to pass through the multi-source selector to the output bus based on determining that the completion queue includes at least one entry. The flow-through input is routed into the elastic FIFO structure based on the completion queue being selected to pass through the multi-source selector to the output bus.

Abstract: A system and method for processor-based security is provided, for on-chip security and trusted computing services for software applications. A processor is provided having a processor core, a cache memory, a plurality of registers for storing at least one hash value and at least one encryption key, a memory interface, and at least one on-chip instruction for creating a secure memory area in a memory external to the processor, and a hypervisor program executed by the processor. The hypervisor program instructs the processor to execute the at least one on-chip instruction to create a secure memory area for a software area for a software module, and the processor encrypts data written to, and decrypts data read from, the external memory using the at least one encryption key and the verifying data read from the external memory using the at least one hash value.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: Embodiments of the invention relate to tracking processor transactional read and write sets, thereby eliminating speculative mispredictions. Both non-speculative read set and write set indications are maintained for a transaction. The indications are stored in cache. In addition, load and write queues of addresses are maintained. The load queue of addresses relates to speculative members of a read set and the write queue of addresses relates to speculating member of a write set. For a received read request, a transaction resolution process takes place, and a resolution is performed if an address match in the write queue is detected. Similarly, for a receive write request the transaction interference additionally checks the load queue and the non-speculative read set for the pending address.

Abstract: Techniques are disclosed for using contextual information to determine an appropriate response in a system that includes a device paired with an accessory device. The contextual information can be sourced from local sensors, received communications, and information stored on a device within the system. Stored parameters in the system allow flexibility and configurability in evaluating the contextual information. Using feedback obtained after actions taken based on the contextual information allows the system to adapt to better meet the needs of the user.

Abstract: A method and system for dynamically managing memory in a computing environment using a control monitor. The control monitor (e.g., a virtual machine monitor or operating system kernel) includes a nomination module configured to collect memory statistics associated with at least one memory node. Based on the memory statistics, the control monitor detects one or more first pages accessed from a remote memory node at or above an access threshold. The nomination module nominates, via a communication to at least one of a scheduler module and a memory manager of the control monitor, the one or more first pages for migration to the remote memory node.

Abstract: According to one embodiment of the present invention, a method is provided. The method may include a computer registering a first instance of a logical partition on a source server with a logical unit and placing a first persistent reservation on the logical unit, wherein the first persistent reservation indicates that only the first instance of the logical partition can hold a reservation on the logical unit. The method may further include the computer registering a second instance of the logical partition on a destination server with the logical unit and downgrading the first persistent reservation, such that the first and second instances of the logical partition can hold persistent reservations on the logical unit. The method may further include the computer placing, by one or more computer processors, a second persistent reservation on the logical unit.

Abstract: File sharing circuit and computer using the same are provided. The computer includes a computer host and a file sharing circuit. The computer host includes a first storage device, a first system control chip, a control unit, and a power integrated circuit. The file sharing circuit includes a second system control chip and a first bus switch. When the second system control chip performs a file sharing procedure, the power integrated circuit powers the first storage device, the second system control chip, and the first bus switch, and the control unit switches the first bus switch to a first state so that the second system control chip accesses the first storage device. When the second system control chip does not perform the file sharing procedure, the control unit switches the first bus switch to a second state so that the first system control chip accesses the first storage device.

Abstract: A processor maintains a count of accesses to each memory page. When the accesses to a memory page exceed a threshold amount for that memory page, the processor sets an indicator for the page. Based on the indicators for the memory pages, the processor manages data at one or more levels of the processor's memory hierarchy.

Abstract: A method and apparatus of memory management are disclosed. Pooling of at least one memory to generate a memory pool, dividing the memory pool to generate at least one memory space, and allocating a respective memory space to a respective CPU in a one-to-one correspondence manner are performed. Further, the respective memory space allocated to the respective CPU is set as a pinned memory of the respective CPU. Additionally, setting unallocated memory space as a shared memory pool, obtaining a memory value that represents usage of the respective memory space by the respective CPU during operation, and determining if the memory value exceeds a preset threshold range are performed. Selecting, if the memory value exceeds the preset threshold range, additional memory space from the memory pool to allocate to the respective CPU or reallocating at least a portion of the respective memory space allocated to the CPU are performed.

Abstract: Examples of techniques for processing I/O operations in a channel are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: copying, by a system assist processor, a subchannel of the channel into a lower portion of a channel communication area responsive to receiving the I/O operation; copying, by the system assist processor, channel program information from a designated starting location in a customer memory into a control block; building, by the system assist processor, a starting channel communication area into a top portion of the control block; queuing, by the system assist processor, the control block to a queue for the channel; processing, by the channel, the I/O operation responsive to retrieving the control block from the queue.

Abstract: According to one embodiment of the present invention, a method is provided. The method may include a computer registering a first instance of a logical partition on a source server with a logical unit and placing a first persistent reservation on the logical unit, wherein the first persistent reservation indicates that only the first instance of the logical partition can hold a reservation on the logical unit. The method may further include the computer registering a second instance of the logical partition on a destination server with the logical unit and downgrading the first persistent reservation, such that the first and second instances of the logical partition can hold persistent reservations on the logical unit. The method may further include the computer placing, by one or more computer processors, a second persistent reservation on the logical unit.

Abstract: In accordance with the disclosed subject matter, systems and methods are provided for improving performance of a versioned database. Embodiments include systems and methods for improving performance of versioned databases by selectively loading portions of database files on disk into memory. Embodiments also include systems and methods for capturing and consolidating or condensing transaction logs into database files for loading.

Abstract: A tag and a method of writing data to memory of a tag are provided. The tag includes memory that stores data elements as well as an access control list that maps access keys to the data elements. An authentication protocol is employed by the tag to determine whether a data element received from a writing device will be written to the memory.

Abstract: A second memory allocator receives a request to allocate memory from a second process of the second memory allocator executing on a computer, and determines that memory for allocation to the second process is not available from a memory hoard of the second memory allocator. The second memory allocator determines that memory for allocation to the second process is not available from an operating system of the computer, and transmits the request to release memory to a first memory allocator. The first memory allocator of a first process executing on the computer receives the request from the second memory allocator executing on the computer to release memory. Responsive to the request from the second memory allocator to release memory, the first memory allocator releases hoarded memory previously hoarded for allocation to the first process.

Abstract: The file storage system includes a controller and a volume storing a plurality of files, the volume including a first directory storing a first file and a second file and a second directory storing a third file being created. The controller migrates actual data of the second file to the third file, sets up a management information of the second file so that the third file is referred to when the second file is read, and if the sizes of actual data of the first file and the actual data of the third file are identical and the binaries of the actual data of the first file and the actual data of the third file are identical, sets up a management information of the first file to refer to the third file when reading the first file.

Abstract: A method to convert lock-free algorithm to wait-free using a hardware accelerator includes (i) executing a plurality of software threads by a plurality of processing units associated, the plurality of software threads is associated with at least one operation, (ii) generating at least one of a read request or a write request at the hardware accelerator based on the execution, (iii) generating at least one operation includes PARAM and read request or the write request at the hardware accelerator, (iv) checking, an operation specific condition of at least one software thread of the plurality of software threads, and (v) updating, at least one read value or write value and at least one state variable upon the operation specific condition being an operation success. The operation specific condition includes an operation success or an operation failure based on the PARAM, the read request, or the write request.