Abstract: Subject matter disclosed herein relates to performing concurrent memory operations.

Abstract: Systems, methods, and computer-readable media for optimizing emulated fixed-function and programmable graphics operations are provided. Data comprising fixed function and programmable states for an image or scenario to be rendered is received. The data for the image is translated into operations. One or more optimizations are applied to the operations. The optimized operations are implemented to render the scenario.

Abstract: A method for thread address mapping in a parallel thread processor. The method includes receiving a thread address associated with a first thread in a thread group; computing an effective address based on a location of the thread address within a local window of a thread address space; computing a thread group address in an address space associated with the thread group based on the effective address and a thread identifier associated with a first thread; and computing a virtual address associated with the first thread based on the thread group address and a thread group identifier, where the virtual address is used to access a location in a memory associated with the thread address to load or store data.

Abstract: An apparatus comprising an arbiter circuit, a translation circuit and a controller circuit. The arbiter circuit may be configured to generate one or more first control signals and a data write signal in response to an input signal and a read data signal. The translation circuit may be configured to generate a one or more second control signals in response to the one or more first control signals and the write address signal. The controller circuit may be configured to generate an address signal in response to the one or more second control signals.

Abstract: A storage device is disclosed, in which the device comprises memory (222) divisible into multiple zones, each zone comprising a plurality of physical blocks of the memory (222) and for associating with a zone-based address map for mapping between logical and physical addresses of said zone. The multiple zones are configurable independently of each other, and the memory (222) is non-volatile or volatile memory. A related zone-based block management and address mapping method, and a zone-based block management and address map for a storage device are also disclosed.

Abstract: Operating system virtual memory management for hardware transactional memory. A system includes an operating system deciding to unmap a first virtual page. As a result, the operating system removes the mapping of the first virtual page to the first physical page from the virtual memory page table. As a result, the operating system performs an action to discard transactional memory hardware state for at least the first physical page. Embodiments may further suspend hardware transactions in kernel mode. Embodiments may further perform soft page fault handling without aborting a hardware transaction, resuming the hardware transaction upon return to user mode, and even successfully committing the hardware transaction.

Abstract: Each actual page inside a pool is configured from a plurality of actual tracks, and each virtual page inside a virtual volume is configured from a plurality of virtual tracks. A storage control apparatus of a mainframe system has management information that includes information denoting a track in which there exists a user record, which is a record including user data (the data used by a host apparatus of a mainframe system). Based on the management information, a controller identifies an actual page that is configured only from tracks that do not comprise the user record, and cancels the allocation of the identified actual page to the virtual page.

Abstract: A request is received to clone a source data object. A source block range of the source data object in a source logical storage unit is determined. An empty data object in the destination logical storage unit is created. A destination block range of the empty data object in the destination logical storage unit is determined. The source block range is mapped to the destination block range. The source data object is cloned based on the mapping.

Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.

Abstract: A cache management method using checkpoint tags in checkpoint mode includes steps of: receiving a request to save data; fetching at least one cache block including the data from cache memory; writing the data from the at least one cache block into the data array; writing a physical address and metadata of the cache block into an array of cache memory tags; and upon receipt of a restore request: fetching an identifier for the at least one cache block stored in the checkpoint tag array; reloading the cache memory with the at least one cache block in the checkpoint tag array; and switching to normal mode.

Abstract: The storage system of the present invention is able to generate one virtual logical device from different logical devices which exist in each of the different storage control units and remote-copy all or part of the virtual logical device to another logical device. The same virtual identifier is set for a volume of the first storage unit and for a volume of the second storage unit. The path control unit of the host identifies a plurality of volumes which have the same virtual identifier as one virtual volume. A remote copy pair can also be set by a virtual volume and a volume of the third storage unit. The setting of the virtual volume and the setting of the remote copy can be performed by means of an instruction from the management server.

Abstract: Conventionally, when a switch virtualizing a storage (storage virtualization switch) is installed in a computer system including an SAN, a host computer, and a storage device, since a port ID of a virtual storage and a port ID of a storage device assigned to the virtual storage are different, the computer system has to be suspended at the time of installation of the storage virtualization switch. The storage virtualization switch installed in the computer system assigns a port ID to a port of a virtual storage generated by the storage virtualization switch so as to be equivalent to a port ID of an existing storage device and, in the case in which the port ID is designated as an access destination by an access request from one computer to the storage device, sends the access request to the virtual storage.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial origin address of a translation table of the hierarchy of translation tables is obtained. Based on the obtained initial origin, a segment table entry is obtained. The segment table entry is configured to contain a format control and access validity fields. If the format control and access validity fields are enabled, the segment table entry further contains an access control field, a fetch protection field, and a segment-frame absolute address. Store operations are permitted only if the access control field matches a program access key provided by any one of a Program Status Word or an operand of a program instruction being executed. Fetch operations are permitted if the program access key associated with the virtual address is equal to the segment access control field.

Abstract: The statuses of an actual area are (1) a first status which indicates that [the actual area] is already initialized and can be assigned to a virtual area, (2) a second status which indicates that [the actual area] is already assigned to a virtual area, and (3) a third status which indicates that [the actual area] cannot be assigned to a virtual area and initialization which is specified data write is to be performed. The storage controller limits the total virtual volume capacity which is the total capacity of one or more virtual volumes which are associated with the pool, in accordance with whether the pool comprises an actual page in the third status or not, to the capacity of the pool or smaller.

Abstract: A method of tier management of data comprises performing a tier migration log information setup process which includes selecting an area specified by a virtual volume address and a logical volume address; determining a destination tier for the area based on a number of accesses to the area; and updating a tier migration log information by inputting the determined destination tier and a time; and performing a process using the tier migration log information to determine whether to migrate a specific area which includes loading a tier migration log from the tier migration log information by selecting a specific time; checking if a current tier of the specific area equals a destination tier specified by the tier migration log; and if the current tier is not equal to the destination tier, migrating the specific area to the destination tier.

Abstract: In one embodiment, a method includes reserving extents in a storage pool, reading data from a first portion of an in-use RAID arranged according to a first array configuration, using the reserved extents in the storage pool to store a first portion of the data for writing to the in-use RAID, using one or more free extents in the storage pool or in the in-use RAID to store a second portion of the data for writing to the in-use RAID, writing the data to a second portion of the in-use RAID arranged according to a second array configuration, performing one or more first I/O operations according to the first array configuration, wherein the one or more first I/O operations are performed on the data before the data is read by the data migrating component, and performing one or more second I/O operations according to the second array configuration.

Abstract: A mechanism is provided for attributing network addresses to virtual machines. A request for a number of addresses is received from a requesting entity, thereby forming a requested number of addresses. A length of continuous ranges of available addresses is compared to the requested number of addresses. A range of available addresses comprising a number of addresses greater than the requested number of addresses is selected from a memory, thereby forming a selected range of available addresses. A first new range comprising the requested number of addresses excised from the selected range of available addresses is defined and one or more further new ranges are defined comprising the remainder of the selected range of available addresses not belonging to the first new range. The first new range is attributed for the use of the requesting entity.

Abstract: In general, the present invention relates to data cache processing. Specifically, the present invention relates to a system that provides reconfigurable dynamic cache which varies the operation strategy of cache memory based on the demand from the applications originating from different external general processor cores, along with functions of a virtualized hybrid core system. The system includes receiving a data request, selecting an operational mode based on the data request and a predefined selection algorithm, and processing the data request based on the selected operational mode. The system is further configured to delegate computational or memory resource needs to a plurality of sub-processing cores for processing to satisfy application demands.

Abstract: A storage apparatus and its control method capable of implementing thin provisioning and reducing power consumption of storage devices are provided. The storage apparatus classifies a plurality of storage devices, which provide a pool with a storage resource, into a plurality of groups; performs thin provisioning operation by setting some of the plurality of groups to an active mode, in which the storage devices belonging to the groups are made to enter an activated state; sets other groups to a power-saving mode in which the storage devices are made to enter a power-saving state; and sequentially switches between the group(s) in the active mode and the group(s) in the power-saving mode among the plurality of groups.

Abstract: According to one embodiment, a computer program product includes a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to receive a mount request to access at least one host data record on a virtual tape storage (VTS) system; computer readable program code configured to determine a number of host compressed data records per physical block on a magnetic tape medium; computer readable program code configured to determine a physical block ID (PBID) that corresponds to the requested at least one host data record; computer readable program code configured to access a physical block on the magnetic tape medium corresponding to the PBID; and computer readable program code configured to output the physical block without outputting an entire logical volume from the magnetic tape medium that the physical block is stored to. Other systems and computer program products are also described.

Abstract: Systems and/or methods that provide for frequency distributed flash memory allocation are disclosed. The systems and methods determine the rate at which a system address is being written and the current erase cycle state of each data block in the non-volatile memory device and assigns a physical address to the write operation based on the determined system address rate and the current erase state of each data block in the non-volatile system. In this regard, system addresses that are assigned more frequently are assigned physical page addresses from data blocks which have a low erase cycle state (i.e., greater cycle endurance remaining) and system addresses that assigned less frequently are assigned physical page addresses from data blocks which have a high erase cycle state (i.e., lesser cycle endurance remaining). The result is a more robust non-volatile device having increased erase/initialization cycle endurance, which adds to the overall reliability of the device over time.

Abstract: A computer-readable storage medium has stored therein an information processing program that causes a computer of an information processing apparatus to operate as: means for sequentially obtaining an image; means for detecting a specific object from the obtained image; means for detecting, on the basis of a first threshold and a pixel value obtained from a first region of the detected specific object, first region information on the first region; calculation means for calculating a second threshold on the basis of the pixel value obtained from the first region when the first region information is detected; means for detecting, on the basis of the second threshold calculated by the calculation means and a pixel value obtained from a second region of the detected specific object that is different from the first region, second region information on the second region; and means for outputting at least the second region information detected.

Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.

Abstract: In computer system simulations, previous translations of simulation virtual addresses to physical host addresses can be remembered in a cache. During execution of a simulation program, the simulated computer system generates a simulation virtual address. The simulation virtual address may be translated to a host address. Information associated with the translation can be cached, and subsequent accesses to the simulation virtual address can use the cached information to compute the host address.

Abstract: According to one embodiment of the present invention, a method for operating a memory device that includes memory and a processing element includes receiving, in the processing element, a command from a requestor, loading, in the processing element, a program based on the command, the program comprising a load instruction loaded from a first memory location in the memory, and performing, by the processing element, the program, the performing including loading data in the processing element from a second memory location in the memory. The method also includes generating, by the processing element, a virtual address of the second memory location based on the load instruction and translating, by the processing element, the virtual address into a real address.

Abstract: Methods, apparatus, and systems, including computer programs encoded on a computer storage medium, manage metadata for virtual volumes. In some implementations, a method includes: loading into memory at least a portion of metadata for a virtual volume (VV) that spans data extents of different persistent storage devices, wherein the metadata comprises virtual metadata block (VMB) descriptors and virtual metadata blocks (VMBs); mapping an address of the VV to a VMB number and an index of an extent pointer within a VMB identified by the VMB number, wherein the extent pointer indicates an extent within one of the different persistent storage devices; locating a VMB descriptor in the memory based on the VMB number; and locating the identified VMB in the memory or not in the memory based on the located VMB descriptor.

Abstract: An audio decoder includes an arithmetic decoder for providing a plurality of decoded spectral values on the basis of an arithmetically encoded representation of the spectral values, and a frequency-domain-to-time-domain converter for providing a time-domain audio representation using the decoded spectral values. The arithmetic decoder selects a mapping rule describing a mapping of a code value onto a symbol code in dependence on a context state described by a numeric current context value. The arithmetic decoder determines the numeric current context value in dependence on a plurality of previously decoded spectral values. The arithmetic decoder evaluates a hash table, entries of which define both significant state values and boundaries of intervals of numeric context values, in order to select the mapping rule. A mapping rule index value is individually associated to a numeric context value being a significant state value.

Abstract: A second storage maps a migration source volume to a virtual volume of a migration destination volume according to storage virtualization technology. A host system including a host switches an access path from an access path to the migration source volume to an access path to the migration destination volume. The second storage executes copy processing of migrating, from the migration source volume to the migration destination volume, data in an assigned area of a virtual volume according to thin provisioning of the migration source volume based on the information contained in the first thin provisioning information in the first storage, and copying that data from the migration destination volume to a virtual volume according to thin provisioning of a copy destination volume in the second storage. The second storage associates the virtual volume of the copy destination volume with the migration destination volume in substitute for the original virtual volume.

Abstract: A mechanism is provided in a computing system for controlling virtualized storage operable to communicate with a host and with mapped and unmapped storage resource pools. A selection component selects a target for a destructive data storage operation from the mapped storage resource pool. Responsive to the selection of the target, a virtual targeting component creates a virtual target from the unmapped storage resource pool to represent the target. Responsive to the selection of the target, a storage move component moves the target to a protected storage resource pool. Responsive to the creation of the virtual target from the unmapped storage resource pool, storage move component, moves the virtual target to the used storage resource pool. The computing system then performs the destructive data storage operation on the virtual target.

Abstract: An input/output (I/O) device includes a host interface for connection to a host device having a memory, and a network interface, which is configured to transmit and receive, over a network, data packets associated with I/O operations directed to specified virtual addresses in the memory. Processing circuitry is configured to translate the virtual addresses into physical addresses using memory keys provided in conjunction with the I/O operations and to perform the I/O operations by accessing the physical addresses in the memory. At least one of the memory keys is an indirect memory key, which points to multiple direct memory keys, corresponding to multiple respective ranges of the virtual addresses, such that an I/O operation referencing the indirect memory key can cause the processing circuitry to access the memory in at least two of the multiple respective ranges.

Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

Abstract: A method for managing resources in a storage pool of external virtual memory, that includes a host manager being associated with a storage pool by a storage manager. The host manager manages the resources, the managing including creating resources in the storage pool and/or deleting resources in the storage pool. The host manager further accesses the resource in the pool, such accessing including reading data to or writing data to the resource.

Abstract: A plurality of modules (1) and (2) comprise a plurality of virtual volumes with which the same volume identification number is associated. A module (2), which receives a write request from a computer, searches for an unallocated real area from among a plurality of real areas in the module (2) rather than from among a plurality of real areas in the other module (1) if a real area has not been allocated to a write-targeted virtual area in accordance with the write request. The module (2) allocates the real area retrieved from the module (2) to the write-targeted virtual area, and writes data according to the write request to this real area.

Abstract: A virtual device control method of a computing device which includes a nonvolatile memory is provided. The virtual device control method includes receiving a virtualization request; assigning a first part of the nonvolatile memory to a virtual memory; assigning a second part of the nonvolatile memory to a virtual storage; and generating a virtual device including the assigned virtual memory and virtual storage.

Abstract: Described embodiments provide for restructuring a scheduling hierarchy of a network processor having a plurality of processing modules and a shared memory. The scheduling hierarchy schedules packets for transmission. The network processor generates tasks corresponding to each received packet associated with a data flow. A traffic manager receives tasks provided by one of the processing modules and determines a queue of the scheduling hierarchy corresponding to the task. The queue has a parent scheduler at each of one or more next levels of the scheduling hierarchy up to a root scheduler, forming a branch of the hierarchy. The traffic manager determines if the queue and one or more of the parent schedulers of the branch should be restructured. If so, the traffic manager drops subsequently received tasks for the branch, drains all tasks of the branch, and removes the corresponding nodes of the branch from the scheduling hierarchy.

Abstract: What is provided is a load page table entry address function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which contains an opcode indicating that a load page table entry address function is to be performed. The machine instruction contains an M field, a first field identifying a first general register, and a second field identifying a second general register. Based on the contents of the M field, an initial origin address of a hierarchy of address translation tables having at least one segment table is obtained. Based on the obtained initial origin address, dynamic address translation is performed until a page table entry is obtained. The page table entry address is saved in the identified first general register.

Abstract: A storage apparatus connectable to another storage apparatus so as to copy the data thereto, for providing a first virtual volume including at least a first block, includes at least a storage unit having storage areas, each storage area being allocatable as a one of the first blocks; a memory storing information for indicating a relationship between each first block and each the storage area, at least one of the storage areas being allocated to the at least one of the first blocks according to a usage pattern of the first virtual volume; and a controller configured to receive an instruction for copying data, determine whether each first block is allocated to any of the storage areas or not in reference to the information, transmit data indicating that one of the first blocks is unallocated to any of the first storage areas on the basis of the determination.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

Abstract: An externally-connected volume of a main storage is correlated to an AOU volume inside of an external storage. The AOU volume is allocated with a not-yet-used page in a pool in accordance with data writing. When a command is issued to the externally-connected volume for formatting or others, a first controller in the main storage converts the command into a format command or an area deallocation command with respect to the AOU volume in the external storage. As such, the external AOU volume is subjected to a write process in its entirety, thereby being able to prevent any unnecessary page allocation. With such a configuration, the storage system of the present invention can use pages in the pool with good efficiency.

Abstract: A data processing apparatus and method have a processor for executing instructions, and a prefetch unit for prefetching instructions from memory prior to sending those instructions to the processor for execution. A branch target cache structure has a plurality of entries, where the cache structure comprises an initial branch target cache having a first number of entries and a promoted entry branch target cache having a second number of entries. During lookup operation, both the initial entry branch target cache and the promoted entry branch target cache are accessed in parallel. For a branch instruction executed by the processor that does not currently have a corresponding entry in the branch target cache structure, allocation circuitry performs an initial allocation operation to allocate one of the entries in the initial entry branch target cache for storing the branch instruction information for that branch instruction.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory buffer in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: A translation table entry contains a change recording override field for controlling whether a change bit is to be set on a store or not. Each 4K byte block of main storage has an associated storage key comprising a change bit. The change recording override field controls whether the change bit of the storage key associated with the desired 4K byte block of main storage is set to 1 for a store operation.

Abstract: A method and system for managing direct memory access (DMA) in a computer system that hosts virtual machines and allows memory overcommit. The computer receives an indication that a bus address is to be used by a device to perform DMA to a buffer. In response to the indication, the computer determines a host device identifier for the device, and pins a memory page addressed by a host address that is associated with the bus address and a guest address. The computer also records, in a host I/O memory management unit (IOMMU), a mapping of the bus address and the host device identifier to the host address. After the device completes the DMA, the computer removes the mapping from the host IOMMU to prevent further direct access to the host address.

Abstract: An embodiment of the invention provides a method for organizing data addresses within a virtual address space to reduce the number of data fetches to a cloud computing environment. More specifically, data access requests to the cloud computing environment are monitored to identifying data addresses having similar properties. Multi-dimensional clusters are created based on the monitoring to group the data addresses having similar properties. A memory page is created from a multi-dimensional cluster, wherein the creating of the memory page includes creating a cross-sectional partition from the multi-dimensional cluster. The multi-dimensional clusters and the memory page are stored in the cloud computing environment. A request for a data object in the cloud computing environment is received from a user interface. The data address corresponding to the data object is identified and mapped to the multi-dimensional cluster and/or the memory page. The memory page is transferred to the user interface.

Abstract: A method for accessing a virtual memory of a processor using a processor-bus-connected flash storage module (PFSM) as a first paging device and a hard disk drive (HDD) as a second paging device, the method including: allocating a first address partition and a second address partition of a virtual memory for a software application of a processor to the first paging device and the second paging device, respectively, identifying a virtual memory page in the first paging device responsive to a page fault of the virtual memory triggered by the software application, sending a page access request to the PFSM for accessing the virtual memory page responsive to the page fault, and receiving the virtual memory page from the PFSM based on a command of the processor bus issued by the PFSM in conjunction with performing a flash memory access in the flash memory using a flash page address.

Abstract: A method and system for simulating in software a digital computer system by performing virtual to physical translations of simulated instructions is disclosed. The number of virtual to physical translations using hash lookups is reduced by analyzing sequences of the instructions for determining with high probability whether the memory accesses made by the instructions perform the same virtual to physical translation in order to reduce the number of necessary hash lookups to enable faster simulation performance.

Abstract: What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. An index portion of the virtual address is used to reference an entry in the translation table. If a format control field contained in the translation table entry is enabled, the table entry contains a frame address of a large block of data of at least 1M byte in size. The frame address is then combined with an offset portion of the virtual address to form the translated address of a small 4K byte block of data in main storage or memory.

Abstract: Virtual tape libraries (VTLs) and methods for concurrently accessing a VTL are provided. One VTL includes memory partitioned into multiple volumes, multiple virtual drives, and a processor. The processor is configured to enable multiple applications to concurrently access a virtual storage volume in a first or second access mode. One method includes receiving a first request for a first application to access a virtual storage volume to write data to or read data from the virtual storage volume and granting the first request. The method further includes receiving a second request for a second application to concurrently access the virtual storage volume to write data to or read data from the virtual storage volume, determining if the first and second requests are compatible, and accepting or denying the second request based on the determination. Also provided are physical computer storage mediums including computer code for performing the above method.

Abstract: Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.