Virtual Addressing Patents (Class 711/203)
-
Patent number: 8521988Abstract: A control method of a virtual memory is adapted for using in a computer. The control method includes the following steps. First, a plurality of application programs executed in the computer are monitored. Second, the application programs are compared with at least a predetermined program, respectively. Third, the virtual memory of a solid state disk (SSD) is controlled to be turned on or turned off according to a comparing result. Herein, the virtual memory of the SSD is controlled to be turned on or turned off to enhance both lifetime of the SSD and operation efficiency of the computer.Type: GrantFiled: January 7, 2010Date of Patent: August 27, 2013Assignee: ASUSTeK Computer Inc.Inventors: Chun-Kai Chan, Li-Hsiang Liao, Ya-Shu Juang
-
Patent number: 8516218Abstract: In an embodiment of the invention, an apparatus and method for storage space management performs the steps including: activating a logical volume group; reading pattern-based mapping information from physical volumes in the logical volume group; and using the pattern-based mapping information to determine a target physical extent in at least one of the physical volumes for a received request.Type: GrantFiled: October 30, 2006Date of Patent: August 20, 2013Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jonathan M. Sauer, Sesidhar Baddela, Jean-Marc P. Eurin, Jorge Valle
-
Patent number: 8516163Abstract: A serial buffer includes queues configured to store data packets received from a host. A direct memory access (DMA) engine receives data packets from the highest priority queue having a water level that reaches a corresponding watermark. The DMA engine is configured in response to a DMA register set, which is selected from a plurality of DMA register sets. The DMA register set used to configure the DMA engine can be selected in response to information in the header of the read data packet, or in response to the queue from which the data packet is read. Each DMA register set defines a corresponding buffer in system memory, to which the data packet is transferred. Each DMA register set also defines whether the corresponding buffer is accessed in a wrap mode or a stop mode, and whether doorbell signals are generated in response to transfers to the last address in the corresponding buffer.Type: GrantFiled: February 27, 2007Date of Patent: August 20, 2013Assignee: Integrated Device Technology, Inc.Inventors: Chi-Lie Wang, Bertan Tezcan
-
Patent number: 8516219Abstract: Memory mapping techniques for non-volatile memory are disclosed where logical sectors are mapped into physical pages using data structures in volatile and non-volatile memory. In some implementations, a first lookup table in non-volatile memory maps logical sectors directly into physical pages. A second lookup table in volatile memory holds the location of the first lookup table in non-volatile memory. An index cache tree in volatile memory holds the physical addresses of the most recently written or accessed logical sectors in a compressed format.Type: GrantFiled: July 24, 2009Date of Patent: August 20, 2013Assignee: Apple Inc.Inventors: Daniel Jeffrey Post, Nir Jacob Wakrat, Vadim Khmelnitsky
-
Patent number: 8516433Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.Type: GrantFiled: June 25, 2010Date of Patent: August 20, 2013Assignee: Cadence Design Systems, Inc.Inventors: Thaddeus Clay McCracken, Miles P McGowan
-
Patent number: 8510759Abstract: Systems and methods may provide for receiving a scatter/gather list that identifies a contiguous data block in a physical memory, and splitting the contiguous data block into a first data packet payload and a second data packet payload based on a target packet size. Additionally, another contiguous data block can be combined into one of the first and second data packet payloads based on the target packet size, wherein the first and second data packet payloads may be transferred in a data stream through a host interface that does not support scatter/gather lists. In one example, a software driver is used to split and combine the contiguous data blocks.Type: GrantFiled: June 29, 2012Date of Patent: August 13, 2013Assignee: Intel CorporationInventor: Steven Mcgowan
-
Patent number: 8510532Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.Type: GrantFiled: April 6, 2012Date of Patent: August 13, 2013Assignee: Imation Corp.Inventor: Arunprasad Ramiya Mothilal
-
Patent number: 8509603Abstract: This invention provides an information processing method and apparatus, which can set all extent sizes of data divisionally recorded on a disk to be equal to or larger than the minimum recording unit, and can guarantee continuous reproduction of the divisionally recorded data. Of data divisionally recorded on a recording medium (5), data which corresponds to an end portion of that data and cannot be recorded as a recording area equal to or larger than a minimum recording unit specified in the recording medium (5) due to the presence of a recording area (6) of another data, that has already been recorded on the recording medium (5), is re-recorded on a recording area equal to or larger than the minimum recording unit. At this time, new data is generated by combining data less than the minimum recording unit, and data recorded in another recording area, and the new data is re-recorded on a new recording area.Type: GrantFiled: September 3, 2009Date of Patent: August 13, 2013Assignee: Canon Kabushiki KaishaInventor: Ikuo Watanabe
-
Patent number: 8510517Abstract: For betterment, by putting a virtual storage device into a suspend mode, physical resources are turned OFF on a virtual storage device basis. Moreover, control information and volume data of the virtual storage device are stored in any external volume, for example, and the resources that have been used by the virtual storage device are deallocated. At the time of resumption of operation, using any resources not in use, the virtual storage device is restored based on the control information in storage. When a change is made to a WWN on the side of a host, the storage device receives a WWN change notification from a management server, and makes settings again to a WWN table, thereby making it accessible from the host.Type: GrantFiled: November 17, 2008Date of Patent: August 13, 2013Assignee: Hitachi, Ltd.Inventors: Hiroaki Akutsu, Kazuyoshi Serizawa, Yoshiki Kano
-
Patent number: 8504794Abstract: A memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for virtualizing context memory storage and independently controlling access to the context memory without interference from other engine activities. The shared resource management unit overrides a stream of access denials (e.g., NACKs) associated with an access problem. The memory management system and method facilitate access to memory while controlling translation between virtual and physical memory “spaces”. In one embodiment the memory management system includes a translation lookaside buffer and a fill component. The translation lookaside buffer tracks information associating a virtual memory space with a physical memory space. The fill component tracks the status of an access request progress from a plurality of engines independently and faults that occur in attempting to access a memory space.Type: GrantFiled: November 1, 2006Date of Patent: August 6, 2013Assignee: Nvidia CorporationInventors: David B. Glasco, John S. Montrym, Lingfeng Yuan, Robert C. Keller
-
Patent number: 8504795Abstract: Provided are a method, system, and program for utilizing a virtualized data structure table such as an address translation and protection table (TPT), for example, in an I/O device. The virtualized data structure table has virtually contiguous data structures but not necessarily physically contiguous data structures in system memory. The data structure table may be accessed in a virtually contiguous manner. In the illustrated embodiment, the table is subdivided at a first hierarchal level into a plurality of virtually contiguous units or segments. Each unit or segment is in turn subdivided at a second hierarchal level into a plurality of virtually contiguous subunits, subsegments, pages or blocks. Each page or block is in turn subdivided at a third hierarchal level into a plurality of physically contiguous table entries.Type: GrantFiled: June 30, 2004Date of Patent: August 6, 2013Assignee: Intel CorporationInventors: Hemal V. Shah, Ali S. Oztaskin
-
Patent number: 8499114Abstract: Various embodiments disclosed herein including systems and methods for improving allocation of computing resources in a virtual machine (VM) environment. Embodiments maintain data relating to how VM image data is stored in storage devices and loaded into volatile memory such as random access memory (RAM). The data is then used to identify common content in the volatile memory that can be shared across VM instances. In some embodiments, multiple VM instances can share at least a portion of a single common VM image loaded into a shared volatile memory.Type: GrantFiled: September 30, 2010Date of Patent: July 30, 2013Assignee: Amazon Technologies, Inc.Inventor: Pradeep Vincent
-
Patent number: 8499117Abstract: A method for writing and reading data in memory cells, comprises the steps of: defining a virtual memory, defining write commands and read commands of data (DT) in the virtual memory, providing a first nonvolatile physical memory zone (A1), providing a second nonvolatile physical memory zone (A2), and, in response to a write command of an initial data, searching for a first erased location in the first memory zone, writing the initial data (DT1a) in the first location (PB1(DPP0)), and writing, in the metadata (DSC0) an information (DS(PB1)) allowing the first location to be found and an information (LPA, DS(PB1)) forming a link between the first location and the location of the data in the virtual memory.Type: GrantFiled: September 21, 2010Date of Patent: July 30, 2013Assignee: STMicroelectronics (Rousset) SASInventor: Hubert Rousseau
-
Publication number: 20130191609Abstract: A device includes a host including a main memory, and semiconductor memory including a nonvolatile semiconductor memory, memory unit, and controller. The nonvolatile semiconductor memory stores first address information. The memory unit stores second address information as part of the first address information. The controller accesses the nonvolatile semiconductor memory based on the second address information. Third address information is stored in the main memory, and is part or all of the first address information. The controller uses the third address information when accessing the nonvolatile semiconductor memory if address information to be referred is not stored in the second address information.Type: ApplicationFiled: July 30, 2012Publication date: July 25, 2013Inventors: Atsushi KUNIMATSU, Kenichi MAEDA
-
Patent number: 8495282Abstract: Reliable storage for database management systems (DBMS) running on memory devices such as NAND type flash memory utilizes minimum I/O overhead and provides maximum data durability. A virtual page map is utilized between the flash memory and a page access component to record changes to the DBMS pages and prevent overwriting or data loss. There is no need for journaling and logging, and performance is increased by reducing the write and erase counts on the flash memory. The logical page numbers of the DBMS are mapped to physical page numbers in the page map, such that the virtual page map allocates an available page from the physical pages when changes to a page occur, and the updated information is stored in the allocated page. The allocated page number is mapped to the logical page number of the original page, thus maintaining a modified page representation while preventing physical in-place updates.Type: GrantFiled: November 12, 2010Date of Patent: July 23, 2013Assignee: Oracle International CorporationInventors: SangCheol Lee, BongSoo Ko, HyungGook Yoo, SongHee Kang
-
Patent number: 8495252Abstract: A method, system and computer program product are provided for implementing PCI-Express memory domains for single root virtualized devices. A PCI host bridge (PHB) includes a memory mapped IO (MMIO) domain descriptor (MDD) and an MMIO Domain Table (MDT) are used to associate MMIO domains with PCI memory VF BAR spaces. One MDD is provided for each unique VF BAR space size per bus segment connecting a single root IO virtualization (SRIOV) device to the PCI host bridge (PHB). The MDT used with the MDD includes having a number of entries limited to a predefined total number of SRIOV VFs to be configured. A VF BAR Stride, which may be further implemented as a VF BAR Stride Capability Structure, is provided to reduce the number of MDDs required to map SRIOV VF BAR spaces. A particular definition of the MDD is provided to reduce the number of MDDs required to at most one per SRIOV bus segment below a PHB.Type: GrantFiled: January 17, 2011Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Eric N. Lais, Gregory M. Nordstrom, Steven M. Thurber
-
Patent number: 8489810Abstract: In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mapping scheme of the storage device.Type: GrantFiled: April 11, 2012Date of Patent: July 16, 2013Assignee: Microsoft CorporationInventors: Ruston Panabaker, Cenk Ergan, Michael R. Fortin
-
Patent number: 8489853Abstract: What is disclosed is a frame management function defined for a machine architecture of a computer system. In one embodiment, a frame management instruction is obtained which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.Type: GrantFiled: March 6, 2012Date of Patent: July 16, 2013Assignee: International Business Machines CorporationInventors: Dan F Greiner, Charles W Gainey, Jr., Lisa C Heller, Damian L Osisek, Timothy J Slegel, Gustav E Sittmann
-
Patent number: 8488631Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.Type: GrantFiled: September 9, 2011Date of Patent: July 16, 2013Assignee: Micron Technology, Inc.Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
-
Publication number: 20130173878Abstract: A data preservation function is provided which, in one embodiment, includes indicating by a map, usage of a particular map extent range by a relationship between a source extent range of storage locations on a source storage device containing data to be preserved in the source extent range, and a target extent range mapped to the map particular extent range. In another aspect, in response to receipt of a data preservation command, a data preservation operation is performed including determining whether a map indicates availability of a map extent range mapped to the identified target extent range. Upon determining that a particular map indicates availability of a map extent range mapped to the identified target extent range, a relationship between the identified source extent range and the identified target extent range is established. Other features and aspects may be realized, depending upon the particular application.Type: ApplicationFiled: February 22, 2013Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: International Business Machines Corporation
-
Patent number: 8478931Abstract: A buffer pool for a database application is maintained in a volatile main memory component. A control portion that corresponds to a block of application data residing on a non-volatile, asymmetric memory component and that includes a reference to a location of the block of application data on the non-volatile, asymmetric memory component is added to the buffer pool maintained in the volatile main memory component. The control portion from the buffer pool maintained in the volatile main memory component that corresponds to the block of application data is accessed and the location of the block of application data on the non-volatile, asymmetric memory component is identified. Based on identifying the location of the block of application data on the non-volatile, asymmetric memory component, the database application is enabled to access the block of application data directly from the non-volatile, asymmetric memory component.Type: GrantFiled: May 7, 2012Date of Patent: July 2, 2013Assignee: Virident Systems Inc.Inventor: Vijay Karamcheti
-
Patent number: 8479080Abstract: A method for data storage includes, in a memory that includes multiple memory blocks, specifying at a first time a first over-provisioning overhead, and storing data in the memory while retaining in the memory blocks memory areas, which do not hold valid data and whose aggregated size is at least commensurate with the specified first over-provisioning overhead. Portions of the data from one or more previously-programmed memory blocks containing one or more of the retained memory areas are compacted. At a second time subsequent to the first time, a second over-provisioning overhead, different from the first over-provisioning overhead, is specified, and data storage and data portion compaction is continued while complying with the second over-provisioning overhead.Type: GrantFiled: June 24, 2010Date of Patent: July 2, 2013Assignee: Apple Inc.Inventors: Ofir Shalvi, Naftali Sommer, Yoav Kasorla
-
Patent number: 8478949Abstract: A data accessing method, and a storage system and a controller using the same are provided. The data accessing method is suitable for a flash memory storage system having a data perturbation module. The data accessing method includes receiving a read command from a host and obtaining a logical block to be read and a page to be read from the read command. The data accessing method also includes determining whether a physical block in a data area corresponding to the logical block to be read is a new block and transmitting a predetermined data to the host when the physical block corresponding to the logical block to be read is a new block. Thereby, the host is prevented from reading garbled code from the flash memory storage system having the data perturbation module.Type: GrantFiled: March 13, 2012Date of Patent: July 2, 2013Assignee: Phison Electronics Corp.Inventors: Chien-Hua Chu, Chih-Kang Yeh
-
Patent number: 8477946Abstract: In a logically partitioned computer system, a partition manager maintains and controls master encryption keys for the different partitions. Preferably, processes executing within a partition have no direct access to real memory, addresses in the partition's memory space being mapped to real memory by the partition manager. The partition manager maintains master keys at real memory addresses inaccessible to processes executing in the partitions. Preferably, a special hardware register stores a pointer to the current key, and is read only by a hardware crypto-engine to encrypt/decrypt data. The crypto-engine returns the encrypted/decrypted data, but does not output the key itself or its location.Type: GrantFiled: February 27, 2008Date of Patent: July 2, 2013Assignee: International Business Machines CorporationInventors: Mark R. Funk, Jeffrey E. Remfert
-
Patent number: 8473713Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: building at least one local page address linking table containing a page address linking relationship between a plurality of physical page addresses and at least a logical page address, wherein the local page address linking table includes a first local page address linking table containing a first page address linking relationship of a plurality of first physical pages, and a second local page address linking table containing a second page address linking relationship of a plurality of second physical pages that are different from the first physical pages; building a global page address linking table according to the local page address linking table; and accessing the memory apparatus according to the global page address linking table.Type: GrantFiled: September 6, 2012Date of Patent: June 25, 2013Assignee: Silicon Motion Inc.Inventors: Tsai-Cheng Lin, Chun-Kun Lee
-
Patent number: 8473712Abstract: A method for managing a memory apparatus including at least one non-volatile (NV) memory element includes: providing at least one block of the memory apparatus with at least one local page address linking table within the memory apparatus, wherein the local page address linking table includes linking relationships between physical page addresses and logical page addresses of a plurality of pages; and building a global page address linking table of the memory apparatus according to the local page address linking table. More particularly, the step of providing the block with the local page address linking table further includes: building a temporary local page address linking table for the local page address linking table corresponding to programming/writing operations of the memory apparatus; and temporarily storing the temporary local page address linking table in a volatile memory of the memory apparatus, and updating the temporary local page address linking table when needed.Type: GrantFiled: September 6, 2012Date of Patent: June 25, 2013Assignee: Silicon Motion Inc.Inventors: Tsai-Cheng Lin, Chun-Kun Lee
-
Patent number: 8473671Abstract: A predetermined number of erasable blocks positioned at a start of a volume area in a semiconductor memory card are provided so as to include volume management information. A user area following the volume management information includes a plurality of clusters. A size of the partition control area of an area from a master boot record & partition table sector to a partition boot sector is determined so that the plurality of clusters in the user area are not arranged so as to straddle erasable block boundaries. Since cluster boundaries and erasable block boundaries in the user area are aligned, there is no need to perform wasteful processing in which two erasable blocks are erased to rewrite one cluster.Type: GrantFiled: April 3, 2012Date of Patent: June 25, 2013Assignee: Panasonic CorporationInventors: Takuji Maeda, Teruto Hirota
-
Patent number: 8473709Abstract: Allocation of virtual disk volumes of a size designated by the computer manager to a virtual computer and accessiblity from the virtual computer to the virtual disk voumes without requiring intervention by a hypervisor are to be achieved. In a computer, at least one virtual computer to be in execution on the computer, and a computer system in which the virtual computer has volumes for holding data, a virtualization mechanism has a virtual volume allocating unit and a virtual volume information supplying unit, and the virtual computer has a virtual volume driver for converting positional information on virtual volumes. Additionally, the virtualization mechanism holds the virtual volume information together with defining information for the virtual computer to which the virtual volumes have been allocated.Type: GrantFiled: September 14, 2011Date of Patent: June 25, 2013Inventors: Naoko Ikegaya, Tomoki Sekiguchi, Keisuke Hatasaki
-
Patent number: 8473698Abstract: A LUN is provided that can store multiple datasets (e.g., data and/or applications, such as virtual machines stored as virtual hard drives). The LUN is partitioned into multiple partitions. One or more datasets may be stored in each partition. As a result, multiple datasets can be accessed through a single LUN, rather than through a number of LUNs proportional to the number of datasets. Furthermore, the datasets stored in the LUN may be pivoted. A second LUN may be generated that is dedicated to storing a dataset of the multiple datasets stored in the first LUN. The dataset is copied to the second LUN, and the second LUN is exposed to a host computer to enable the host computer to interact with the dataset. Still further, the dataset may be pivoted from the second LUN back to a partition of the first LUN.Type: GrantFiled: November 17, 2011Date of Patent: June 25, 2013Assignee: Microsoft CorporationInventors: Chris Lionetti, Robert Pike
-
Patent number: 8468322Abstract: In a copying apparatus, a storage capacity of an HDD which is used in a unique file system can be changed. In a partition area for image data formatted by a general-purpose file system, an area for a virtual unique high speed file system is provided and a reservation file having a data structure which can be used by the unique file system is constructed. A unique high speed file system accesses such an area, thereby enabling functions of the unique high speed file system to be virtually used and enabling information management of the image data to be made.Type: GrantFiled: March 25, 2009Date of Patent: June 18, 2013Assignee: Canon Kabushiki KaishaInventor: Junichi Yamakawa
-
Patent number: 8468299Abstract: An apparatus for real-time performance management of a virtualized storage system operable in a network having managed physical storage and virtual storage presented by an in-band virtualization controller comprises: a monitoring component operable in communication with the network for acquiring performance data from the managed physical storage and the virtual storage; and a cache controller component responsive to the monitoring component for adjusting cache parameters for the virtual storage. The apparatus may further comprise a queue controller component responsive to the monitoring component for adjusting queue parameters for the managed physical storage. The monitoring component, the cache controller component and the queue controller component may be configured to operate periodically during operation of the virtualized storage system.Type: GrantFiled: April 29, 2008Date of Patent: June 18, 2013Assignee: International Business Machines CorporationInventors: Nicholas M. O'Rourke, Lee J. Sanders, William J. Scales, Barry D. Whyte
-
Patent number: 8463995Abstract: A storage system has multiple disk controller (DKC) units that are coupled to one another in accordance with a coupling mode that satisfies the following (a1) through (a3): (a1) One DKC inside one DKC unit and one DKC inside another DKC unit are coupled via a second type of coupling medium that differs from the internal bus of the DKC and has a longer maximum communication distance than a first type of coupling medium, which is the same type of coupling medium as the internal bus of the DKC; (a2) the one DKC unit virtualizes a logical volume of the other DKC unit and provides this virtualized logical volume to host(s) coupled to the one DKC unit; and (a3) the other DKC unit virtualizes a logical volume of the DKC unit and provides this virtualized logical volume to host(s) coupled to the other DKC unit.Type: GrantFiled: July 16, 2010Date of Patent: June 11, 2013Assignee: Hitachi, Ltd.Inventors: Yuko Matsui, Hiroshi Kawano, Shigeo Homma, Masayuki Yamamoto
-
Publication number: 20130141446Abstract: A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling request to a translation mechanism is sent when the page fault is detected. A fault handling response corresponding to the detected page fault from the translation mechanism is received. Confirmation that the detected page fault has been handled through performing page mapping based on the fault handling response is received.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip J. Rogers, Mark Leather
-
Determining A Desirable Number Of Segments For A Multi-Segment Single Error Correcting Coding Scheme
Publication number: 20130145119Abstract: A desirable number of segments for a multi-segment single error correcting (SEC) coding scheme is determined based on scrambling information for a memory. The desirable number of segments can be the minimum number of segments required to satisfy a masked write segmentation requirement and a multi-bit upset size requirement. In one aspect, the memory scrambling information can specify the different scrambling techniques employed by the memory (e.g., Input-Output (IO) cell scrambling, column scrambling, column twisting, strap distribution, etc.). Based on the scrambling information, a mapping between the logical structure and physical layout for the memory can be derived. The mapping can be used to determine the least number of segments needed to satisfy the masked write requirement and the multi-bit upset size requirement.Type: ApplicationFiled: December 2, 2011Publication date: June 6, 2013Applicant: Synopsys, Inc.Inventors: Hayk Grigoryan, Gurgen Harutyunyan, Samvel Shoukourian, Valery Vardanian, Yervant Zorian -
Patent number: 8458436Abstract: An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.Type: GrantFiled: January 30, 2012Date of Patent: June 4, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Kunimatsu, Hiroto Nakai, Hiroyuki Sakamoto, Kenichi Maeda
-
Patent number: 8458411Abstract: A distributed shared memory multiprocessor that includes a first processing element, a first memory which is a local memory of the first processing element, a second processing element connected to the first processing element via a bus, a second memory which is a local memory of the second processing element, a virtual shared memory region, where physical addresses of the first memory and the second memory are associated for one logical address in a logical address space of a shared memory having the first memory and the second memory, and an arbiter which suspends an access of the first processing element, if there is a write access request from the first processing element to the virtual shared memory region, according to a state of a write access request from the second processing element to the virtual shared memory region.Type: GrantFiled: August 25, 2009Date of Patent: June 4, 2013Assignee: Renesas Electronics CorporationInventors: Yukihiko Akaike, Hitoshi Suzuki
-
Patent number: 8458433Abstract: A method and apparatus creates and manages persistent memory (PM) in a multi-node computing system. A PM Manager in the service node creates and manages pools of nodes with various sizes of PM. A node manager uses the pools of nodes to load applications to the nodes according to the size of the available PM. The PM Manager can dynamically adjust the size of the PM according to the needs of the applications based on historical use or as determined by a system administrator. The PM Manager works with an operating system kernel on the nodes to provide persistent memory for application data and system metadata. The PM Manager uses the persistent memory to load applications to preserve data from one application to the next. Also, the data preserved in persistent memory may be system metadata such as file system data that will be available to subsequent applications.Type: GrantFiled: October 29, 2007Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Eric Lawrence Barsness, David L. Darrington, Patrick Joseph McCarthy, Amanda Peters, John Matthew Santosuosso
-
Patent number: 8458437Abstract: Method and system for supporting multiple byte order formats, separately or simultaneously, are provided and described. In one embodiment, a page attribute table (PAT), which is programmable, is utilized to indicate byte order format. In another embodiment, a memory type range register (MTRR), which is programmable, is utilized to indicate byte order format.Type: GrantFiled: March 2, 2012Date of Patent: June 4, 2013Inventor: H. Peter Anvin
-
Patent number: 8458435Abstract: Embodiments of the invention are directed to systems and methods for detecting sequential write threads in non-volatile storage media. The embodiments described herein detect write commands directed to a range of logical addresses corresponding to a write thread. Upon detection of a write command directed to a write thread, the write command is assigned a physical write address associated with the write thread. Identification of write threads can be implemented with a hardware component which performs comparison operations between the write command address range and the write thread address range.Type: GrantFiled: December 20, 2010Date of Patent: June 4, 2013Assignee: Western Digital Technologies, Inc.Inventors: Charles P. Rainey, III, Dominic S. Suryabudi, Ho-Fan Kang
-
Patent number: 8458430Abstract: The system utilizes a plurality of layers to provide a robust storage solution. One layer is the RAID engine that provides parity RAID protection, disk management and striping for the RAID sets. The second layer is called the virtualization layer and it separates the physical disks and storage capacity into virtual disks that mirror the drives that a target system requires. A third layer is a LUN (logical unit number) layer that is disposed between the virtual disks and the host. By using this approach, the system can be used to represent any number, size, or capacity of disks that a host system requires while using any configuration of physical RAID storage.Type: GrantFiled: April 22, 2008Date of Patent: June 4, 2013Assignee: Archion, Inc.Inventor: James A. Tucci
-
Patent number: 8458434Abstract: Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.Type: GrantFiled: July 27, 2010Date of Patent: June 4, 2013Assignee: Qualcomm Innovation Center, Inc.Inventors: Zachary A. Pfeffer, Larry A. Bassel
-
Patent number: 8452914Abstract: An electronic device with improved flash memory compatibility and a method corresponding thereto are disclosed. The electronic device has a NAND flash, a processing unit and a program memory. The program memory stores application software and codes of an operating system, to be retrieved and executed by the processing unit. The application software requests for NAND flash access in accordance with a specific page size. The operating system acts as an intermediary between the application software and the NAND flash and provides a device driver which allocates a number of physical pages of the NAND flash to each virtual page of the specific page size for responding to NAND flash access requests from the application software by referring to the virtual pages.Type: GrantFiled: August 3, 2011Date of Patent: May 28, 2013Assignee: HTC CorporationInventors: Jia-Ruei Wang, Ssu-Po Chin
-
Patent number: 8452941Abstract: This disclosure provides a method for assigning data in an information handling system including a plurality of physical storage resources comprising a first tier and a second tier which has a lower performance and cost relative to capacity than the first tier. A tier manager may be hosted on the information handling system and in electronic communication with the plurality physical storage resources. The tier manager may, for each page: determine a seek distance value, determine an operation rate, determine an operation size value, determine an elapsed time value, and calculate a relative randomness value using the seek distance value, operation rate, operation size value, and elapsed time value determined for each page. A classification module may assign a physical location for each page such that the relative randomness value for each page in the first tier is greater than in the second tier.Type: GrantFiled: September 23, 2009Date of Patent: May 28, 2013Assignee: Dell Products L.P.Inventors: William Price Dawkins, Stephen Gouze Luning
-
Patent number: 8452933Abstract: Data written in the primary logical volume of the first storage device are transmitted to the third storage device via the second storage device, the data being written in the same location as the primary logical volume within the secondary logical volume in the third storage device; when transmission of the data stops among the first to the third storage devices, the respective second storage device and the third storage device manage locations in the secondary logical volume where the data held thereby are to be written; and, when transmission of the data resumes among the first to the third storage devices, the locations in the secondary logical volume managed by the respective second and the third storage devices are aggregated, the data to be written in the respective aggregated location in the secondary logical volume being transmitted from the first storage device to the third storage device via the second storage device.Type: GrantFiled: September 20, 2012Date of Patent: May 28, 2013Assignee: Hitachi, Ltd.Inventors: Shintaro Inoue, Katsuhiro Okumoto
-
Patent number: 8447945Abstract: A storage apparatus maintains a performance even if an unused storage area is not released. The storage apparatus includes a plurality of types of storage media, each having different performances, and moves the unused storage area to the storage medium having a low performance.Type: GrantFiled: June 14, 2010Date of Patent: May 21, 2013Assignee: Hitachi, Ltd.Inventor: Norifumi Nishikawa
-
Patent number: 8447936Abstract: A method for managing software modules of at least two operating systems sharing physical resources of a computing environment, but running in different partitions separated by a virtualization boundary comprises accumulating module information in a virtualization subsystem that directs the creation and management of the partitions. The accumulated module information is used across the virtualization boundary to manage the use of the software modules. Also, a method for managing software modules comprises making at least two operating systems aware that they are being hosted in a virtualized computing environment.Type: GrantFiled: June 30, 2006Date of Patent: May 21, 2013Assignee: Microsoft CorporationInventors: Douglas A. Watkins, Idan Avraham
-
Patent number: 8447904Abstract: Roughly described, a data processing system comprises a memory addressable by a range of physical memory addresses; a plurality of non-privileged software domains each having a virtual memory address space; a privileged software domain; a memory management unit operable to perform virtual address translation of a virtual memory address into a physical memory address; and an I/O device supporting virtualised interfaces each associated with a respective non-privileged software domain, the I/O device comprising an operation management unit operable to perform virtual address translation in one or more of the virtual memory address spaces; wherein, for I/O operations requested by a virtualised interface, the I/O device invokes the operation management unit to perform virtual address translation for those I/O operations meeting first criteria and to invoke the memory management unit to perform virtual address translation for those I/O operations which do not meet the first criteria.Type: GrantFiled: December 14, 2009Date of Patent: May 21, 2013Assignee: Solarflare Communications, Inc.Inventor: David Riddoch
-
Patent number: 8443166Abstract: Systems and methods for tracking changes and performing backups to a storage device are provided. For virtual disks of a virtual machine, changes are tracked from outside the virtual machine in the kernel of a virtualization layer. The changes can be tracked in a lightweight fashion with a bitmap, with a finer granularity stored and tracked at intermittent intervals in persistent storage. Multiple backup applications can be allowed to accurately and efficiently backup a storage device. Each backup application can determine which block of the storage device has been updated since the last backup of a respective application. This change log is efficiently stored as a counter value for each block, where the counter is incremented when a backup is performed. The change log can be maintained with little impact on I/O by using a coarse bitmap to update the finer grained change log.Type: GrantFiled: June 23, 2009Date of Patent: May 14, 2013Assignee: VMware, Inc.Inventors: Christian Czezatke, Krishna Yadappanavar, Andrew Tucker
-
Patent number: 8443136Abstract: Methods and apparatuses for enhanced protection of data stored in a FLASH memory system involve a controller capable of using variable size page stripes in the memory system. The controller is configured to store data such that each page stripe comprises a plurality of data pages, with each data page in the page stripe being stored in a different FLASH memory chip. The controller is also configured to maintain one or more buffers containing information reflecting blocks of memory within the FLASH memory chips that have been erased and are available for information storage, and to dynamically determine the number of data pages to be included in a page stripe based on the information in the one or more buffers such that a first page stripe and a second page stripe can have different numbers of data pages.Type: GrantFiled: December 17, 2010Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Holloway H. Frost, James A. Fuxa, Charles J. Camp
-
Patent number: 8438360Abstract: A volume manager I/O method and system. The method includes determining a storage extent mapping of storage functionality of a plurality of storage devices and generating a logical disk extent based on the storage extent mapping. The logical disk extent is exported to a volume device component that is communicatively coupled to implement I/O for an application. An I/O request from the application is received via the volume device component. The I/O request is executed in accordance with the logical disk extent.Type: GrantFiled: February 26, 2010Date of Patent: May 7, 2013Assignee: Symantec CorporationInventor: Christopher Youngworth