Virtual Addressing Patents (Class 711/203)
  • Patent number: 8612672
    Abstract: A solid-state drive, a solid-state drive access unit allocation/data storage approach, and a solid-state drive access unit access/data retrieval approach are described that improve the efficiency with which data, that has been stored to the solid-state drive in association with a series of logical block addresses, can be retrieved from the solid-state drive. The described access unit allocation approach assures that data stored in the solid-state drive in association with a sequential series of logical block addresses is stored and maintained in solid-state drive access units, i.e., addressable units of solid-state drive memory that allow parallel read access to the data via parallel memory access I/O channels internal to the solid-state drive. In this manner, the time required to retrieve data associated with a sequential series of logical block addresses from corresponding access units within the solid-state drive is reduced.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 17, 2013
    Assignee: Marvell International Ltd.
    Inventors: Gwoyuh Hwu, Lau Nguyen
  • Patent number: 8607020
    Abstract: Hypervisor managed memory paging is provided in a data processing system having multiple logical partitions. The data processing system includes a shared memory pool defined within physical memory. The shared memory pool includes a volume of physical memory with dynamically adjustable sub-volumes or sets of physical pages associated with the multiple logical partitions. Each sub-volume or set is associated with a particular logical partition and includes mapped logical memory pages for that logical partition. A hypervisor memory manager interfaces the multiple logical partitions and the shared memory pool, and manages access to logical memory pages within the shared memory pool. The hypervisor memory manager further manages page-out and page-in of logical memory pages from the shared memory pool to one or more external paging devices. This page-out and page-in managing by the hypervisor memory manager is transparent to the multiple logical partitions.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: December 10, 2013
    Assignee: International Business Machines Corporation
    Inventors: Stuart Z. Jacobs, Andrew T. Koch, David A. Larson, Kyle A. Lucke, Wade B. Ouren, Kenneth C. Vossen
  • Patent number: 8607024
    Abstract: An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.
    Type: Grant
    Filed: December 1, 2010
    Date of Patent: December 10, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenta Yasufuku, Shigeaki Iwasa, Yasuhiko Kurosawa, Hiroo Hayashi, Seiji Maeda, Mitsuo Saito
  • Patent number: 8601230
    Abstract: A volume migration method for causing to carry out a migration from a first volume manager to a second volume, includes: by causing the first volume manager to carry out actual accesses, obtaining information of correspondence, by the first volume manager, between logical volume offsets and physical blocks on a physical medium; judging, based on the obtained information of the correspondence, whether or not an exceptional data layout is carried out; and when it is judged that the exceptional data layout is not carried out, updating only a header area on the physical medium for the second volume manager. Incidentally, the aforementioned obtaining is carried out by using a program module for blocking access by the first volume manager to the physical medium. Thus, when only the header area is updated after it is confirmed the exceptional data layout is not made, the high-speed volume migration becomes possible.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: December 3, 2013
    Assignee: Fujitsu Limited
    Inventors: Takeshi Miyamae, Yoshitake Shinkai
  • Patent number: 8601235
    Abstract: A shared memory management system and method are described. In one embodiment, a memory management system includes a memory management unit for concurrently managing memory access requests from a plurality of engines. The shared memory management system independently controls access to the context memory without interference from other engine activities. In one exemplary implementation, the memory management unit tracks an identifier for each of the plurality of engines making a memory access request. The memory management unit associates each of the plurality of engines with particular translation information respectively. This translation information is specified by a block bind operation. In one embodiment the translation information is stored in a portion of instance memory. A memory management unit can be non-blocking and can also permit a hit under miss.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: December 3, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, John S. Montrym, Lingfeng Yuan
  • Patent number: 8601233
    Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Richard A. Uhlig, Scott Dion Rodgers, Rajesh M. Sankaran, Camron B. Rust, Sebastian Schoenberg
  • Patent number: 8595461
    Abstract: A method for data storage includes representing logical volumes by respective sets of pointers to physical partitions in which data used by the logical volumes is stored. One or more of the logical volumes are defined as provisionally deleted. A subset of the provisionally-deleted logical volumes is selected such that each logical volume in the subset has one or more private physical partitions whose data is used exclusively by that logical volume. One or more of the private physical partitions of the logical volumes in the subset are released for reallocation to another logical volume.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Haim Helman, Shemer S. Schwarz, Kariel E. Sandler
  • Patent number: 8595465
    Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: November 26, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventor: Moshe Raz
  • Patent number: 8595349
    Abstract: Method or apparatus for passive process monitoring is described. One aspect of the invention relates to monitoring a process executing on a computer system. An operating system is instructed to report at least one event related to process termination. Termination of the process is detected in response to a reported instance of the at least one event by the operating system. A notification is provided to an agent in the computer system that the process has terminated.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: November 26, 2013
    Assignee: Symantec Corporation
    Inventors: Carlos Wong, Yuh-Yen Yen, Bhavin Thaker
  • Patent number: 8595463
    Abstract: A computing system and methods for memory management are presented. A memory or an I/O controller receives a write request where the data two be written is associated with an address. Hint information may be associated with the address and may relate to memory characteristics such as an historical, O/S direction, data priority, job priority, job importance, job category, memory type, I/O sender ID, latency, power, write cost, or read cost components. The memory controller may interrogate the hint information to determine where (e.g., what memory type or class) to store the associated data. Data is therefore efficiently stored within the system. The hint information may also be used to track post-write information and may be interrogated to determine if a data migration should occur and to which new memory type or class the data should be moved.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert B. Tremaine, Robert W. Wisniewski
  • Patent number: 8594080
    Abstract: In one aspect of the present description, a connection between a predetermined input port and a predetermined output port is created in a partition of a VSAN switch, in which the connection is a destination address independent physical layer connection conforming to the physical layer of a communication protocol. Another connection between a plurality of input ports and a plurality of output ports may be created in another partition of the VSAN switch, in which the connection is a multi-layer connection which includes a network layer connection conforming to the network layer of the communication protocol. Other features and aspects may be realized, depending upon the particular application.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Mark Sean Fleming, Hemanth Kalluri, Jeffry Lynn Larson
  • Patent number: 8589616
    Abstract: A management system is coupled to a storage system group including a scale-out storage system (a virtual storage system). The management system has storage management information, which includes information denoting, for each storage system, whether or not a storage system is a component of a virtual storage system. The management system, based on the storage management information, determines whether or not a first storage system is a component of a virtual storage system, and in a case where the result of this determination is affirmative, identifies, based on the storage management information, a second storage system, which is a storage system other than the virtual storage system that includes the first storage system, and allows a user to perform a specific operation only with respect to this second storage system.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: November 19, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kyoko Miwa, Junichi Hara, Masayasu Asano
  • Patent number: 8589637
    Abstract: For each original data segment, a distributed storage processing unit generates encoded slices designed to prevent the original data segment from being reconstructed using fewer than a threshold number of encoded slices. Multiple encoded slices are generated for each of two different data segments, and the slices associated with the first and second data segment are stored substantially concurrently in different storage sets employing different distributed storage units. Encoded slices for even and odd data segments can be stored in different storage sets, or longer sequences of data segments can be stored in alternating storage sets. Storage sets can also be determined by the vault generation of a particular data segment.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: November 19, 2013
    Assignee: Cleversafe, Inc.
    Inventors: John Quigley, Akshay Lal, Asimuddin Kazi
  • Publication number: 20130305010
    Abstract: In one embodiment, a method comprises receiving a plurality of data frames representing at least one virtually concatenated data stream, storing the plurality of data frames in a memory; and recording, for each of a plurality of data frames, a physical write address that indicates a position in the memory and a virtual write address that includes a multiframe indicator and a byte number indicator.
    Type: Application
    Filed: July 15, 2013
    Publication date: November 14, 2013
    Inventors: Jing Ling, Soowan Suh, Juan-Carlos Calderon
  • Patent number: 8583892
    Abstract: A file system layout apportions an underlying physical volume into one or more virtual volumes (vvols) of a storage system. The underlying physical volume is an aggregate comprising one or more groups of disks, such as RAID groups, of the storage system. The aggregate has its own physical volume block number (pvbn) space and maintains metadata, such as block allocation structures, within that pvbn space. Each vvol has its own virtual volume block number (vvbn) space and maintains metadata, such as block allocation structures, within that vvbn space. Notably, the block allocation structures of a vvol are sized to the vvol, and not to the underlying aggregate, to thereby allow operations that manage data served by the storage system (e.g., snapshot operations) to efficiently work over the vvols.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: November 12, 2013
    Assignee: NetApp, Inc.
    Inventors: John K. Edwards, Blake H. Lewis, Robert M. English, Eric Hamilton, Peter F. Corbett
  • Patent number: 8583879
    Abstract: A data storage device including a storing medium to shingle write and a controller to access the storing medium so that data is sequentially written on the storing medium using a mapping table based on Logical Block Address (LBA) included in a write command.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 12, 2013
    Assignee: Seagate Technology International
    Inventors: Se-wook Na, In Sik Ryu
  • Patent number: 8578106
    Abstract: A method for writing data to submission queues in a storage controller including receiving an input/output (I/O) request from a client application, where the client application is associated with a virtual port and where the virtual port is associated with a physical port. The method further includes determining a size of the I/O request, identifying a queue group based on the size of the I/O request and the virtual port, where the queue group includes submission queues and is associated with the virtual port. The method further includes identifying a submission queue, sending the I/O request to a storage controller over the physical port, where the queue group is located in memory operatively connected to the storage controller and where the storage controller is configured to place the I/O request in the submission queue.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 5, 2013
    Assignee: DSSD, Inc.
    Inventor: Michael W. Shapiro
  • Publication number: 20130290668
    Abstract: Methods and apparatuses for adjusting the size of a virtual band or virtual zone of a storage medium are provided. In one embodiment, an apparatus may comprise a data storage device including a data storage medium having a physical zone; and a processor configured to receive a virtual addressing adjustment command, and adjust a number of virtual addresses in a virtual band mapped to the physical zone based on the virtual addressing adjustment command. In another embodiment, a method may comprise providing a data storage device configured to implement virtual addresses associated with a virtual band mapped to a physical zone of a data storage medium of the data storage device, receiving at the data storage device a virtual addressing adjustment command, and adjusting a number of virtual addresses in a virtual band based on the virtual addressing adjustment command.
    Type: Application
    Filed: April 27, 2012
    Publication date: October 31, 2013
    Applicant: Seagate Technology LLC
    Inventor: Se Wook Na
  • Patent number: 8572350
    Abstract: A memory management and writing method for managing a memory module is provided. The memory module has a plurality of memory units and a plurality of data input/output buses corresponding to the memory units. The method includes configuring a plurality of logical units, dividing each of the logical units as a plurality of logical parts, and mapping the logical parts of each of the logical units to physical blocks of the memory units. The method also includes respectively establishing mapping tables corresponding to the data input/output buses, and only using one of the data input/output buses to write data from a host system into the corresponding memory unit according to the mapping table corresponding to the data input/output bus. Accordingly, the method can effectively increase the speed of writing data into the memory module.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: October 29, 2013
    Assignee: Phison Electronics Corp.
    Inventor: Chih-Kang Yeh
  • Patent number: 8572351
    Abstract: The memory device comprises a physical memory plane (PMP) comprising m first physical lines (RGP1i) extending along a first direction and n second physical lines (RGP2j) extending along a second direction, reception means for receiving a logical address (ADR) designating a first logical line (RG1i) and a second logical line (RG2j) of a matrix logical memory plane (PML), possessing 2p first logical lines extending along the first direction and 2q second logical lines extending along the second direction, in that m and n are each different from a power of two, m being a multiple of 2k, k being less than or equal to p, and the product of m and n being equal to the nearest integer above 2p+q, and in that it comprises means for addressing the physical memory plane (PMP) that are configured to address a first physical line and a part only of a second physical line on the basis of the content of the said logical address received and of the remainder of a Euclidean division of a part of the content of this logical ad
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: October 29, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Francois Tailliet
  • Patent number: 8566291
    Abstract: A method include forming an initial bitmap from the de-duplicated data on virtual volumes, sorting discrete blocks according to frequency of occurrence to form a revised bitmap to first include a plurality of most common discrete blocks, creating a physical volume map from the revised bitmap, reviewing, from the physical volume map, an initial virtual volume of the virtual volumes contained on a corresponding original physical volume, to determine whether moving the initial virtual volume to a different physical volume reduces the total number of data blocks in the physical volume map, deleting the initial virtual volume from its corresponding original physical volume and adding the initial virtual volume to the different original physical volume to create a revised physical volume map including revised physical volumes, and writing the revised physical volumes to the target set of physical media using the revised physical volume map.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: John J. Auvenshine, Erik Bartholomy, Andrew G. Hourselt, John T. Olson, Harley D. Puckett, III
  • Patent number: 8566502
    Abstract: In a computer system with a disk array that has physical storage devices arranged as logical storage units and is capable of carrying out hardware storage operations on a per logical storage unit basis, a switch is provided to offload storage operations from a file system to storage hardware. The switch translates primitives used for performing storage operations into commands executable by the physical storage devices so that the data moving portion of the storage operations can be offloaded from the file system to the storage devices.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: October 22, 2013
    Assignee: VMware, Inc.
    Inventor: Satyam B. Vaghani
  • Patent number: 8566557
    Abstract: A method and a system are disclosed for storing initial data from an image detecting device in a camera system initial storage medium and making the data accessible. The initial data is stored consecutively in blocks, where file specific pointers representing the starting address for each stored file and file sequence, and dynamic memory pointers that points out the next writable address, are managed and stored during real time writing of the data. The data is made accessible through a virtual representation of the data in a virtual file system with a format known by an external storage medium controller, the virtual representation being related to the file specific pointers.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: October 22, 2013
    Assignee: Ikonoskop AB
    Inventors: Göran Olsson, Leif Byström, Mats Mårdberg
  • Patent number: 8566511
    Abstract: A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: October 22, 2013
    Assignee: STEC, Inc.
    Inventors: Mohammadali Tootoonchian, Mark Moshayedi
  • Patent number: 8566522
    Abstract: Systems and methods for management of a cache are disclosed. In general, embodiments described herein store access counts in file system metadata associated with files in the cache. By encoding access counts in the file system metadata, file I/O operations are reduced. Preferably, the reference count is encoded in an access count timestamp in the file system metadata. The access counts can be decoded based on the difference between the access count time stamp and a base time value, with larger differences reflecting a larger access count. The cache can be aged by advancing the base time value, thereby causing the access count for a file to drop. The base time value can also be stored in file system metadata, thereby reducing file I/O operations when performing aging.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 22, 2013
    Assignee: Open Text S.A.
    Inventor: James Conrad Shea
  • Patent number: 8566509
    Abstract: A method and program product for processing data by a pipeline of a single hardware-implemented virtual multiple instance finite state machine (VMI FSM). An input token of multiple input tokens is selected to enter a pipeline of the VMI FSM. The input token includes a reference to an FSM instance. In one embodiment, the reference is an InfiniBand QP number. After being received at the pipeline, a current state and context of the FSM instance are fetched from an array based on the reference and inserted into a field of the input token. A new state of the FSM instance is determined and an output token is generated. The new state and the output token are based on the current state, context, a first input value, and an availability of a resource. The new state of the first FSM instance is written to the array.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Rolf K. Fritz, Andreas Muller, Thomas Schlipf, Daniel Thiele
  • Patent number: 8566559
    Abstract: During compilation, a table mapping relative virtual address of a memory-allocating instruction of a native language program to a user type of the instance is created. During execution of the program, a module injected into the process intercepts calls to memory allocating functions and records the virtual address of the instruction calling the memory allocating function and the virtual address of the instance created. When a snapshot of the process heap is requested, the user type of the corresponding compile time instruction is assigned to the created instance. User type and heap information can be used to compute sizes of memory allocations and to aggregate user type instance counts and sizes. Using the static debugging information, a reference graph that displays the nesting of objects in live instances can be computed and displayed.
    Type: Grant
    Filed: October 10, 2011
    Date of Patent: October 22, 2013
    Assignee: Microsoft Corporation
    Inventors: Christopher Schmich, Aaron R. Robinson
  • Publication number: 20130275715
    Abstract: An apparatus and method is described herein for providing structures to support software memory re-ordering within atomic sections of code. Upon a start or end of a critical section, speculative bits of a translation buffer are reset. When a speculative memory access causes an address translation of a virtual address to a physical address, the translation buffer is searched to determine if another entry (a different virtual address) includes the same physical address. And if another entry does include the same physical address, the speculative execution is failed to provide protection from invalid execution resulting from the memory re-ordering.
    Type: Application
    Filed: December 8, 2011
    Publication date: October 17, 2013
    Inventors: Paul Caprioli, Abhay S. Kanhere
  • Patent number: 8560791
    Abstract: Techniques for migrating persistent data between and across data stores are implemented using monitoring methods. The method includes classifying frequently updated blocks of persistent data to distinguish those blocks from less frequently updated blocks of persistent data. The less frequently updated blocks are copied from the source data store to the destination data store, such that persistent data is copied to the destination data store in the absence of the persistent data of the frequently updated blocks. The method further includes identifying a modified set of the less frequently updated blocks that are modified during the copying. The modified set of less frequently updated blocks is copied from the source data store to the destination data store, without copying the frequently updated blocks. It is then determined whether to copy the frequently updated blocks of persistent data from the source data store to the destination data store.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: October 15, 2013
    Assignee: VMware, Inc.
    Inventors: Ali Mashitizadeh, Min Cai, Emre Celebi
  • Patent number: 8560759
    Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, and a non-volatile semiconductor memory (NVSM). A read frequency of a first logical block address (LBA) is maintained, and when the read frequency of the first LBA exceeds a threshold and a corresponding PBA is assigned to a data sector of the disk, first data stored in the data sector is copied to a memory segment of the NVSM. When the read frequency of the first LBA exceeds a threshold and the PBA is assigned to a memory segment of the NVSM, first data stored in the memory segment is copied to a data sector of the disk. When a read command is received to read the first LBA, a decision is made to read the first data from one of the NVSM and the disk.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: October 15, 2013
    Assignee: Western Digital Technologies, Inc.
    Inventors: William B. Boyle, Curtis E. Stevens, Virgil V. Wilkins
  • Patent number: 8554988
    Abstract: A storage controller manages address conversion information denoting the correspondence relationship between a logical address and a physical address of storage area (for example, a physical block) inside a flash memory. The storage controller uses the above-mentioned address conversion information to specify a physical address corresponding to a logical address specified by an I/O request from a higher-level device, and sends an I/O command including I/O-destination information based on the specified physical address to a memory controller inside a flash memory module. The memory controller carries out the I/O with respect to a storage area inside a flash memory specified from the I/O-destination information of the I/O command from the storage controller.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: October 8, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Jun Kitahara
  • Patent number: 8549253
    Abstract: A system integrates an intelligent storage switch with a flexible virtualization system to enable the intelligent storage switch to provide efficient service of file and block protocol data access requests for information stored on the system. A storage operating system executing on a storage system coupled to the switch implements the virtualization system to provide a unified view of storage to clients by logically organizing the information as named files, directories and logical unit numbers. The virtualization system may be embodied as a file system having a write allocator configured to provide a flexible block numbering policy to the storage switch that addresses volume management capabilities, such as storage virtualization.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: October 1, 2013
    Assignee: NetApp, Inc.
    Inventors: Vijayan Rajan, Brian Pawlowski, Jeffrey S. Kimmel, Gary Ross
  • Publication number: 20130249925
    Abstract: In one embodiment, the present invention includes a device that has a device processor and a device memory. The device can couple to a host with a host processor and host memory. Both of the memories can have page tables to map virtual addresses to physical addresses of the corresponding memory, and the two memories may appear to a user-level application as a single virtual memory space. Other embodiments are described and claimed.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 26, 2013
    Inventor: Boris Ginzburg
  • Publication number: 20130246891
    Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.
    Type: Application
    Filed: March 15, 2012
    Publication date: September 19, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Troy A. Manning, Troy D. Larsen, Martin L. Culley
  • Publication number: 20130246732
    Abstract: A method of programming memory cells for a rewritable non-volatile memory module is provided. The method includes: receiving a command which indicates performing an update operation to a logical page; and identifying valid logical access addresses and invalid logical access addresses in the logical page according to the command. The method also includes: selecting a physical page; setting flags corresponding to the valid logical access addresses in a valid state, setting flags corresponding to the invalid logical access in an invalid state; programming the flags and data belonging to the valid logical access addresses to the selected physical page based on the update operation; and mapping the selected physical page to the logical page. Accordingly, the method can effectively increase the speed of programming the memory cells.
    Type: Application
    Filed: June 21, 2012
    Publication date: September 19, 2013
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Kian-Fui Seng, Ming-Hui Tseng, Ching-Hsien Wang
  • Patent number: 8539137
    Abstract: A method, system and computer program product for storing data of a Virtual Execution Environment (VEE), such as a Virtual Private Server (VPS) or a Virtual Machine, including starting an operating system running a computing system; starting a Virtual Machine Monitor under control of the operating system, wherein the VMM virtualizes the computing system and has privileges as high as the operating system; creating isolated Virtual Machines (VMs), running on the computing system simultaneously, wherein each VM executes its own OS kernel and each VM runs under the control of the VMM; starting a storage device driver and a file system driver in the operating system; mounting a virtual disk drive; starting VM-specific file system drivers in the VM, the VM specific file system driver together with the common storage device drivers support virtual disk drives, the virtual disk drive is represented on the storage device as a disk image, the disk image data are stored on the storage device as at least one file that in
    Type: Grant
    Filed: June 4, 2007
    Date of Patent: September 17, 2013
    Assignee: Parallels IP Holdings GmbH
    Inventors: Stanislav S. Protassov, Alexander G. Tormasov, Serguei M. Beloussov
  • Patent number: 8539193
    Abstract: A storage system and method is provided including physical storage devices controlled by storage control devices constituting a storage control layer operatively coupled to the physical storage devices and hosts. The storage control layer includes a first virtual layer interfacing with the hosts, operable to represent a logical address space available to said hosts and characterized by an Internal Virtual Address Space (IVAS); a second virtual layer characterized by a Physical Virtual Address Space (PVAS), interfacing with the physical storage devices, and operable to represent an available storage space; and an allocation module operatively coupled to the first and second virtual layers and providing mapping between IVAP and PVAS. Each address in PVAS is configured to have a corresponding address in IVAS. The allocation module facilitates management of IVAS and PVAS, enabling separation of a process of deleting certain logical object into processes performing changes in IVAS and PVAS, respectively.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: September 17, 2013
    Assignee: Infinidat Ltd.
    Inventors: Yechiel Yochai, Leo Corry, Haim Kopylovitz, Ido Ben-Tsion
  • Patent number: 8539194
    Abstract: A controller in a storage system receives a capacity change command specifying a device, and changes, to a volume capacity value indicating a storage capacity following the capacity change command, a volume capacity value of a virtual volume associated with the device specified in management information, which includes the volume capacity value indicating a storage capacity of the virtual volume. As such, without increasing or decreasing the number of logical volumes associated with a device provided by a host device, the device can be changed in storage capacity.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: September 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Shintaro Inoue, Yutaka Takata
  • Patent number: 8539142
    Abstract: Logical-physical translation information comprises information denoting the corresponding relationships between multiple logical pages and multiple logical chunks forming a logical address space of a nonvolatile semiconductor storage medium, and information denoting the corresponding relationships between the multiple logical chunks and multiple physical storage areas. Each logical page is a logical storage area conforming to a logical address range. Each logical chunk is allocated to two or more logical pages of multiple logical pages. Two or more physical storage areas of multiple physical storage areas are allocated to each logical chunk. A controller adjusts the number of physical storage areas to be allocated to each logical chunk.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: September 17, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Junji Ogawa, Atsushi Kawamura
  • Patent number: 8532973
    Abstract: A system and method of testing, during development, the operation of a clustered storage server system and its associated storage operating system. The system includes at least one host computer having a host operating system, and at least one virtual computer having a simulated storage operating system, at least one simulated disk, a simulated NVRAM, and a simulated flashcard within a guest operating system hosted by the host operating system. The simulated storage operating system represents an actual storage operating system. Facilities of the simulated storage operating system including the simulated disk, the simulated NVRAM, and the simulated flashcard are mapped onto corresponding facilities of the host operating system via virtualization components of the virtual computer so that the simulated storage operating system operates substantially the same as the actual storage operating system on low cost host hardware platforms.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: September 10, 2013
    Assignee: NetApp, Inc.
    Inventors: Joseph CaraDonna, Brian McCarthy
  • Patent number: 8533424
    Abstract: A computing system comprises at least a processing module, a main memory, a memory controller, and a plurality of memory components. A method begins by the memory controller receiving a memory access request regarding a data segment. The method continues with the memory controller interpreting the memory access request to determine whether an error encoding dispersal function of the data segment is applicable. The method continues with the memory controller identifying at least a threshold number of memories based on the memory access request, wherein the threshold number of memories includes at least one of the main memory and/or one or more of the plurality of memory components, when the error encoding dispersal function is applicable. The method continues with the memory controller addressing the at least a threshold number of memories to facilitate the memory access request.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: September 10, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8533428
    Abstract: A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Steven M. Bennett, Andrew V. Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers
  • Patent number: 8527697
    Abstract: Methods and systems for load balancing read/write requests of a virtualized storage system. In one embodiment, a storage system includes a plurality of physical storage devices and a storage module operable within a communication network to present the plurality of physical storage devices as a virtual storage device to a plurality of network computing elements that are coupled to the communication network. The virtual storage device comprises a plurality of virtual storage volumes, wherein each virtual storage volume is communicatively coupled to the physical storage devices via the storage module. The storage module comprises maps that are used to route read/write requests from the network computing elements to the virtual storage volumes. Each map links read/write requests from at least one network computing element to a respective virtual storage volume within the virtual storage device.
    Type: Grant
    Filed: July 20, 2009
    Date of Patent: September 3, 2013
    Assignee: Netapp, Inc.
    Inventors: Wayland Jeong, Mukul Kotwani, Vladimir Popovski
  • Patent number: 8527673
    Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.
    Type: Grant
    Filed: May 21, 2008
    Date of Patent: September 3, 2013
    Assignee: VMware, Inc.
    Inventors: Mallik Mahalingam, Michael Nelson
  • Patent number: 8527716
    Abstract: Since only one golden image (GI) of a snapshot can exist and is shared among a plurality of storage apparatuses, there was a problem that migration or copy thereof deteriorates the capacity efficiency and increases the cost for managing consistency. The present invention solves the above-mentioned problem by either (1) a direct sharing method of generating a parent-child relationship of snapshots among different storage apparatuses at the time of creating differential LUs from the GI or (2) a virtual sharing method of creating virtual LUs of the GI in the respective storage apparatuses and creating differential LUs of the snapshots from the created virtual LUs, using a storage virtualization function among a plurality of storage apparatuses.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Toru Tanaka, Noriko Nakajima, Yasunori Kaneda
  • Patent number: 8527735
    Abstract: Provided are a data storage medium accessing method of accessing a data storage medium of a data storage device according to a virtual address (VA), the data storage device to access the data storage medium according to the VA, and a computer readable recording medium having recorded thereon a program to access the data storage medium accessing method.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: September 3, 2013
    Assignee: Seagate Technology International
    Inventors: In-sik Ryu, Moon-chol Park, Se-wook Na, Jae-sung Lee
  • Patent number: 8527702
    Abstract: Multiple storage area groups into which multiple storage areas provided by multiple storage devices are classified with reference to storage area attributes are managed. The multiple logical volumes to which, in accordance with a write request to at least one address included in multiple addresses in the logical volume, at least one storage area included in the multiple storage areas is allocated are provided. In accordance with the access condition of the at least one address in the logical volume, the data written to the at least one address by the write request is migrated from the at least one storage area included in one of the multiple storage area groups to at least one storage area in another storage area group included in the multiple storage area groups.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Ken Matsuda, Daisuke Orikasa, Yutaka Takata, Yoshiaki Eguchi, Ai Satoyama, Yoichi Mizuno
  • Patent number: 8527734
    Abstract: Administering registered virtual addresses in a hybrid computing environment that includes a host computer and an accelerator, the accelerator architecture optimized, with respect to the host computer architecture, for speed of execution of a particular class of computing functions, the host computer and the accelerator adapted to one another for data communications by a system level message passing module, where administering registered virtual addresses includes maintaining, by an operating system, a watch list of ranges of currently registered virtual addresses; upon a change in physical to virtual address mappings of a particular range of virtual addresses falling within the ranges included in the watch list, notifying the system level message passing module by the operating system of the change; and updating, by the system level message passing module, a cache of ranges of currently registered virtual addresses to reflect the change in physical to virtual address mappings.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: September 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Archer, Gary R. Ricard
  • Patent number: 8527732
    Abstract: A storage system in an embodiment of this invention comprises a virtual volume to which real storage areas are allocated depending on data amount to be stored therein and which stores a plurality of mainframe data managed in units of tracks, each of the plurality of mainframe data including control information and one or more records storing user data, and a controller The virtual volume is managed by a first real storage area storing the records in the plurality of mainframe data and a second real storage area storing the control information in the plurality of mainframe data. The controller determines not to allocate the first real storage area to the virtual volume in a case that user data in the records in the plurality of mainframe data are initial values. The control information in the plurality of mainframe data is stored in the second real storage area allocated to the virtual volume.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: September 3, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Kohei Tatara
  • Patent number: 8521985
    Abstract: There is provided a storage subsystem having a virtual volume and a page volume which has a page physical area allocated to the virtual volume. The storage subsystem divides an address space of the virtual volume into a plurality of pages, classifies each of the pages into one of a plurality of states including at least a first state and a second state, and further divide a page which is classified into the second state into a plurality of segments to managed the page classified into the second state. The first state is a state in which a page physical area is allocated to the page from the page volume, and the write data is stored in the page physical area. The second state is a state in which the predetermined pattern data and the segment are managed, in the memory, by correlating with each other.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: August 27, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Ohira, Shoji Kodama, Kenta Shiga, Yoshiaki Eguchi