Abstract: A method for unidirectional communication between tasks includes providing a first task having access to an amount of virtual memory, blocking a communication channel portion of said first task's virtual memory, such that the first task cannot access said portion, providing a second task, having access to an amount of virtual memory equivalent to the first task's virtual memory, wherein a communication channel portion of the second task's virtual memory corresponding to the blocked portion of the first task's virtual memory is marked as writable, transferring the communication channel memory of the second task to the first task, and unblocking the communication channel memory of the first task.

Abstract: An I/O request to store a file in a file-system is received. A determination is made whether the size of the file does not exceed a threshold size. Exceeding the threshold results in storing at least a portion of the file in a block of the file-system devoid of sub-blocks. A determination is made whether the size of the file does not exceed a size of unallocated space within a single block in the file-system. The single block includes a set of sub-blocks. Responsive to the size of the file not exceeding the threshold size and the size of unallocated space within the single block, the file is stored, at an address, in a first subset of the set of the sub-blocks of the single block. The address identifies the single block and a position of a sub-block in the subset.

Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.

Abstract: A memory system comprises a storage device and a host. The host classifies pages stored in the storage device into a plurality of data groups according to properties of the pages, and transmits setup information regarding the classified data groups to the storage device.

Abstract: Embodiments of copy equivalent protection using secure page flipping for software components within an execution environment are generally described herein. An embodiment includes the ability for a Virtual Machine Monitor (VMM), Operating System Monitor, or other underlying platform capability to restrict memory regions for access only by specifically authenticated, authorized and verified software components, even when part of an otherwise compromised operating system environment. In an embodiment, an embedded VM is allowed to directly manipulate page table mappings so that, even without running the VMM or obtaining VMXRoot privilege, the embedded VM can directly flip pages of memory into its direct/exclusive control and back. Other embodiments may be described and claimed.

Abstract: An information processing device includes a first storage unit configured to store a set value indicating a value corresponding to a set item to define a function and flag information indicating whether an initialization of the set value is required, a second storage unit configured to store a flag address identifying a storage location of the flag information in the first storage unit in association with the set item at least, and an initialization unit configured to identify the flag information for each set item by using the flag address corresponding to each set item, and if the identified flag address indicates that the initialization is required, initialize the set value corresponding to the set item.

Abstract: A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.

Abstract: A method of assigning virtual memory to physical memory in a data processing system allocates a set of contiguous physical memory pages for a new page mapping, instructs the memory controller to move the virtual memory pages according to the new page mapping, and then allows access to the virtual memory pages using the new page mapping while the memory controller is still copying the virtual memory pages to the set of physical memory pages. The memory controller can use a mapping table which temporarily stores entries of the old and new page addresses, and releases the entries as copying for each entry is completed. The translation lookaside buffer (TLB) entries in the processor cores are updated for the new page addresses prior to completion of copying of the memory pages by the memory controller. The invention can be extended to non-uniform memory array (NUMA) systems.

Abstract: What is disclosed is a set key and clear frame management function defined for a machine architecture of a computer system. In one embodiment, a machine instruction is obtained which identifies a first and second general register. Obtained from the first general register is a frame size field indicating whether a storage frame is one of a small block or a large block of data. Obtained from the second general register is an operand address of a storage frame upon which the instruction is to be performed. If the storage frame is a small block, the instruction is performed only on the small block. If the indicated storage frame is a large block of data, an operand address of an initial first block of data within the large block of data is obtained from the second general register. The frame management instruction is performed on all blocks starting from the initial first block.

Abstract: A data protection system includes terminals, and an encryption device that encrypts distribution data distributed to each terminal. Each terminal corresponds with one node on a lowest level of a tree structure having hierarchies. A data protection system excludes nodes on the lowest level, determines a plurality of combination patterns that include combinations of two or more of all four nodes that are reached one level below the node, decides an individual decryption key for each determined combination pattern, and decides an individual decryption key for each node on the lowest level. The data protection system prescribes nodes that are reached from the node on the lowest level and a terminal to the node on the highest level that is an invalid node.

Abstract: A storage device is provided for direct memory access. A controller of the storage device performs a mapping of a window of memory addresses to a logical block addressing (LBA) range of the storage device. Responsive to receiving from a host a write request specifying a write address within the window of memory addresses, the controller initializes a first memory butler in the storage device and associates the first memory buffer with a first address range within the window of memory addresses such that the write address of the request is within the first address range. The controller writes to the first memory buffer based on the write address. Responsive to the buffer being full, the controller persists contents of the first memory buffer to the storage device using logical block addressing based on the mapping.

Abstract: The present disclosure includes methods and devices for a memory system controller. In one or more embodiments, a memory system controller includes a host interface communicatively coupled to a system controller. The system controller has a number of memory interfaces, and is configured for controlling a plurality of intelligent storage nodes communicatively coupled to the number of memory interfaces. The system controller includes logic configured to map between physical and logical memory addresses, and logic configured to manage wear level across the plurality of intelligent storage nodes.

Abstract: For a virtual memory of a virtualized computer system in which a virtual page is mapped to a guest physical page which is backed by a machine page and in which a shadow page table entry directly maps the virtual page to the machine page, reverse mappings of guest physical pages are optimized by removing the reverse mappings of certain immutable guest physical pages. An immutable guest physical memory page is identified, and existing reverse mappings corresponding to the immutable guest physical page are removed. New reverse mappings corresponding to the identified immutable guest physical page are no longer added.

Abstract: A system and method for invalidating obsolete virtual/real address to physical address translations may employ translation lookaside buffers to cache translations. TLB entries may be invalidated in response to changes in the virtual memory space, and thus may need to be demapped. A non-cacheable unit (NCU) residing on a processor may be configured to receive and manage a global TLB demap request from a thread executing on a core residing on the processor. The NCU may send the request to local cores and/or to NCUs of external processors in a multiprocessor system using a hardware instruction to broadcast to all cores and/or processors or to multicast to designated cores and/or processors. The NCU may track completion of the demap operation across the cores and/or processors using one or more counters, and may send an acknowledgement to the initiator of the demap request when the global demap request has been satisfied.

Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.

Abstract: A method for managing virtual disk data storage may include: 1) identifying first and second virtual storage disks on a physical storage system; 2) identifying relocatable data in the first and second virtual storage disks; 3) comparing the relocatable data from the first and second virtual storage disks to identify one or more data objects in the first virtual storage disk that are identical to one or more data objects in the second virtual storage disk; 4) physically relocating the data objects from the first virtual storage disk to create a first chunk of data without changing a logical state of data in the first virtual storage disk; and 5) physically relocating the data objects from the second virtual storage disk to create a second chunk of data that is identical to the first chunk of data without changing a logical state of data in the second virtual storage disk.

Abstract: A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

Abstract: This invention is a system and a method for performing an I/O in a virtual data storage environment using a new architecture. The system of performing an I/O includes a mapping client integrated into a client of the storage server which in communication with the mapping server included in the storage server retrieves the mapping of the special data sharing storage objects and caches the shared objects in the data cache include in the client environment. The method of accessing the data sharing storage objects by one or more applications running on a client reduces the number of I/O on the storage objects by caching the storage objects in the data cache and bringing the knowledge of data sharing into the client environment.

Abstract: Multiple storage area groups into which multiple storage areas provided by multiple storage devices are classified with reference to storage area attributes are managed. The multiple logical volumes to which, in accordance with a write request to at least one address included in multiple addresses in the logical volume, at least one storage area included in the multiple storage areas is allocated are provided. In accordance with the access condition of the at least one address in the logical volume, the data written to the at least one address by the write request is migrated from the at least one storage area included in one of the multiple storage area groups to at least one storage area in another storage area group included in the multiple storage area groups.

Abstract: A system and method for mapping original Media Access Control (MAC) addresses to unique locally administered virtual MAC addresses in an Ethernet network. A first field of the address may include a domain for the address, and a second field may indicate that the address is a locally administered MAC address. A third field of the address may include an index indicating a number of virtual MAC addresses for each user. Fourth and fifth fields of the address may include a Network Element ID (NE ID) for uniquely identifying a given access node in a given domain, and a Port ID for uniquely identifying an end-user port at the given access node. The system may be implemented in an access node or in a network emulator, which generates unique locally administered MAC addresses for all of the nodes in the Ethernet network for performing emulations of the network.

Abstract: Provided is a method and apparatus for storing and restoring a state of a virtual machine on a virtual machine monitor. The method of storing a state of a second virtual machine in a predetermined storage device by a first virtual machine on a virtual machine monitor includes determining whether the state of the second virtual machine has changed, by comparing a previous state of the second virtual machine, which has already been stored in the storage device, with a current state of the second virtual machine and selectively storing the state of the second virtual machine based on a result of the determination, thereby minimizing time required to store or restore the state of the second virtual machine.

Abstract: An apparatus includes a processor and a volatile memory that is configured to be accessible in an active memory sharing configuration. The apparatus includes a machine-readable encoded with instructions executable by the processor. The instructions including first virtual machine instructions configured to access the volatile memory with a first virtual machine. The instructions including second virtual machine instructions configured to access the volatile memory with a second virtual machine. The instructions including virtual machine monitor instructions configured to page data out from a shared memory to a reserved memory section in the volatile memory responsive to the first virtual machine or the second virtual machine paging the data out from the shared memory or paging the data in to the shared memory. The shared memory is shared across the first virtual machine and the second virtual machine. The volatile memory includes the shared memory.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: A method for storing data and two sets of distributed mirrored data disposed as data stripes which permits data recovery without the necessity of parity calculations, is described. Redundant data are stored in groups of five physical hard drives which are logically segmented into stripe groups, each stripe group having three data stripe sets wherein one data stripe is protected by two distributed mirror stripes in accordance with an algorithm. The present method provides protection for all one- and two-disk failures and certain three-disk drive failures, for each physical five disk group, and retains a usable disk capacity of 33%.

Abstract: Methods (100), systems (300) and computer program products are disclosed for uninterrupted execution of an application program (110). The method (100) comprises: receiving a write operation call to a native file system from an application program (110) being executed on an operating system; and dynamically allocating (120, 122) free data blocks to the native file system from at least one other file system in a group of file systems until completion of execution of the application program (110) thereby completing the write operation call. The group of file systems is configured to allow sharing of free data blocks amongst the group of file systems.

Abstract: In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.

Abstract: Provided are methods and systems for multi-caching. The methods and systems provided can enhance network content delivery performance in terms of reduced response time and increased throughput, and can reduce communication overhead by decreasing the amount of data that have to be transmitted over the communication paths.

Abstract: Exemplary embodiments of the invention provide a solution to deploy a virtual hard disk (VHD) to virtual device with maximizing capacity efficiency and data access performance by making the allocation unit size of virtual device the same as that of the VHD. In one embodiment, a method of deploying a VHD file to a storage apparatus comprises checking a block size of the VHD file received by the storage apparatus based on a header of the VHD file; creating a virtual volume to provide a page size which is same size as the block size of the VHD file; and performing one of (A) copying contents of the VHD file to the created virtual volume by allocating one page of the created virtual volume for each block of the VHD file; or (B) formatting the created virtual volume with a virtual volume file system, and copying the VHD file to the formatted virtual volume.

Abstract: A multiprocessor system maintains cache coherence among processors in a coherent domain. Within the coherent domain, a first processor can receive a command to perform a cache maintenance operation. The first processor can determine whether the cache maintenance operation is a coherent operation. For coherent operations, the first processor sends a coherent request message for distribution to other processors in the coherent domain and can cancel execution of the cache maintenance operation pending receipt of intervention messages corresponding to the coherent request. The intervention messages can reflect a global ordering of coherence traffic in the multiprocessor system and can include instructions for maintaining a data cache and an instruction cache of the first processor. Cache maintenance operations that are determined to be non-coherent can be executed at the first processor without sending the coherent request.

Abstract: In one embodiment, a data storage device comprises a buffer, a buffer manager, and a buffer client. The buffer client is configured to receive data to be stored in the buffer, to compute a difference between a bank boundary address of the buffer and a starting buffer address for the data, to generate a first data burst having a length equal to the computed difference and including a first portion of the data, and to send the first data burst to the buffer manager, wherein the buffer manager is configured to write the first data burst to the buffer.

Abstract: A system comprising a plurality of virtual machines executed by a computing system; and an adapter; wherein the adapter includes a direct memory access (DMA) module for transferring control blocks to and from a computing system memory to an adapter memory, where the computing system memory has dedicated memory locations for each virtual machine to place the control blocks and the adapter memory has dedicated memory locations for storing the control blocks generated by each of the plurality of virtual machines.

Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.

Abstract: In one aspect, a method includes exposing a set of storage volumes to a host at a requested point in time, in a virtual access mode. The set of storage volumes are handled by distributed virtual consistency groups (CGs) having a background process wherein the distributed virtual CGs update the set of storage volumes to the requested point in time. The method also includes exposing a first service storage volume at a data protection appliance, determining if the virtual CGs have rolled back and using at least one of a central manager and a splitter to account for input/output requests (IOs) when a virtual CG has not rolled back.

Abstract: In an environment in which a processor operates a hypervisor and multiple guest partitions operating under the hypervisor's control, it is desirable to allow a guest partition access to a physical memory device without decreasing system performance. Accordingly, a conversion instruction for converting a logical address to a real address, i.e., an LTOR instruction, executable from a guest partition, is added to the processor. Upon the guest partition's execution of the conversion instruction with the logical address specified, the processor converts the logical address to an encrypted real address, and returns it to the guest partition. The guest partition is then able to pass the encrypted real address to an accelerator that converts the encrypted real address to a real address in order to access the memory device using the real address.

Abstract: A method of setting an address of a component that includes determining a characterization value associated with a consumable, calculating a number of address change operations based upon the characterization value, and setting a last address generated from the number of address change operations as the new address of the component, wherein the characterization value is determined based upon a usage of the consumable.

Abstract: A processing system has one or more processors that implement a plurality of virtual machines that are managed by a hypervisor. Each virtual machine provides a secure and isolated hardware-emulation environment for execution of one or more corresponding guest operating systems (OSs). Each guest OS, as well as the hypervisor itself, has an associated address space, identified with a corresponding “WorldID.” Further, each virtual machine and the hypervisor can manage multiple lower-level address spaces, identified with a corresponding “address space identifier” or “ASID”. The address translation logic of the processing system translates the WorldID and ASID of the current address space context of the processing system to corresponding WorldID and ASID search keys, which have fewer bits than the original identifiers and thus require less complex translation lookaside buffer (TLB) hit logic.

Abstract: The present invention provides a method and apparatus for data processing and virtualization. The method and apparatus are configured to receive communications, separate a command communication from a data communication, parallel process the command communication and the data communication, generate at least one virtual command based on the command communication, and generate virtual data according to the at least one virtual command. The apparatus can comprise a parallel virtualization subsystem configured to separate data communications from command communications and to parallel process the command communications and the data communications, to generate virtual commands and to generate virtual data according to a virtual command, and a physical volume driver coupled with the parallel virtualization subsystem, wherein the physical volume driver receives the virtual data and configures the virtual data.

Abstract: A setup module saves disk signatures identifying cluster disks for at least one source volume to a device distinct from the cluster disks. A copy module copies data with a volume-level restore from at least one snapshot volume to the at least one source volume, overwriting the disk signatures identifying the cluster disks so that the cluster disks cannot be accessed. A reset module rewrites the saved disk signatures to the cluster disks.

Abstract: Storage unit management methods and systems are provided. The storage unit comprises a plurality of physical blocks, wherein each has one of a plurality of block type definitions. First, a sub-write command is obtained, wherein the sub-write command requests to write data to at least one logical page of a logical block. It is determined whether a candidate block having a first block type definition exists in the storage unit, wherein the logical page of the logic block cannot map to the candidate block based on the first block type definition. If the candidate block exists, the block type definition of the candidate block is transformed from the first block type definition to a second block type definition. Data is written to a specific page of the candidate block, and a mapping relationship between the logical page of the logical block and the specific page of the candidate block is recorded.

Abstract: Techniques for migrating persistent data of virtual machines between and across data stores are optimized using special tracking data structures and monitoring methods. Special tracking data structures include an incremental change block tracking bitmap that indicate what blocks have been modified during a copy operation. The determination of whether any one block has been modified during the copy operation is based on whether or not the copy operation has progressed past that block. Another special tracking data structure is a Bloom filter, which provides a space-efficient data structure for keeping track of dirtied blocks. In addition, heat-based optimization techniques are applied so that blocks that are frequently updated are filtered and not transferred to the destination data store until the last iteration of the migration process.

Abstract: An address translation unit includes a translation lookaside buffer (TLB), a miss queue, and a control unit. The TLB may store a plurality of address translations. The miss queue may store received address translation requests that missed in the TLB. The miss queue includes a plurality of entries. At least some entries may each store a respective address translation request and a corresponding identifier. The corresponding identifier of a given entry identifies another entry in the miss queue that stores another respective address translation request having a process ordering constraint that is the same as a process ordering constraint of the respective address translation request in the given entry. Address translations having a same ordering constraint that are linked together via the identifier belong to the same virtual miss queue. The control unit may process the received address translation requests in an order dependent upon the identifier.

Abstract: Disclosed herein is a memory apparatus comprising: a nonvolatile memory configured to allow data to be written thereto and read therefrom in units of a cluster and to permit data to be deleted therefrom in units of a block made up of a plurality of sectors; a control circuit configured to control access operations to said nonvolatile memory; a management area; a user data area; and a cache area; said management area includes a logical/physical table, and the addresses of physical blocks in said cache area.

Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.

Abstract: A system and method for lun migration between data containers, such as aggregates of a storage system is provided. A new destination lun is created on a destination aggregate. A background copy process is then started that copies all data from a source lun on a source aggregate to the destination lun. The storage system continues to process client-originated data access requests directed to the source lun while the background copying continues. Once all the data of the source lun has been copied to the destination lun, processing of data access requests to the lun(s) is quiesced by the storage system. Lun maps of the storage system are then updated and processing of the client-originated data access requests is resumed with those requests now being directed to the destination lun.

Abstract: A dispersed storage (DS) unit for use within a dispersed storage network is capable of self-configuring using registry information provided to the DS unit. The registry information includes a slice name assignment indicating a range of slice names corresponding to a plurality of potential data slices of potential data objects to be stored in the DS unit. Based on the registry information, the DS unit allocates a portion of physical memory to store the potential data slices.

Abstract: The storage system includes a plurality of first disk devices, a plurality of second disk devices, in which a lifetime of the plurality of second disk devices is different from a lifetime of the plurality of first disk devices, and a controller coupled to the plurality of first disk devices and the plurality of second disk devices. The controller configures a first logical unit by the plurality of first disk devices and a second logical unit by the plurality of second disk devices, provides the first and the second logical units to a host computer, and manages a first remaining available time of the first logical unit and a second remaining available time of the second logical unit, on logical unit basis.

Abstract: A system includes multiple nodes coupled using a network of processor buses. The multiple nodes include a first processor node, including one or more processing cores and main memory, and a flash memory node coupled to the first processor node via a first processor bus of the network of processor buses. The flash memory node includes a flash memory including flash pages, a first memory including a cache partition for storing cached flash pages for the flash pages in the flash memory and a control partition for storing cache control data and contexts of requests to access the flash pages, and a logic module including a direct memory access (DMA) register and configured to receive a first request from the first processor node via the first processor bus to access the flash pages.

Abstract: Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.

Abstract: Lun clones are transferred from a primary server to a secondary server. The lun clones on the secondary server maintain the same data storage space saving relationship with backing luns of the lun clones as exists on the primary server. Incremental backups and restores of the lun clones between the primary and secondary servers involves transferring less than the total number of data blocks associated with the lun clone.

Abstract: Techniques for optimizing data movement in electronic storage devices are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for optimizing data movement in electronic storage devices comprising maintaining, on the electronic storage device, a data structure associating virtual memory addresses with physical memory addresses. Information can be provided regarding the data structure to a host which is in communication with the electronic storage device. Commands can be received from the host to modify the data structure on the electronic storage device, and the data structure can be modified in response to the received command.