Abstract: A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A debug unit is coupled to the bus, a protection unit is coupled with the bus and with the debug unit for protecting access on the bus. The protection unit is programmable to operate in a protecting mode in which the bus can be protected and in a debug mode in which a signal is sent to the debug unit, whereupon the debug unit generates a debug signal.

Abstract: A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace information indicating instruction execution flow in the processor core. The operation of the communication port as a trace port and as a parallel debug port is mutually exclusive. The parallel debug port provides for transmission of debug information between a debug host controller and the processor. The parallel debug port and the trace port physically share pins. Bus request and grant signals are provided between the parallel debug port and a debug host controller to ensure that collisions do not occur between use by the trace port and the debug host controller. A separate serial debug port is also provided which can be used to enable the parallel debug port.

Abstract: An operation controller, an operation unit and a memory are provided. The operation controller always receives a non-gated clock signal from a clock controller. When an operation initiating signal and a parameter signal indicating resources to be used in the operation unit are generated by a microcontroller, the operation controller asserts a request signal. In response to the request signal, respective gated clock signals are supplied from the clock controller to the operation unit and to the memory. The operation controller determines whether or not a status signal supplied from the operation unit satisfies a predetermined end condition. If the signal satisfies the end condition, the operation controller negates the request signal. As a result, the supply of the clock signals to the operation unit and to the memory is stopped.

Abstract: A programmable controller includes memory for storing a ladder logic control program having a plurality of ladder logic instruction rungs. Each rung begins with a start of rung (SOR) instruction. A processor is coupled to the memory for executing the ladder logic control program. User interrupts are disabled during execution of the rungs. During execution of the SOR instruction, a predetermined register, such as a MCR register, is read causing simultaneous enabling of user interrupts which overrides the previously disabled user interrupts to allow the processor to receive an interrupt request signal. The interrupt request signal is received before the read function of the predetermined register has completed.

Abstract: A method and device for identifying the manufacturer make and model type of a computer involves scanning the BIOS area of memory for personal computer (PC) configuration data. This scanned data is then used to generate a character-based computer identification string that is unique to a certain type of computer. This string is then compared to a set of known strings to determine the manufacturer make and model type of the polled computer. From scanning a number of personal computers and through user feedback, the process may build upon its knowledge base of personal computers.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A programmable address arithmetic unit and method for use on microprocessors, microcontrollers, and digital signal processors is described. The addressing arithmetic unit incorporates a programmable logic array or other programmable device coupled to address registers and the instruction stream, the address unit being responsive to commands in the processor's instruction set. A first set of instructions control the initialization and configuration of the address arithmetic unit logic. A second set of instructions reference operands using one or more addressing modes that calculate the operand's effective address using the logic programmed by said first set of instructions.

Abstract: A method for specifying a system comprising a plurality of interconnected functional modules each representing a respective abstract-state based machine, and a system so specified. A system is specified to include various interconnected functional modules at respective hierarchical levels. Each module represents an abstract state-based-machine. Each non-top level first module connects to a single second module at a next higher level by a transformer link from the second module for enabling a relevant change-of-state of the first module, by an observer link for a state enquiry signal from the second module, and by an event link for a solicited event signal to the second module. The first module retrosignals an internal autonomously executed step. Each non-bottom module enables one or more lower level modules to function as such first module. A top module can exchange signals with an environment.

Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.

Abstract: A micro-computer is arranged to execute instructions for data intensive applications, such as those used in mobile communications. One particular embodiment involves processing instructions into computational codes and data management codes. These two parts are coded separately and issued to two different program decoders in parallel. Computational codes control the computational units with register-to-register data movement only. Data management codes control data movement through the data management unit to prepare and transfer data for the computation. Multiple register files with active file swapping scheme may be used to simplify the computational operations without decreasing performance. The arrangement provides a significant reduction in power and is, therefore, especially advantageous for battery-operated communication applications and devices.

Abstract: It is an object of the present invention to provide a one-chip microcomputer which permits the access time for an external memory to be equal to that for an internal memory. The one-chip microcomputer 10 includes an internal ROM 11, control circuit 12, output terminals 13, input terminals 14, control circuit 15, selector 16, instruction register 17, delay circuit 18, and fetch control signal select gate 19. For selection of the external ROM 30, a control arrangement 20 and a delay circuit 18 are employed in one embodiment to adjust the time at which ROM data is fetched by the instruction register 17, based on the delay time for accessing the external ROM 30.

Abstract: A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed for instruction execution. And, the control of the coded division is executed by noting the code bits.

Abstract: A single chip application specific integrated circuit (ASIC) which provides a flexible, modular interface between a subsystem and a standard system bus. The ASIC includes a microcontroller/microprocessor, a serial interface for connection to the bus, and a variety of communications interface devices available for coupling to the subsystem. A three-bus architecture, utilizing arbitration, provides connectivity within the ASIC and between the ASIC and the subsystem. The communication interface devices include UART (serial), parallel, analog, and external device interface utilizing bus connections paired with device select signals. A low power (sleep) mode is provided as is a processor disable option.

Abstract: A programmable, special-purpose, pipeline processing system for processing dynamic programming algorithms. The pipeline processing system includes a plurality of accelerator chips coupled in series. The first and last accelerator chips are coupled to interface logic. Each of the accelerator chips includes an instruction processor; a plurality of pipeline processor segments coupled in series. Each of the pipeline processor segments includes a plurality of pipeline processors coupled in series. Each of the pipeline processors has an output and has as one input an output from a preceding pipeline processor and, as a set of second inputs, a corresponding set of outputs from the instruction processor. Also provided is a result processor having an output, and having as one input, an output from a prior result processor, and, as a second input, the output from one of the plurality of pipeline processors.

Abstract: A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are contained. A fetch unit (26) includes a branch target buffer (56) and a plurality of pattern history tables (53). Select logic (80) receives signals indicating, for each branching instruction, the type of program containing the instruction, and selects one of the pattern history tables (53) for use in generating a prediction code in response to a portion of a branch history field (BH) in an entry (63) of the branch target buffer (56) corresponding to the instruction address. Disclosed examples of the signals used in selecting the pattern history table (53) include an indication (U/S) of the privilege level (e.g., user-level or supervisor-level) of the instruction.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data. An external program address bus (RA) allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus (D). A bus interchange module (BIM) allows transfer between the separate internal program and data busses (P-Bus and D-Bus) in special circumstances. The internal busses are 16-bit, while the ALU and accumulator (Acc) are 32-bit. A multiplier circuit (M) produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter (S) with sign extension.

Abstract: A system and method for the streamlined execution of complex or repeating instructions. The method comprises creating a specialized instruction unit for executing a group of operations and then executing the group as they appear in an instruction stream. The system includes a programmable specialized instruction unit for executing the group of instructions as they appear in an instruction stream. The method comprises receiving a plurality of instructions, examining the plurality of instructions, identifying a subset of the plurality of instructions, creating a specialized instruction unit which is operable to execute the subset, and executing the subset in the special instruction unit upon an occurrence of the subset. Examining the plurality of instructions may occur at such times as compiling a computer program, performing an initialization procedure, or fetching or decoding instructions before execution.

Abstract: An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-processor node, a simultaneous buffering system is provided that allows all of the processors of the multi-processor node to operate at peak performance. A memory is shared among the nodes, with a portion of the memory resident at each of the multi-processor nodes. Each of the multi-processor nodes includes a number of elements for maintaining memory coherency, including a victim cache, a directory and a transaction tracking table. The victim cache allows for selective updates of victim data destined for memory stored at a remote multi-processing node, thereby improving the overall performance of memory.

Abstract: A multi-chip module and a chip set that comprises a plurality of the multi-chip modules. The multi-chip module includes a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs. A plurality of pins are secured in a single row along the periphery of the substrate and are connected to the inputs and outputs. The pins include a set of 91 signal pins, two ground pins, and a power pin, the signal pins having a configuration complying in number and signal type with the IEEE-P996 Requirements to define an ISA bus. The multi-chip module includes a rectangular housing wherein the pins, in the form of gull wing pins, extend laterally from a peripherally extending wall. The ISA bus pins extend along one side and partially along adjacent sides of the rectangular module.

Abstract: Disclosed herein is a microcomputer of the present invention.

Abstract: A computer processor includes a multiplexer having a first input, a second input, a third input, and an output. The processor further includes a scheduler coupled to the multiplexer first input, an execution unit coupled to the multiplexer output, and a replay system that has an input coupled to the multiplexer output. The replay system includes a first checker coupled to the replay system input and the second multiplexer input, and a second checker coupled to the first checker and the third multiplexer input.

Abstract: A method and an apparatus for data processing between multiple execution units using local and global register bypasses is disclosed. In one embodiment, the device contains a register file, at least two bypass circuits, a plurality of execution units, and a control circuit. Each bypass circuit connects to at least one execution unit. The control circuit, which is coupled to the execution units, limits no more than one clock delay per each execution clock cycle. The control circuit further designates delay clock cycles for handling delays.

Abstract: A PC card includes a plurality of functions and a plurality of CISs each for a single function or a combination of functions among the plurality of functions. A selection-signal input device inputs the CIS signal corresponding to the function to be used. A selection-signal determination section determines the designated CIS. According to the determination result, a CIS-switching setting section sets the designated CIS as the CIS to be read by a personal computer. A function-power-source switching control section supplies a power voltage only to the function corresponding to the designated CIS. An interface-bus-switching control section connects an interface bus for the function corresponding to the designated CIS to an interface bus connected to the main control section of the PC card.

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: A process and apparatus for quantum acceleration of a conventional computer by coupling a few quantum devices to the conventional computer. Initially, a first, second, and third maximally entangled qubit are prepared in a Greenberger-Horne-Zeilinger state. A fourth qubit is prepared in a perfect superposition of states which is unentangled from the three qubits. The second qubit is then measured and its measured value is input to the conventional computer. The conventional computer operates on this measured input value and performs an inverse oracle function. The second qubit is modified according to the output from the conventional computer. This modified qubit is used as one of two control inputs for controlling a quantum gate. The other control input is the fourth qubit. The quantum gate phase inverts the third qubit according to the two control inputs. A measurement of the complement of the first qubit is taken in order to produce the necessary quantum interference of the third qubit.

Abstract: A data processing apparatus (71) includes a data processor bus (103), the rotation register (208) and a register selection circuit. The rotation register (208) is embodied by a plurality of data registers (200) each having a plurality of equal bit groups. The number of bits within each bit group of each data register preferably equals the number N of data registers. The register selection circuit permits normal register reads and writes via the data processor bus. The register selection circuit permits special rotational data accesses. In a rotation read mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for read access. In a rotation write mode the register selection circuit selects noncontiguous bits from a predetermined position within each sections for each of the data registers for write access. The data registers (200) are connected together in a loop (208).

Abstract: Systems are provided for saving register data in a pipelined data processing system, and for restoring the data to the appropriate register in the event of an exception condition. One embodiment concerns a latch feedback assembly, such as a SRL, which includes multiple series-connected latches having a feedback connection between last and first latches. The latches are clocked to temporarily reserve a delayed backup copy of data from the first latch on the last latch. Upon detection of an exception, the backup copy is first preserved by disabling writes to the last latch; then the backup copy is copied to the first latch to restore the first latch to its state prior to occurrence of the exception. Another embodiment involves a register file save/restore mechanism, in which an additional bank of registers, called a "backup register", is coupled to a register file. When data is stored in an address of the register file, the address and its data content are also stored in the backup register.

Abstract: A VLIW microprocessor capable of executing two or more instructions having data dependency in a single cycle. The microprocessor includes an instruction fetch and decode unit, a register file, and a plurality of execution units communicating with the instruction fetch and decode unit and with the register file. At least two of the execution units are connected such that the output of a first one of the two execution units is connected to the input of a second one of the two execution units, such that the output of the first execution unit is available as an input to the second execution unit during said single cycle, and such that both execution units can execute in said single cycle. In an exemplary embodiment, the first execution unit is a shift left unit, and the second execution unit is a shift right unit. With this embodiment, a complete extract operation can be performed in a single cycle.

Abstract: An 8051 instruction set compatible microcontroller utilizing four or less clock cycles per machine cycle. The microcontroller is designed utilizing standard hardware design language techniques (HDL) and standardized cells. The microcontroller uses both a standard 8051 style special function register and a duplicate register to perform instructions requiring indirect memory accessing.

Abstract: A double cache snoop mechanism in uniprocessor computer systems having a cache and coherent I/O and multiprocessor computer systems reduces the number of cycles that a processor is stalled during a coherency check. The snoop mechanism splits each coherency check, such that a read-only check is first sent to the cache subsystem., and a read-write check is sent thereafter only if there is a cache hit during the read-only check, and there is the need to modify the cache. Average processor pipeline stall time is reduced even though a cache hit results in an additional coherency check because most coherency checks do not result in a cache hit.

Abstract: A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating instruction is translated into first and second instructions. The subsequent instruction is translated into at least a third instruction. The first instruction, when executed, generates a result and intermediate flag generation data. The second instruction, when executed, generates a plurality of flags. The first instruction is scheduled to execute before the second and third instructions. The second instruction is scheduled to execute before the third instruction if the third instruction has a data dependency on the second instruction, otherwise the third instruction may be scheduled to execute before the second instruction.

Abstract: A microprocessor on-board RAM provides both the usual random access by addressing and a subset of memory cells with their contents continually available on a secondary bus paralleling the data bus. This secondary bus may be used for register indirect addressing without a separate register read when the RAM subset includes the registers for register indirect addressing. The processor also has a two stage output driver for limiting maximum output current and feedback-controlled clock period partitioning.

Abstract: A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an active state. When either the first or second processor encounter a cache miss that has to be serviced by off-chip cache the processor requiring service is placed in nap state in which instruction fetching for that processor is disabled. When either the first or second processor encounter a cache miss that has to be serviced by main memory, the processor requiring services I placed in a sleep state by flushing all instructions from the processor in the sleep state and disabling instruction fetching for the processor in the sleep state.

Abstract: An information processor having a high performance as a whole is provided by improving the throughput of the processor and the semiconductor memory device. The information processor comprises a memory having a buffer for temporarily holding data and a processor having a memory interface part for controlling the memory to transfer data to the buffer before determining whether the data is to be written in the memory and to write the data in said memory after determining of writing. Data writing and reading to the semiconductor device is pipelined by justifying data exchange between reading and writing. Since the data transfer timings of reading from a memory and writing in the memory can be executed at the same time, the reading process and the writing process can be performed by pipeline-like process and the throughput can be improved.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: A processor architecture scheme which allows for encoding multiple addressing modes and which has multiple sources for generating a bank address value. The processor architecture scheme has a Central Processing Unit (CPU) for executing an instruction set. A data memory is coupled to the CPU. The data memory is used for storing and transferring data to and from the CPU. The data memory is divided into a plurality of banks wherein one of the plurality of banks is a dedicated bank for general and special purpose registers. A selection circuit is coupled to the data memory. The selection circuit is used for selecting one of the multiple sources for generating the bank address value. A bank select register is coupled to the selection circuit. The bank select register is used for supplying a bank address value for an instruction to be executed in a direct short addressing mode.

Abstract: At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which the information processing apparatus controls the peripheral apparatus through the network. The control information stored in the storage means is transferred through the network to the information processing apparatus, which receives it, the control data being generated by the information processing apparatus based upon the control information transferred to the information processing apparatus control means executes control process according to the data control received.

Abstract: A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model, and an interface for hardware blocks. The design allows software to control much of the configuration of the architecture while using hardware to provide efficient data flow, signal processing, and memory access. In devices with embedded DSPs, memory access is often the bottleneck and is tightly coupled to the efficiency of the design. The platform architecture involves a method that allows the sharing of the DSP memory with other custom hardware blocks or the micro-controller. The DSP can operate at full millions-of-instructions-per-second (MIPS) while another function is transferring data to and from memory. This allows for an efficient use of the memory and for a partitioning of the DSP tasks between software and hardware.

Abstract: A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain commands which are fully programmable at the user level. The processor itself is programmed at the register level to assure the fastest data rate possible (32 bit access) across the VMEbus. The processor driver is invisible to the user.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: According to the present invention, a method for changing a program including a plurality of instructions in a processor having a ROM for storing the program therein is provided. The method includes the steps of: replacing one of the plurality of instructions which are stored in the ROM with data having a predetermined value; and interpreting the data having the predetermined value as an instruction.

Abstract: A bus switch providing versatile data path routing between a first group of busses associated with a disk array controller and a second group of busses associated with the individual disk drives within the disk array. The bus switch comprises a plurality of bus multiplexers, equal in number to the number of drive busses. Each bus multiplexer includes a plurality of inputs, each input being connected to a corresponding one of the controller busses. The multiplexers are responsive to select and enable signals to connect selected controller busses to selected drive busses. The bus switch additionally includes a plurality of bus multiplexers for directing data from the drive busses to the controller busses. A parity generator comprising an exclusive-OR circuit is integrated with the bus switch. The output of the parity generator is also provided to each of the multiplexers and can be directed thereby to any of the controller or drive busses.

Abstract: A method and apparatus for In-System Programming which overcomes the above-described disadvantages. The method and apparatus of the ISP system interfaces with the two oscillator (instead of I/O) pins on the microcontroller. By interfacing with the two oscillator pins, the need for extra isolation circuitry to isolate other circuits from the ISP circuits is avoided in most circumstances, without incurring the expense of an expensive JTAG tester or extra dedicated pins. The amount of isolation circuitry necessary is reduced because the two oscillator pins are usually connected to passive components (registers, capacitors, or crystals) which cannot be damaged by the relatively high programming voltages and which do not produce signals that would interfere with the ISP programming signals.

Abstract: For the obtainment of a unique number identifier called a ticket indentifying a task or an event in a multi-node data processing system (SYS), a master node (Ny) for distributing the ticket in the system is designated, and it includes a ticket generator (TICKy:VALy, SESSy, COUNTy) whose address (TICK.sub.-- ID) is stored in a reference register (REF) of each node. When a node (Nx) requests a ticket, it reads the address (TICK.sub.-- ID) in this register and thus accesses the ticket generator of the master node (Ny). A backup or substitute node (Ns) can replace the master node (Ny) in case of a failure (TICK-MISS).

Abstract: This invention is a technique for summing plural sections of a single data word. The technique uses a repeated process forming larger and larger partial sums. Initially the single data word is rotated one section. The original single data word and the rotated single data word are masked with a mask having "1's" and "0's" in alternate sections. The mask blocks alternate sections so that adjacent sections of the original data word may be summed on a whole data word basis without any overflow disrupting the partial products. The two masked data words are then summed. This sum results in half as many partial sums as before. Each of these larger partial sums now occupies two original sections of the data word. The process can be repeated for these large partial sums. In the preferred embodiment this technique is used with an arithmetic logic unit (230) capable of forming mixed arithmetic and Boolean combinations of three inputs having a barrel rotator (235) driving one input.

Abstract: A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives.

Abstract: A parallel computer system which divides the entire space of facilities into a plurality of small divisions; assigns a plurality of processors thereof to the divisions, respectively, the lower stream processors receiving data on a boundary condition from the upper stream processor by communication to determine a condition for the continuity of the adjacent divisions, the processors carrying out parallel analytical operations for the analysis of the data on the corresponding divisions so as to meet the received boundary condition; and collects data obtained by the parallel analytical operations of the processors in a host computer to obtain analytical data on the large-scale facilities.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A system for real-time digital signal processing employs a single-chip microcomputer device having separate on-chip program ROM and data RAM, with separate address and data paths for program and data. An external program address bus allows off-chip program fetch in an expansion mode, with the opcode returned by an external data bus. A bus interchange module allows transfer between the separate internal program and data busses in special circumstances. The internal busses are 16-bit, while the ALU and accumulator are 32-bit. A multiplier circuit produces a single state 16.times.16 multiply function separate from the ALU, with 32-bit output to the ALU. One input to the ALU passes through a 0-to-15 bit shifter with sign extension.

Abstract: A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.