Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.

Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Abstract: A digital signal processor includes an instruction fetch unit for fetching and decoding instructions, a data cache, a memory, an execution unit, including a register file, for executing the instructions, and a load control unit for loading data from the data cache to the register file in response to instructions of a first instruction type and for loading data from the memory to the register file in response to instructions of a second instruction type. Instructions of the first instruction type may be microcontroller instructions, and instructions of the second instruction type may be digital signal processor instructions. The execution unit may include a microcontroller execution unit having a first number of pipeline stages for executing the microcontroller instructions and a digital signal processor execution unit having a second number of pipeline stages for executing the digital signal processor instructions.

Abstract: When converting a sequential execution source program into a parallel program to be executed by respective processors (nodes) of a distributed shared memory parallel computer, a compiler computer transforms the source program to increase a processing speed of the parallel program. First, a kernel loop having a longest sequential execution time is detected in the source program. Next, a data access pattern equal to that of the kernel loop is reproduced to generate a control code to control first touch data distribution. The first touch control code generated is inserted in the parallel program.

Abstract: A microprocessor integrated circuit including a processing unit disposed upon an integrated circuit substrate is disclosed herein. The processing unit is designed to operate in accordance with a predefined sequence of program instructions stored within an instruction register. A memory, capable of storing information provided by the processing unit and occupying a larger area of the integrated circuit substrate than the processing unit, is also provided within the microprocessor integrated circuit. The memory may be implemented using, for example dynamic or static random-access memory. A variable output frequency system clock, such as generated by a ring oscillator, is also disposed on the integrated circuit substrate.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices.

Abstract: A central processor-coprocessor assembly comprising an assembler software tool for extending the base central processor tasks into at least one coprocessor. What is important is that the assembler software tool does not need to be rebuilt when changes are made to the coprocessor elements. The invention allows assembly time extension of a base core language processing (CLP) programming model, without the need to rebuild the assembler tool itself. The assembler tool comprises a set of commands which enable the central processor to manipulate the coprocessor registers, and a coprocessor execute instruction, which initiates command processing on the coprocessor. The present invention simplifies the maintenance of the assembler tool through multiple hardware revisions by enabling hardware designers to update their coprocessor definition files to reflect new or modified coprocessors.

Abstract: An embedded processor system having a single-chip embedded microprocessor, with analog and digital electrical interfaces to external systems, that is suitable for implementation in various integrated circuit technology formats. A processor core uses pipelined execution of multiple independent or dependent concurrent threads, together with supervisory control for monitoring and controlling the processor thread state and access to other components. The pipeline enables simultaneous execution of multiple threads by selectively avoiding memory or peripheral access conflicts through the types of pipeline stages chosen and the use of dual and tri-port memory techniques. The single processor core executes one or multiple instruction streams on multiple data streams in various combinations under the control of single or multiple threads. The invention can also support a programmable clock mechanism, thread-level monitoring capability, and power management capability.

Abstract: A semiconductor integrated circuit with a IP test circuit having a IP test circuit, a IP6, a IP7, a COU 4, a SRAM 5. The IP test circuit has a IP test controller 21 including a register 21, a test sequencer 2, a selector 3, and a bus interface 11. Under the control of the IP test controller 1, a test program and test data in serial form are transferred from an external tester through a test data terminal 9 and then converted to the test program and the test data in parallel form. The converted test program and the test data are stored into the SRAM 5. The CPU 4 executes the test operation for the IP6 directly connected to a cpu bus 8. The test sequencer 7 executes the test operation for the IP7 that is not directly connected to the cpu bus 8. The test results are transferred to the external tester through the test data terminal.

Abstract: The present disclosure relates to a system and method for dynamically patching code. In one arrangement, the system and method pertain to intercepting program instructions, determining if a program instruction requires unavailable hardware functionality, and dynamically replacing the program instruction with a replacement instruction that does not require unavailable hardware functionality if it is determined that the program instruction requires unavailable hardware functionality.

Abstract: An improved microprocessor is provided having a program control unit for storing and then decoding instructions, a program address generation unit for generating addresses used to obtain instructions, an address register arithmetic unit for generating addresses for data, an arithmetic logic unit for performing operations on data, a shifter unit for shifting data in response to a predetermined instruction, a multiplier unit for performing multiplication of two input values; and a plurality of registers of which at least a portion are individually selectively associated with one or more of said units as a function of an instruction.

Abstract: A core logic chip set is provided in a computer system to provide a bridge between host and memory buses and an accelerated graphics port (“AGP”) bus adapted for operation of two AGP devices, or one AGP device and one peripheral component interconnect (“PCI”) device. A common AGP bus having provisions for the PCI and AGP interface signals is connected to the core logic chip set and the AGP and/or PCI device(s). The core logic chip set has an AGP/PCI arbiter having Request (“REQ”) and Grant (“GNT”) signal lines for each AGP and/or PCI device connected to the AGP bus. Another embodiment has a plurality of AGP buses for a plurality of AGP devices. This allows concurrent operation for AGP devices connected to different AGP buses. Two of the AGP buses may be combined to connect to one 64 bit PCI device.

Abstract: A distributed automation system comprising a programmable logic controller connected to programmable logic controllers equipped with a host unit and couplers communicating with the host unit through the back panel bus. One of the couplers is connected through a bus to associated equipment, wherein the coupler can communicate with the associated equipment through a server function using the TCP/IP protocol. The server coupler is provided with a mass memory containing (1) “PLC variables” type software objects that manage access to PLC variables, and (2) “manufacturer” type software objects that transform information from PLC variable objects to manufacturer-type information that can be used by the associated equipment.

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to top of stack including a push or pop.

Abstract: Access control to protected resources in a multiprocessor system is implemented without additional use of the processor bus. A bridge interconnects each processor with shared resources. The bridge has a semaphore corresponding to each protected resource indicating if the corresponding resource is available. The bridge halts a processor requesting access to any resource having a corresponding semaphore indicating the requested resource is not available.

Abstract: An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides the native instructions where each native instruction contains at least one register identifier. Flags are provided to each native instruction where each flag indicates whether a register identifier is valid. A bundler checks for dependency among the valid register identifiers in the native instructions.

Abstract: An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded freely over a bus system, the EALU being decoupled from the bus system over input and output registers. The output registers are connected to the input of the EALU to permit serial operations. A bus control unit is responsible for the connection to the bus, which it connects according to the bus register. The unit is designed so that distribution of data to multiple receivers (broadcasting) is possible. A synchronization circuit controls the data exchange between multiple cells over the bus system. The EALU, the synchronization circuit, the bus control unit, and registers are designed so that a cell can be reconfigured on site independently of the cells surrounding it.

Abstract: A processing device (10) provides general-purpose input/output pins (52) for use by software routines as needed. A data input register (54) has bits corresponding to each pin (52) for storing the value of the signal on the pin. A data output register (56) has bits corresponding to each pin for driving the signal on the pin (52) to a desired value. An output enable register (58) controls output buffers (62) coupled between the output register (56) and the pins (52). A plurality of mask registers (60) may be individually set to define a set a pins associated with the mask. Each of the data registers, the data input register (56), the data output register (58) and the output enable register (60) are accessed through a plurality of addresses, where the address specifies both the data register being accessed and an associated mask register (60). Logic (50) accesses the data registers in view of the state of the associated mask register (60).

Abstract: Improved processors and processing methods are disclosed for high-speed computerized comparison analysis of two or more linear symbol or character sequences, such as biological nucleic acid sequences, protein sequences, or other long linear arrays of characters. These improved processors and processing methods, which are suitable for use with recursive analytical techniques such as the Smith-Waterman algorithm, and the like, are optimized for minimum gate count and maximum clock cycle computing efficiency. This is done by interleaving multiple linear sequence comparison operations per processor, which optimizes use of the processor's resources. In use, a plurality of such processors are embedded in high-density integrated circuit chips, and run synchronously to efficiently analyze long sequences. Such processor designs and methods exceed the performance of currently available designs, and facilitate higher dimensional sequence comparison analysis between three or more linear sequences.

Abstract: A high speed programmable ER computational engine that is based on a micro-programmed control unit and a register intensive pipelined datapath that removes the need for having an instruction set interpreter includes a data path unit operably coupled to directly receive datapath control words from a control unit. The control unit includes memory and an address unit, where the memory stores the data path control words, which relate to a computational algorithm. The address unit receives input (e.g., begin an ER calculation) from an external source, where the input causes at least some of the data path control words to be retrieved from the memory. The data path unit includes a pair of register files, a plurality of floating point units, and data flow coupling. The pair of register files operate in a double buffering manner such that one of the register files is receiving parameters (e.g., data rate information of a connection) for subsequent computation while the other is used for a current computation.

Abstract: In an example embodiment, a data transaction access system for an embedded microprocessor coupled to a PCMCIA bus device comprises a local bus adapted to convey digital signals. Coupled to the local bus is a bus master. A host bus adapter couples to the local bus for enabling communication between the bus master and a PCMCIA device coupled to the host bus adapter via a PCMCIA bus. A wait register is coupled to the host bus adapter. The wait register is adapted to receive a delay input describing a latency period of the PCMCIA device, wherein the host bus adapter is configured to insert wait states into a data transaction from the bus master to the PCMCIA device when the delay input is less than a predetermined amount and wherein the host bus adapter is configured to retry the bus master when the delay input is greater than the predetermined amount.

Abstract: A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run legacy code written for the Z80 micoprocessor without requiring recompiling of code. An optional embodiment includes autonomous Multiply/Accumulator Engine (MAC) optimized to perform sum-of-products (SOP) operations with little controller overhead, making the invention capable of more effectively handling a number of processing tasks, particularly tasks related to digital signal processing (DSP).

Abstract: The data processing device maintains two stacks. The length of the basic unit of information is different for each stack. Pops and pushes cause a change in the stack pointer which differs dependent on which stack is used. Instructions refer to different locations on the stack as registers defined by an offset of a number of basic units relative to the top of stack. In an embodiment a reference to registers is normally interpreted as a reference to one of a set of registers (including the top of stack register) without push or pop, but a reference to one register is interpreted as a reference to, top of stack including a push or pop.

Abstract: A data processor which includes a first processor for executing a first instruction set and a second processor for executing a second instruction set different from the first instruction set. When the first processor executes a predetermined instruction of the first instruction set the second processor executes an instruction of the second instructions set. The first processor may be a reduced instruction set computer (RISC) type processor, the second processor may be a very long instruction word (VLIW) type processor, the first instruction set may be a RISC instruction set and the second instruction set may be a VLIW instruction set. The predetermined instruction of the RISC instruction set executed by the first processor may be a branch instruction causing a branch to a specific address space at which VLIW instructions are stored. Thereafter, the VLIW instructions at the specific address space are executed by the VLIW type processor.

Abstract: A non-traditional computing machine implements a parameterless computer language that operates without operands and without linear addressing of code or data. A code space having multiple dimensions contains programmed instructions, each having a unique position defined with respect to the code space dimensions. A data space having multiple dimensions contains data bits, each having a unique position defined with respect to the data space dimensions. A code pointer has a position and a direction within the code space. The code pointer position identifies a present instruction. A data pointer has a position and a direction within the data space. The data pointer position identifies a present data bit. The programmed instructions are selected from an instruction set that includes instructions for navigating the code pointer to select instructions and navigating the data pointer to select data bits. The computing machine operates to manipulate the data in the data space according the programmed instructions.

Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.

Abstract: A method and system of facilitating storage accesses within a multiprocessor system subsequent to a synchronization instruction by a local processor consists of determining if data for the storage accesses is cacheable and if there is a “hit” in a cache. If both conditions are met, the storage accesses return the data to the local processor. The storage accesses have an entry on an interrupt table which is used to discard the returned data if a snoop kills the line before the synchronization instruction completes. After the cache returns data, a return data bit is set in the interrupt table. A snoop killing the line sets a snooped bit in the interrupt table. Upon completion of the synchronization instruction, any entries in the interrupt table subsequent to the synchronization instruction that have the return data bit and snooped bit set are flushed.

Abstract: A method and apparatus for solving the output dependence problem in an explicit parallelism architecture microprocessor with consideration for implementation of the precise exception. In case of an output dependence hazard, the issue into bypass of a result of the earlier issued operation having an output hazard is cancelled. Latencies of short instructions are aligned by including additional stages on the way of writing the results into the register file in shorter executive units, which allows to save the issue order while writing the results into the register file. For long and unpredictable latencies of the instructions, writing of the result of the earlier issued operation having an output dependence hazard into the register file is cancelled after checking for no precise exception condition. All additional stages are connected to the bypass not to increase the result access time in case of this result use in the following operations.

Abstract: A system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. The system includes, among other things, a data sequencer for sequencing the input data stream and a counter. The sequencer includes a select input having a first number of selection input locations, a data input for receiving the digital data stream, and output for transmitting the output data stream. The counter includes the first number of selection outputs. A first logic element and a second logic element are coupled to a number of the selection inputs of the sequencer and a number of the selection outputs of the counter. The first and second logic elements control the data sequencer such that the input data stream in converted into the second format.

Abstract: A quantum computer comprising a semiconductor substrate into which donor atoms are introduced to produce an array of donor nuclear spin electron systems having large electron wave functions at the nucleus of the donor atoms, where the donor electrons only occupy the nondegenerate lowest spin energy level. An insulating layer above the substrate. Conducting A-gates on the insulating layer above respective donor atoms to control strength of the hyperfine interactions between the donated electrons and the donor atoms' nuclear spins, and hence the resonance frequency of the nuclear spins of the donor atoms. Conducting J-gates on the Insulating layer between the A-gates to turn on and off electron mediated coupling between the nuclear spins or adjacent donor atoms.

Abstract: A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.

Abstract: A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.

Abstract: A microprocessor having an instruction queue capable of out-of-order instruction dispatch and efficiently detect full conditions is disclosed. The microprocessor may comprise a plurality of instruction execution pipelines, an instruction cache, and an instruction queue coupled to the instruction cache and execution pipelines. The instruction queue may comprise a plurality of instruction storage locations and may be configured to output up to a predetermined number of non-sequential out of order instructions per clock cycle. The microprocessor may be further configured with high speed control logic coupled to the instruction queue. Instead of determining exactly how many empty storage locations are present in the queue, the control logic may be configured to determine whether the number of non-overlapping strings of empty storage locations is greater than or equal to the number of estimated instructions currently on their way to being stored in the instruction queue.

Abstract: A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.

Abstract: A processing unit, preferably a RISC based microcontroller, is coupled to a processing unit voltage regulator. The processing unit voltage regulator is used for controlling an operating voltage of the processing unit. A control unit is coupled to the processing unit voltage regulator and to the processing unit for setting a regulated voltage level for the processing unit voltage regulator. A voltage supply coupled to the control unit and to the processing unit voltage regulator is provided and is used for supplying the operating voltage for the processing unit wherein the operating voltage will have an upper and lower operating voltage level and an voltage supply operating range of approximately two to eighteen volts with relatively little variation in operating current.

Abstract: A system for switching resources of a computer among a plurality of programs is provided, including a processor for executing programs for the computer. The system further includes a set of register banks coupled to the processor for storing information for the plurality of programs, where each register bank includes a plurality of program information registers in correspondence with the plurality of programs, the set of register banks having a selection input for selecting a current program for the processor to execute. A status register is coupled to the processor for storing in a prioritized order a status bit corresponding to each program, where each status bit has a status bit address and indicates a status of the corresponding program as being one of active and inactive. Each location of the status register is connected to a program determination logic circuit for determining the status bit address of a highest priority active program.

Abstract: An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction.

Abstract: A system and method for accelerating web site access and processing utilizing a multiprocessor computer system incorporating reconfigurable and standard microprocessors as the web site server. One or more reconfigurable processors may be utilized, for example, in accelerating site visitor demographic data processing, real time web site content updating, database searches and other processing associated with e-commerce applications. In a particular embodiment disclosed, all of the reconfigurable and standard microprocessors may be controlled by a single system image of the operating system, although cluster management software may be utilized to cause a cluster of microprocessors to appear to the user as a single copy of the operating system.

Abstract: A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices.

Abstract: An embeddable microcontroller is provided. The microcontroller has program memory for storing instructions. An instruction decoder feteches instructions, decodes them, and forwards them to an enabler. The enabler checks a status bit or consults a pre-defined lookup table to determine whether the instruction at hand should be executed. If the status bit is set to ENABLE, or the instruction appears on a list of enabled instructions, the decoded instruction is forwarded to the central processing unit for execution. Otherwise, if the status bit is set to DISABLE, or the decoded instruction does not appear on the pre-defined list of enabled instructions, then the instruction is not forwarded to the central processing unit, effectively disabling the instruction.

Abstract: Provided are a system, method, program, and data structure for processing a request for data in a first format that is superimposed on blocks of data stored in a second format in a storage device. A data structure for a storage unit in the first format including the requested data is accessed. There is one data structure for each storage unit in the first format being accessed. Further, at least one cache page storing blocks of data in the second format is needed to store one storage unit in the first format. A determination is made of one or more storage blocks in the second format that include the requested data. A determination is also made as to whether the storage unit data structure includes a pointer to a control block for a cache page that would include the determined storage blocks in the second format.

Abstract: An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory.

Abstract: A multi-processor computer system that includes at least one “regular” processor and one “enhanced mode” processor. The enhanced mode processor is preferably not turned over to the regular processor, but is initialized to look like an internal or external device, such as a disk drive or the like. In a preferred embodiment, fast access memory that is outside the addressable range of the regular processor is coupled to the enhanced mode processor and accessed through a RAM-disk device driver. In this manner, the amount of fast access memory available to the regular processor is increased.

Abstract: Disclosed is a fully-interconnected, heterogenous, multiprocessor data processing system. The data processing system topology has a plurality of processors each having unique characteristics including, for example, different processing speeds (frequency) and different cache topologies (sizes, levels, etc.). Second and third generation heterogenous processors are connected to a specialized set of pins, connected to the system bus. The processors are interconnected and communicate via an enhanced communication protocol and specialized SMP bus topology that supports the heterogeneous topology and enables newer processors to support full downward compatibility to the previous generation processors. Various processor functions are modified to support operations on either of the processors depending on which processor is assigned which operations.

Abstract: An embedded-DRAM (dynamic random access memory) processor architecture includes a set of DRAM arrays, a set of register files, set of functional units, and a data assembly unit. The data assembly unit includes a set of row-address registers and is responsive to commands to activate and deactivate DRAM rows and to control the movement of data throughout the system. With the present invention, large SRAM (static random access memory) caches and traditional caching policies are replaced with a pipelined data assembly approach so that the functional units perform register-to-register operations, and so that the data assembly unit performs all load/store operations using very wide data busses. Data masking and switching hardware is used to allow individual data words or groups of words to be transferred between the registers and memory.

Abstract: A graphics processor includes a plurality of interrelated functional modules and at least one register associated with each of the functional modules. The plurality of interrelated functional modules are interconnected by a data pipeline for conveying data, and each register is configured to control a function of its associated functional module. The graphics processor also includes a control bus interconnecting each of the registers for conveying instructions, and an instruction controller for decoding instructions for use with the graphics processor. The control bus and the data pipeline are physically separate, and the instruction controller includes a register setting unit adapted to set the registers via the control bus in accordance with a decoded instruction. This enables the function of each of the functional modules to be configured in response to each instruction.

Abstract: A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be executed is received and a number of stages of the pipeline is selected to execute the instruction as needed to perform a corresponding data operation. Unnecessary stages are bypassed to a reduced latency and the instruction is executed with the selected stages.

Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Abstract: A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type instructions is disclosed. FCOMI-type instructions, which normally store their results to integer status flag registers, are modified to store a copy of their results to a temporary register located within the floating point unit. If an FCMOV-type instruction is detected following an FCOMI-type instruction, then the FCMOV-type instruction's source for flag information is changed from the integer flag register to the temporary register. FCMOV-type instructions are thereby able to execute earlier because they need not wait for the integer flags to be read from the integer portion of the microprocessor. A computer system and method for rapidly executing FCOMI-type instructions followed by FCMOV-type instructions are also disclosed.