Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A method for generating an intermediate representation of computer program code written for running on a programmable machine comprises: (i) generating a plurality of register objects for holding variable values to be generated by the program code; and (ii) generating a plurality of expression objects representing fixed values and/or relationships between said fixed values and said variable values according to said program code; said objects being organized into a branched tree-like network having all register objects at the lowest basic root or tree-trunk level of the network with no register object feeding into any other register object.

Abstract: A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. The intermediate representation is generated to include a combination of register objects and expression objects. Register objects represent abstract registers that provide a representation of the state of the first programmable machine based on expected effects of the instructions within the first program code, while expression objects represent elements, such as operations or sub-operations, of the instructions in the first program code. In the intermediate representation, a branched tree-like network is formed in which each register object serves as a basic root of the network and references expression objects to which they relate either directly or indirectly through references from other expression objects.

Abstract: The present invention is an integral parallel machine for performing intensive computations. By combining data parallelism, time parallelism and speculative parallelism where data parallelism and time parallelism are segregated, efficient computations can be performed. Specifically, for sequential functions, the time parallel system in conjunction with an implementation for speculative parallelism is able to handle the sequential computations in a parallel manner. Each processing element in the time parallel system is able to perform a function and receives data from a prior processing element in the pipeline. Thus, after a latency period for filling the pipeline, a result is produced after clock cycle or other desired time period.

Abstract: A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine employing run time generation of an intermediate representation of the first program code. Upon first encountering a given portion of program code, only the target code necessary to execute that portion of program code under a prevailing set of entry conditions is initially generated and stored. When the same portion of program code is again encountered, a determination is made as to whether intermediate representation corresponding to a second subsequent set of conditions has been generated. If not, the target code necessary to execute the same portion of program code under that second set of conditions is generated.

Abstract: A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute instructions on data provided from the local store, and at least one issue logic unit operable to convert instructions provided from the local store into operations of the functional unit for executing the instructions. The at least one issue logic unit may be operable to decode a unitary instruction provided from the local store to simultaneously operate all of the functional units according to the unitary instruction. Each issue logic unit may be operable to decode multiple instructions to separately operate first and second subsets of the plurality of functional units according to respective ones of the multiple instructions.

Abstract: A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a data rebuffering section disposed in the chip and adapted to couple data from a one of a plurality of data ports to a data port of the microprocessor selectively in accordance with a control signal; and (ii) a main memory interface adapted for coupling to a main memory for the microprocessor, such main memory interface being adapted for coupling to the microprocessor and being coupled to the data rebuffering section for providing control signals to the main memory section for enabling data transfer between the main memory and the microprocessor through the data rebuffering section.

Abstract: A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination processor. The bit is positioned in a send register associated with the originating processor and transposed from the send register of the originating processor to a receive register of the destination processor. An interrupt signal is then generated in response to the bit being transposed.

Abstract: A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes processing a sequence of packets with a sequence of threads, with the sequence of threads spanning multiple programmable processing elements integrated within a processor, and with the programmable processing elements providing multiple threads of execution such that each of the threads acquires exclusive modification access to data shared.

Abstract: A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core includes an integer execution unit that may be configured to execute integer instructions. The complex computing unit may be configured to execute complex vector instructions. The complex computing unit may include a first and a second clustered execution pipeline. The first clustered execution pipeline may include one or more complex arithmetic logic unit datapaths configured to execute first complex vector instructions. The second clustered execution pipeline may include one or more complex multiplier accumulator datapaths configured to execute second complex vector instructions.

Abstract: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.

Abstract: A voltage is applied across gate electrodes (103A) and (103B) in a two-dimensional electronic system (101) placed under a magnetic field, and the polarity of an electric current passed between ohmic electrodes (102D) and (102S) is selected to bring about inversion of electron spins based on a non-equilibrium distribution of electrons in a quantum Hall edge state and to initialize the polarization of nuclear spins. An oscillatory electric field of a nuclear magnetic resonance frequency is applied to coplanar waveguides (104A) and (104B) to control the nuclear spin polarization. The controlled spin polarization is read out by measuring the Hall resistance from ohmic electrodes (102VA) and (102VB).

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.

Abstract: A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the device in a second state or mode. The second state or mode can be temporary. The changing of the state or mode of the device can be used to perform testing of the chip, during which a memory is written to and read from to verify operation of the chip. The second state or mode of the device may also be used to allow the device to perform alternative functions that are not available during its first state or mode.

Abstract: A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.

Abstract: Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from the controller to the processor to indicate that the controller is not ready to execute the instruction. Initiation of execution of the instruction by the controller is done while continuing to indicate to the processor that the controller is not ready to execute the instruction.

Abstract: A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command decoder and an associated data aligner. A command buffer arbiter sequentially receives frame alteration commands and sequentially selects one of the frame data alteration engines for the sequentially received frame alteration commands. Each command decoder receives and decodes frame alteration commands and provides frame alignment commands and alteration instructions and each associated data aligner receives frame data and selectively latches data bytes of the received frame data responsive to the frame alignment commands and sequentially provides an aligned frame data output of a predefined number of bytes.

Abstract: A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which can be loaded individually into the local memory for execution. Queuing the individual blocks of code allows the program to be executed by the processor and also facilitates loading of the subsequent code to be executed. A semaphore system can be utilized to indicate which blocks of local memory are available/unavailable. A group of transfer parameters as queue entries allow code and data for an algorithm to be transferred between both local and external memory.

Abstract: An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first clock signal having a frequency. A control module is activated by edges of a second clock signal having a frequency, which is at least twice as large as the frequency of the first clock signal. The control module is constructed so as, in response to an request for access to the target module, initiated by the initiator module on an active edge of the activation signal, to set a signal for blocking the activation signal before the next edge of the latter, and to reinitialize the blocking signal on the first active edge of the first clock signal which follows the indication by the target module that the processing of the request is terminated at the target module.

Abstract: An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM1 stored in the external ROM to a high-speed processing region of an internal RAM. When a fetch address AZ1 specified by the MPU indicates a region of the external ROM in which the high-speed processing part PGM1 is stored, the address translation unit translates the fetch address AZ1 to the address AF of a region of the internal RAM corresponding to the high-speed processing part PGM1.

Abstract: A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The hardware/firmware layer eliminates the need for an operating system. Each of the Managers comprises a microcontroller associated with a firmware embedded in ROM or Flash memory that contains instruction sets that cause the microcontroller to provide a designated task of device management, information management, memory management and process management. In another aspect of the invention, devices connected to the computer system are “smart devices,” each device having a device microcontroller and embedded device drivers in a ROM or Flash memory. The hardware/firmware of the present invention does not need to search for available devices, provide diagnostic tests or obtain device drivers to communicate with the devices.

Abstract: The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped against a corresponding desired set of heuristics. Heuristics relating to job requests submitted by processes in the computer system are monitored and analysed. These heuristics may include the number of read and write requests, the ratio of read requests to write requests, input/output throughput, disk utilization and the average time taken for processes to submit subsequent jobs once an initial job completes. The analysed heuristics are compared to the desired sets of heuristics for the plurality of input/output schedulers to select one of the plurality of input/output schedulers.

Abstract: A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

Abstract: The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.

Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.

Abstract: An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled with the multimedia system in which the multi-processor multimedia chips are disposed. The present invention is comprised of a data memory to retrievably store data. The present invention is further comprised of an instruction memory to retrievably store instructions. The present invention is also comprised of an incoming buffer which permits transfer of data into the data and communication apparatus and provides fast access to streaming data. The present invention is additionally comprised of an outgoing buffer which monitors and permits transfer of data out of the data and communication apparatus.

Abstract: The present invention provides system and methods for executing a sequential in parallel. Parallel procedures, specified in the program, are executed as parallel slave processes. A process when actually accessing a ‘synchronous object’ that does not contain the data value same as in program's sequential run gets blocked till the right value is received. Object value transfer takes place through an ownership queue. Synchronization over referred objects along with run-time alterations in the linkage structure of the objects is also supported. In the event of a fault, aborted processes are rescheduled and redundancy in data storage is avoided.

Abstract: In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a resource is not ready, unnecessary attempts to execute subsequent instruction can be avoided. If a processor register has not yet been loaded and the next instruction attempts to use that register, the task will suspend. A task can also be suspended by incorporating a computer instruction that suspends the task after execution. A task can also be suspended by utilizing resources that provide one or more suspend indications.

Abstract: The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.

Abstract: A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process.

Abstract: A system comprises at least one processor, and supporting firmware for supporting at least one function of the at least one processor. The system further comprises logic operable to expand the functionality of the at least one function in a fashion that is not natively supported by the supporting firmware, and an interposer for supporting the expanded functionality of the at least one function. A method for expanding the functionality of an execution unit of a system comprises implementing an execution unit in a system, and implementing pre-existing support firmware for the execution unit in the system, wherein the pre-existing support firmware supports at least one function of the execution unit. The method further comprises implementing logic expanding the at least one function in a manner not supported by the pre-existing support firmware, and implementing an interposer to support the expansion of the at least one function.

Abstract: An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

Abstract: A microprocessor system includes a plurality of modules, among them a microprocessor and at least one storage module for storing the code and/or data for the microprocessor. Stored, in a non-changeable manner, in at least one of the modules, referred to as exchange-protected module, is a serial number of this module. A control module is configured to receive a data value specified by the at least one serial number and to block, at least partially, the function of the microprocessor system if the received data value does not match an expected data value encoded in the control module.

Abstract: The present invention provides devices and techniques for replacing at least one processor in a multi-processor computer system with an interposer device that maintains at least some of the input/output (“I/O”) connectivity of the replaced processor or processors. Layers of the interposer device may be configured to match the corresponding layers of the motherboard to which the processors and interposer device are attached. According to some implementations of the invention, the power system of the motherboard is altered to allow a voltage regulator that powers a link between a processor and the interposer device to also power a link between the interposer device and an I/O device.

Abstract: The present invention provides coupled-type computers wherein a computer can be coupled with computers of the same structure easily, and can be coupled with other computers of the same structure in high density. Computer components such as CPUs or memories are built in a holder made of polyhedron cube. A radio propagation bus space formed by a cavity is provided in the inside of the holder, and a plurality of radio-electric signal interconversion elements provided with a signal identification means facing the radio propagation bus space are disposed in the holder. These radio-electric signal interconversion elements are connected to the computer components in the holder. Holes communicating with the radio propagation bus space are bored on the surfaces of the outsides of the holders by means of the radio lines.

Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large numbers of computers connected, like the Internet, wherein more than one separate parallel processing operation involving more than one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network.

Abstract: The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data representing the result of the processing into the memory. The hardware block is capable of interacting with external hardware, thereby providing a flexible and universally applicable hardware block.

Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large numbers of computers connected, like the Internet, wherein more than one separate parallel processing operation involving more than one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network.

Abstract: A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that is to be executed if that branch instruction causes the program to branch. The data processing system includes a plurality of processing sections having a function unit, a local memory, and a pointer. The local memory stores instruction sequences from the program that is to be executed by the function unit in that processing section. The pointer contains a value defining the next instruction in the local memory to be executed by the function unit. Each function unit executes instructions according to machine cycles, each function unit executing one instruction per machine cycle. The pointers in each of the processing sections are reset to a new value determined by the target address of one of the branch instructions when a function unit branches in response to that branch instruction.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a control signal from the first processor to a selector, the selector switching electrical communication at least one signal line of the processor bus from the first bus to a second bus, sends a second instruction from the first processor to a second device, sends a control signal from the first processor to the selector, the selector switching electrical communication of the at least one signal line of the processor bus from the second bus to the first bus, and sends data from the first device to the first processor.

Abstract: The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated circuit may include receiving a specification for an integrated circuit having multiprocessors, the specification having a desired functionality. Functional components are chosen which provide the desired functionality of the received specification. The functional components are implemented in a modular multiprocessor reference design as an example system for the multiprocessor integrated circuit. The implemented functional components of the modular multiprocessor reference design may be suitable for testing software for operation by the multiprocessor integrated circuit. Moreover, the modular multiprocessor reference design enables testing of interaction of functional components for providing the desired functionality of the received specification.

Abstract: A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core (500) integrated as a single bus master, an integrated external bus interface (606) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: A bridge board connects a TMS470 processor evaluation module and a TMS320C54XX processor evaluation module. The bridge board performs translation of signal formats on both of the boards and also synchronizes the signal formats on both boards so that both boards are able to operate together. With this bridge board, and its specific connections to both of the evaluation modules, a single workstation, preferably connected to the TMS470 module is able to not only control the TMS470 module but also the TMS320 module. Software for the TMS320 can be loaded from the workstation through the TMS470 module, through the bridge board and into the TMS320 module. The software in both of the evaluation modules can then operate and interact with each other through the bridge board.

Abstract: A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional complicated control circuitry. On accepting an erase/write command which constitutes a rewrite command, a flash memory module (2) outputs to a flash memory control circuit (3) a ready status signal RYIBY indicative of a busy state during execution of the series of processing. When the ready status signal RYIBY indicates the busy state, the flash memory control circuit (3) outputs a hold signal HOLD at active “H,” in order to inhibit a CPU (1) from accessing the flash memory module (2). When the ready status signal RYIBY has recovered the ready state, the flash memory control circuit (3) outputs the hold signal HOLD at “L” to allow the CPU (1) to access the flash memory module (2).

Abstract: A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal processor (DSP) that is based on single-instruction-multiple-data (SIMD) principles and provides indirect access to vector elements. The disclosed configuration uses a processor with two vector units and associated registers, where the vector units are connected back to back for processing Viterbi decoder state metrics. Viterbi add instructions increment vectors of state metrics from a first register, performing a desired permutation of state metrics while reading them indirectly through vector pointers, and writing intermediate result vectors to a second register.

Abstract: Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.