Abstract: A system that can test individual components having tolerances on a circuit board without complete access to every node on the board is disclosed. The system uses a method that develops test limits from a model of the board, component tolerances, and a list of accessible nodes. A method of reducing the complexity of the test problem by limiting the number of components under consideration is also disclosed. A method of reducing the complexity of the test problem by limiting the number of nodes under consideration is also disclosed. A method of picking nodes to apply stimulus to a board is also disclosed. Finally, a method of correcting for certain parasitics associated with tester hardware is disclosed.

Abstract: A method and system for remotely troubleshooting a local computer connected to an array of local peripheral devices include a data collector connected to the local computer. The data collector includes a signal interceptor for intercepting signaling information transmitted by the computer to the peripheral devices. The intercepted signaling information has been formatted for processing by the local peripheral devices at a point of interception. The data collector further includes a transceiver having a transceiver input configured to relay signaling information received from remote peripheral devices located at a remote troubleshooting site to input/output (I/O) ports of local peripheral devices. A transceiver output is configured to transmit intercepted signaling information to the remote peripheral devices at the remote troubleshooting site.

Abstract: The present invention provides for satellite-based remote monitoring of equipment under test to perform predictive assessment from a central diagnostic site which houses a central diagnostic station. The satellite-based remote diagnostic system monitors several machines at various geographically remote locations. Information gathered enables the user to assess the health of the equipment under test. The user may also utilize the present invention to conduct specialized tests on the equipment under test to aid in predictive maintenance.

Abstract: A system for debugging a processor includes logic circuits for communicating commands and data between a serial input/output port, a trace logic, and the processor. Some embodiments of the debugging system also include a parallel input/output port so that the logic circuits also communicate commands and data between the parallel input/output port, the trace logic, and the processor. The debug system includes a plurality of state machines that read the commands and data from the serial input/output ports. The commands are decoded by a decode logic. Some of the commands, such as commands for reading data from memory, utilize processor intervention and are transferred to the processor for execution. The state machines operate only on a single command at one time so that an active state machine does not accept additional commands until completion of the command that is currently executed.

Abstract: A system for debugging a processor includes a data steering circuit for steering commands and data from a debug port and a parallel input/output port. The data steering circuit also directs commands and data to from the debug port and the parallel input/output port to the same set of debug registers. The data steering circuit also selectively directs trace information indicative of execution of instructions in the processor to either a trace buffer or directly out to a port, such as the debug port or the parallel input/output port.

Abstract: An integrated peripheral device comprises an associated register. The register comprises a data area containing a password. The register is connected to a read/write control unit, which generates an enabling signal after a first access which allows a data word to be written to the register during a following second write access. The read/write control unit comprises a comparator which compares data transmitted to the peripheral device during a first access with the password and generates a comparison signal, the read/write control unit only generates the enabling signal if the comparator generates a predefined comparison signal, for example, an equality signal.

Abstract: A modular reusable bus architecture enhances testability of an integrated computer system in which multiple modules communicate over a system bus. Under the modular reusable bus architecture, the system bus can be configured to operate in different operation modes. In one embodiment, the bus architecture provides a test mode for testing an individual module within the integrated computer system, separate from the other modules. In another embodiment, the bus architecture configures the system bus to provide access to configuration registers and memory units disposed within each module, otherwise inaccessible in normal system operation. The modular reusable architecture can support any types and any number of modules, including modules incorporating analog and digital circuitry, and modules operating under different clock domains.

Abstract: The present invention provides method and system aspects for performing error data gathering from fault isolation registers of a computer system following a machine check occurrence. A method aspect includes utilizing firmware to perform failure information retrieval in software accessible registers and initiating a service processor (SP) for failure data retrieval in non-software accessible registers. The method further includes coordinating the combination of the failure information retrieved and the failure data retrieved in an error log for use in isolation of a fault source in the computer system.

Abstract: A method and circuit for testing a packaged semiconductor memory device allow the acquisition of information on redundant elements by performing one of three possible redundancy rollcall tests on the packaged memory chip. By stimulating the packaged device's pins, the memory chip is set in one of the three test modes. In the first test mode, a preset signal indicating redundancy is sensed and the state of an output pin is changed. In the second test mode, memory array rows are sequentially addressed and the state of an output pin is changed when a redundant row is addressed. In the third test, array columns are sequentially addressed and, when a redundant column is addressed, the state of the output pin to which the redundant column is mapped is changed.

Abstract: An apparatus, system and method permitting a variety of reset procedures and corresponding reset states. A device reset control register is provided for each I/O device adapter in single function or multifunction devices. The device reset control registers permit a greater degree of control over single function devices, multifunction device as a whole and individual device functions within a multifunction device. A device immediate status register synchronizes the various reset procedures. A logical power on reset procedure, a directed unit reset procedure and a directed interface reset procedure utilize the greater degree of control that the device reset control registers provide to force the I/O device adapter, single function device or multifunction device into a corresponding logical power on reset state, a directed unit reset state or a directed interface reset state.

Abstract: A multiprocessor system includes a plurality of processors. A debugger interface includes interface circuitry to interface the plurality of processors to a debugger. The debugger interface includes means for receiving a debugger command from the debugger. Debugger command directing means determines from the debugger command for which of at least one of the plurality of processors the debugger command is intended, directs the debugger command, via the interface circuitry to the at least one intended processor. A processor command is received from one of the plurality of processors, and processor command directing means directs the processor command, received from the one processor, via the interface circuitry to the debugger. The system is especially suited for debugging software that is executing on the plurality of processors of the multiprocessor system.

Abstract: The present invention is a system, method, and computer readable medium for representing program event trace information in a way which is very compact and efficient, and yet supports a wide variety of queries regarding system performance. The tracing and reduction of the present invention may be dynamic, in which case information is obtained and added to the trace representation in real-time. Alternately, the tracing and reduction may be static, in which case a trace text file or binary file is obtained from a trace buffer, and the reduction takes place using the trace file as input. The trace information, whether obtained statically or dynamically, is represented as a tree of events. The present invention may be used to present many types of trace information in a compact manner which supports performance queries.

Abstract: An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high.

Abstract: A system for testing a computer built into a control unit. A power supply unit is provided for the voltage supply for the control unit and the computer. In addition, the test result can be indicated by a device and/or means may be provided for shutting down the system regulated and/or controlled by the control unit. The control unit contains means that can bring the computer into certain operating modes. In addition, sensing means are provided that detect the current or voltage in the power supply circuit of the computer, whereupon the current or voltage detected is compared with at least one preset threshold value in comparator means. For actuation of the device and/or the cutoff, there are actuator means that indicate an error depending on the result of the comparison or cause all or part of the system to be shut down in reaction to such an error.

Abstract: A personal computer system is discloses which includes a diagnostic system which uses an input/output controller to perform diagnostic functions. Such a system advantageously allows diagnostic functions to be performed on the computer system including the system processor of the computer system. The diagnostic program may be stored within nonvolatile memory which is coupled to the I/O controller, thus allowing diagnostic functions to be performed without the need for the computer system memory of the computer system.

Abstract: A method for monitoring performance of a program. A periodically occurring event is detected and a stack associated with the program is identified in response to a detection of the periodically occurring event, which may be a timer interrupt. The stack is examined to identify each routine (and specific invocation point, or offset) that is currently executing in association with the program. Each routine (and offset) is represented as a node in a tree structure.

Abstract: In a diagnostic application, a plurality of independent test modules are executed in a multi-tasking fashion. The diagnostic application is modular with a front end module issuing commands to lower level modules. A lower level test dispatcher module receives information from the plurality of test modules pertaining to test parameters, including whether the test module is multitaskable. A test dispatcher controls the launching of the test modules according to the test parameters. A test definition tool is provided to graphically develop test scripts by moving icons from one list to another. The output of the test definition tool is a scripting language readable by the diagnostic application.

Abstract: A debug interface supports data transfer using read and write system calls that communicate data without stopping an executing kernel. The printf( ) command passes an information string to an executing operating system. The information string summons the operating system to use a serial debug port to signal to a debug device, such as a host system, that is connected to the serial port. The debug interface-supported read and write operations and system calls allow the kernel and executing applications software, respectively, to continue executing during the read and write data transfers. The debug interface includes support for a plurality of extended function sideband signals that extend the functionality of the read and write functionality to allow the processor to concurrently run kernel and application programs while transferring data using read and write operation.

Abstract: There is disclosed a single chip integrated circuit device having a bus system, functional circuitry, and external port, and a parallel/serial data packet converter interconnecting the bus system and the external port. The parallel/serial data packet converter is operable to convert parallel data from the bus system into bit serial packets for output through the port, and allocate a packet identifier to the bit serial packets in dependence on the information received from the bus system in accordance with a predetermined protocol. A method of effecting communication between a single chip integrated circuit device and an external device using such a parallel/serial data packet converter is also disclosed.

Abstract: An apparatus and a method for storing diagnostic software on a data storage device provides one or more ghost partitions overlapping a user partition on a data storage device. During a factory download of the application software as well as the diagnostics software, the apparatus creates a user partition and one or more overlapping ghost partitions. Next, it determines a minimum and maximum partition size for the ghost partition(s) and allocates the ghost partition size(s) appropriately. The apparatus then creates one or more master boot records (MBRs), one for each created partition. The ghost partition containing the diagnostics software is set as the active partition to allow the diagnostic software to be executed. Upon completion of the diagnostics process, the MBR for a second ghost partition is enabled so that upon reboot, download verification software located on a second ghost partition can be executed to ensure the correctness of the software downloading process.

Abstract: An improved dual-connector cable for connecting a computer to a serial instrumentation bus. In one embodiment, the serial instrumentation bus is a fieldbus, preferably either a Foundation fieldbus or a Controller Area Network (CAN) bus. The cable comprises a first terminal located at a first end of the cable for coupling the cable to the computer. The first terminal comprises a device connector which is configured to connect the first terminal to a connector on the computer. The cable also comprises a second terminal located at a second end of the cable for coupling the cable to the serial instrumentation bus. The second terminal comprises interface circuitry for interfacing the cable with the serial instrumentation bus. The second terminal further comprises a first bus connector that is electrically coupled to the serial instrumentation interface circuitry. The first bus connector is configured to connect to a mating connector for coupling to the serial instrumentation bus.