Abstract: A method of operating a data processing system includes predicting values for a set of thermal sensors based on an assumed inlet air temperature and a selected configuration state. Additional values are predicted for a plurality of assumed inlet air temperatures and a plurality of configuration states. Actual thermal sensor values are then determined. A measure of the difference between each set of predicted values and the set of actual values is determined and, based thereon, a most likely configuration state is identified. The plurality of thermal sensors preferably includes an inlet air thermal sensor suitable for determining air temperature at an inlet to the system. The configuration states includes a state in which one of the thermal sensors is malfunctioning. The measure of difference is determined by squaring a difference between each actual thermal sensor values and a corresponding predicted thermal sensor value and summing the squares.

Abstract: Methods, systems, and products are disclosed for verifying the integrity of web server content. Communication with a server is initiated and content is retrieved that is specified by a Uniform Resource Locator. The content is parsed and searched for an error message. When the content contains linked content, then the linked content is parsed and also searched for the error message. The error message is logged to indicate an existence of a partial page error.

Abstract: A method is provided for handling failures in a computer system including a compliance checking system in a computer network. In response to a client computer failing to obtain a compliance check, a determination is made as to a category of an error that at least partially caused the failure in obtaining the compliance check. As a result, the method includes performing an action to at least partially based on the determined category of the error. In some instances, the action can include allowing the client computer to connect to the network. Another method includes receiving a definition of a configurable mitigation rule, where the configurable mitigation rule describes an action to perform at least partially based on the category of an error. Yet another method includes receiving a selection of a security level of operation of the compliance checking system.

Abstract: The present disclosure relates to conducting testing on a remote client computer by a server computer. The remote client computer is connected to the server computer through a network which allows either the remote client computer or server computer to initiate a testing session with the other. Programs resident on the remote client computer and server computer initiate the session. A graphics test tool application program is resident on the server computer. The graphics test tool application program includes a set of instructions and data used to communication to a set of instructions and data in the remote client computer. Communication in particular is performed through a communication channel which further allows graphics tests to be sent from the graphics test tool application program to the remote client computer. The graphics tests may be timed as to how long they take to be sent to the remote client computer.

Abstract: A method of testing memory modules comprising jumping through all addressable memory blocks a first and second time is disclosed. Each jumped-to address is determined by first XORing the last two bits of the previous address, and then XORing the first result with a bit representation of the previous jump direction for a second result. The second result determines the direction of the next jump, either upwards or downwards. Each jumped-to address is XORed with its contents, and the result is written to the address. For initially empty and defect-free memory, this results in all 1 values written for the first time jumping, and all 0 values written for the second time jumping. Finally, after the second time jumping, all addressable memory values are checked, and any non-0 value addresses are identified as defective memory cells.

Abstract: A system and method for path saturation in a storage area network so that the throughput of the storage area network may be determined. The system and method includes a software utility suite that uses either a system administration scripting language, e.g., Perl or Korn shell, or by compiled or machine language software. The software utility suite includes a set of software tools to be installed on one or more computer systems sharing access to a data storage system, such as a storage area network (SAN). The software tools running on these separate computer systems communicate and collaborate in a peer-to-peer fashion in order to coordinate loading, testing and measurement of storage throughput on the shared data storage system. The software tools further coordinate the collection, storage and presentation of results data obtained through such loading, testing and measurement of the storage throughput of the shared data storage system.

Abstract: A method for diagnosing devices via a remote testing device (2) being connectable to devices to be diagnosed (1) via a communication network (4) is provided. Between the remote testing device (2) and the devices to be diagnosed (1) first diagnostics information is exchanged (S3, S8, S11-S16) to perform said remote diagnosing. The remote diagnosing is done in dependence of second diagnostics information being exchanged between (S6, S7) said remote testing device (2) and controlling devices (3) being connectable to said remote testing device (2) via said communication network (4).

Abstract: A method for testing a network device having modules for receiving and sending data packets in a network includes generating in the network device at least one internal data structure associated with a data packet received by the network device from the network. A predefined action on the network device is then preformed responsive to the internal data structure indicating that the data packet satisfies a predefined condition.

Abstract: Various technologies and techniques are disclosed for performing load tests based upon user pace. A load test application is provided. Load test settings are received from a user that includes a test mix based upon user pace. A test start interval is calculated using the text mix. A load test is performed based upon the text mix. For example, the tests are executed at a pace that is based upon the test start interval for the particular user profile that the test is contained within.

Abstract: A test system for testing memory modules uses vertically-mounted personal computer (PC) motherboards. Many test adaptor boards that contain test sockets for testing memory modules are mounted horizontally across a test bench. Each test adaptor board connects to a motherboard that tests the memory modules in the test sockets. The motherboard is mounted below and perpendicularly to the test adaptor board. The motherboard is modified to extend the memory bus to edge contact pads along an edge of the motherboard. An edge socket on the test adaptor board mates with the edge contact pads to make electrical connection. A robotic arm inserts a memory module into the test socket, allowing the vertically-mounted motherboard to execute programs to test the memory module.

Abstract: A Dedicated Administrator Connection (DAC) for a database server is provided that allows a user with administrator privileges to connect to the database server when a connection by standard means fails. By allowing an administrator to connect to the server through the DAC, the administrator can resolve the issue despite the failure and bring back the server to a responsive state without requiring the server to be shut down and restarted. Additionally, support engineers, developers, etc. can use the DAC to diagnose a range of problems without the use of a debugger or requesting a repro while monitoring for issues.

Abstract: A load testing apparatus and method has a display unit for the presentation of data that relate to a load test of a telecommunication network. The display includes a graphical user interface with the load test being divided into several test phases and on the graphical user interface functionalities being assigned to these test phases. The load testing apparatus further has a storage device into which user identifiers are enterable, and the functionalities are pooled into groups so that for each identifier there one or more groups of functionalities may be enabled.

Abstract: A method for guiding to solve system errors is applied to a computer system. The method of the invention includes the step of calling a debugging application software to check a system state of the computer system when a request for detecting errors inputted by a user is received. When a system error occurring in the computer system is detected, a client database is connected to determine whether a corresponding solution for the user to debug the computer system exists. When the solution corresponding to the system error is not searched out from the client database, a network is connected to transfer a detected error message to a client service terminal.

Abstract: A system of testing a computer includes at least a computer (10) to be tested and a testing server (60) that connects to the computer. The testing server has test scripts for testing the computer. The system of testing the computer further includes a bootable disk (20) that connects to the computer. The bootable disk includes a testing image for starting up the computer. A method of testing a computer based on the testing system includes steps as follows: connecting the bootable disk to the computer to startup the computer; downloading test scripts from the testing server to the computer; running the test scripts and testing the computer.

Abstract: A virtual appliance environment (VAE) consists of components residing on a computer BIOS ROM and also on a mass storage device. The VAE includes a virtual appliance (VA) for diagnosing malfunctioning hardware or software. The VA for diagnosing malfunctions tests the hardware and/or software resident in the computer and transmits the results of the test to a server, which diagnoses the problem and transmits instructions to the VAE for saving the data, determining whether the computer is under warranty, and providing shipping information to a user. The VAE can also download a VA for scanning viruses. The VAE transmits the results of the virus scan to the server, which determines the type of virus infecting the computer and transmits instructions to the virtual appliance for downloading the appropriate VA for removing the virus. The VAE can save the data to another source, remove the virus, and restore the data or simply remove the virus.

Abstract: A single-usage network tap monitors network information flow over a particular connection. Instead of requiring a tap for each analytical device, by incorporating elements that regenerate, spread, and coordinate the timing of the signal, multiple, simultaneous, and parallel analytical devices can monitor a particular network connection through one tap, It incorporates four amplifiers preferably manufactured on the same IC die with high-impedance input terminals connected directly to the two conductors of a gigabit Ethernet local area network digital transmission line so as not to load or otherwise upset its impedance or other parameters. The output terminals of the operational amplifiers are connected to and match the input impedance of the digital transmission protocol Gigabit analyzer. The gain of the operational amplifiers is arranged so as to replicate at the input of the analyzer the signals appearing on the Gigabit local area network transmission line with uninterruptible power supply.

Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.

Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.

Abstract: A test board includes a plurality of sockets for connection to a plurality of integrated circuit chips to be tested. A test control device on the board turns on at least one test engine for testing the plurality of chips simultaneously. A checking circuit verifies the functionality of each chip by comparing outputs of chips with each other or with a golden chip. Failing Chips are disconnected from further testing and passing or failing chips are recorded.

Abstract: A system and method for correlating end user error reports with software developer defect logs to thereby update the end user error reports with information from the developer defect logs. With the system and method, when support personnel open an end user error report to address the problem encountered by the user, the mechanisms of the system and method search a defect report database to determine if there is any defect report related to the same error that is the subject of the opened end user error report. If so, the end user error report is updated to include information from the defect report. This information may include, for example, the identity of the source of the problem generating the error, the identity of the fix or patch that solves the problem generating the error encountered by the end user, if any, and the like.

Abstract: A system and method for remotely controlling a debugging unit, which can easily and accurately control the debugging unit in real time from a remote location regardless without data loss are disclosed. The system for remotely controlling a debugging unit comprises: a first protocol converter for converting a first or a second message between User Datagram Protocol (UDP) and Transmission Control Protocol (TCP), wherein the first message contains a debugging command and the second message contains debugging results; and a second protocol converter for converting a first or a second message between UDP and TCP.

Abstract: The present invention aims at providing a debugging mechanism capable of detecting erroneous read access to a bus slave caused by a synchronization control infringement between bus masters due to a failure of software. Each of a dirty detector and a coherency error detector is used as a detector for monitoring a bus control unit and, during a period that write access corresponding to optionally designated conditions is present on a write buffer, detecting read access corresponding to conditions equal to the aforementioned conditions. A bus master includes a debugging unit. The debugging unit receives a coherency error notification from the coherency error detector to generate a debugging event, breaks an operation of the bus master, and performs various debugging operations while using the debugging event as a trigger.

Abstract: An apparatus and program product check for nodal faults in a row of nodes by causing each node in the row to concurrently communicate with its adjacent neighbor nodes in the row. The communications are analyzed to determine a presence of a faulty node or connection.

Abstract: A semiconductor IC capable of debugging two or more processors at the same time by means of a single debugger and a semiconductor IC test system. The semiconductor IC includes processors operating at different frequencies, a trigger circuit which causes all of the processors to be in a debugging state when one of the processors is in the debugging state, and a JTAG circuit applying a boundary scan operation to the processors connected to a JTAG pin in series.

Abstract: The integrated test framework of the present invention includes a test framework runtime that executes test scripts and that also allows a script to identify a variation tool called a “data provider” that is responsible for providing data to the test framework runtime and controlling the iteration of the runtime through the variations. The script also identifies the type of data set from which the data provider should obtain the data from which the variations are derived and the location of the data set. Multiple variation data providers may be used in conjunction with an adapter layer that coordinates the iteration of each variation data provider and creates an aggregated variation over multiple varying parameters of different scope.

Abstract: Commanding a JTAG bus cross point switching device by the same bus which it configures. Adding, omitting, or rearranging devices on a JTAG bus with a cross point switching device that is included in a JTAG chain. Controlling the switching device with commands on the JTAG bus which it configures.

Abstract: In a storage system including an information processing apparatus and a storage apparatus that is communicably connected to the information processing apparatus via a communication network and that writes or reads data to or from a storage device in response to a data write/read request transmitted from the information processing apparatus, real resource operations are managed, with virtual resources set by assigning the real resources and the settings changed in conformity with the operating status of the real resources.

Abstract: A system for automatically testing motherboards includes a test server (1), client computers (2), and a network (5) connecting the test server with the client computers. The test server is for storing a plurality of high-level OSs (Operating Systems), test programs and test script files, for setting contents of test configuration files, and for storing test results. Each client computer has a motherboard installed therein, and is operated under a DOS (Disk Operating System). The client computer downloads and installs a high-level OS from the test server, downloads and installs one or more test programs and a test script file according to a test configuration file set by the test server, executes the test script file to auto-run test programs in a sequence specified in the test configuration file, and then transmits test results to the test server.

Abstract: The present invention provides a data processing apparatus and method for storing trace data. The data processing apparatus comprises a bus operable to interconnect a number of master devices and slave devices to enable transactions to be routed between the master and slave devices. Each master device is able to initiate a transaction, with the transaction specifying a transaction address. A cache is interposed between at least one of the master devices and the bus and is operable to receive the transaction issued by that master device. The cache has a cache memory and a cache controller operable to control access to the cache memory. The cache controller comprises caching logic operable to selectively cache a data value of the transaction at a location in the cache memory chosen dependent on the transaction address. Control storage is provided identifying a trace address range specifying a trace region.

Abstract: In one embodiment, a computer automatically determines whether one or more debug indicators, each of which is associated with one or more of a plurality of test data items, indicate 1) that one or more of the test data items pertain to a production mode, or 2) that one or more of the test data items pertain to a debug mode. At least one mode selector is displayed via a graphical user interface (GUI). Upon a user selecting the production mode or the debug mode, the GUI is updated to focus on a display of production test data or debug test data. Other embodiments are also disclosed.

Abstract: An integrated circuit having a plurality of functional circuits interconnected via a functional bus is provided with a diagnostic bus-master circuit which uses bus transactions on the functional bus to perform diagnostic operations. These diagnostic operations can be performed in real time during normal speed operation of the integrated circuit to produce more accurate diagnostic results. The diagnostic bus-master circuit is particularly useful for reading data values from memory or writing data values to memory as part of diagnostic operations.

Abstract: A computer-implemented method, system, and computer-readable medium for inducting a software project into a software factory is presented, wherein an induction process identifies what processes and sub-processes are needed to create the software factory, and wherein the induction process identifies potential risks to the software factory.

Abstract: A strategy is described in which multiple testing agents perform multiple respective tests in a multi-user environment. One such multi-user environment allows multiple clients to interact with remote applications that are executed on a server. According to one exemplary case, a central test management module coordinates the execution of the multiple tests by the testing agents. For instance, the test management module can prevent testing agents that make demands on a global state of the multi-user environment from interfering with other testing agents.

Abstract: Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory addresson the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.

Abstract: A test and debug processor capable of initiating, commanding and executing JTAG-bus functions without the involvement of an external CPU. The processor includes a JTAG-bus controller with a JTAG port coupled to it. The JTAG-bus functions are encoded in instructions and stored in a memory structure. The processor instructions are then fetched and executed directly by the JTAG-bus controller without software interpretation. The instructions optionally includes JTAG-bus end state, function duration information, information about the location of the data to be sent out to the test object and a location to store the information received from the test object. Optionally, the test and debug processor can directly access any memory structure to fetch or store test data objects by adding a memory bus-controller interface to the processor. The ability to execute arithmetic and logic operation and register transfer operations on test data can be added using an ALU.

Abstract: A data processing system 2 is described having a central processing unit 4 and a diagnostic mechanism 10. The central processing unit 4 is switchable into a power-down mode from which it may resume into a normal operation mode. When the central processing unit 4 resumes into the normal operation mode, execution of program instructions is inhibited by the diagnostic mechanism 10 to allow the diagnostic mechanism to be appropriately programmed such that the immediate power-up code and operations can be properly diagnosed. The requirement to prevent program instruction execution on power-up is programmed by writing to a latch 16 within the diagnostic mechanism 10 prior to the power-down. The prevention of program execution may be achieved, for example, by generation of a halt request or by extending the time period for which the central processing unit 4 is held in reset following power-up.

Abstract: Test apparatus for testing a circuit unit. A first test device is arranged outside the circuit unit. A second test device, which is arranged integrally with the circuit unit, has a sample-and-hold unit for sampling at least one voltage value of an output signal output from the circuit unit and for holding the sampled voltage value, and a logic unit for driving the sample-and-hold unit. The voltage value sampled by the second test device is fed to the first test device as a test result signal.

Abstract: In an information processing system including one or a plurality of processors, a diagnostic program is executed with a predetermined frequency to diagnose the processors. The diagnostic program generates one or a plurality of processes or threads at a predetermined frequency, at predetermined time intervals, for example, to diagnose the processors. A generated process or thread executes diagnosis on each processor, and the process or thread that detected a fault in the processor finishes its execution by storing fault information in storage. The process or thread of another processor other than the faulty processor refers to the fault information about the faulty processor and executes a troubleshooting process.

Abstract: A method and a system for automatically diagnosing disability of computer peripheral devices are provided. In the method, a set of interrupt configuration data relevant to a disabled PCI peripheral device, including relevant setting values of a hardware IRQ routing, is input and compared with a PCI IRQ routing table pre-stored in a boot control unit. Then, whether errors exist in the current setting values of the relevant control parameters and flags of all the relevant control units are automatically checked. If an incorrect setting value is found, a corresponding diagnosis result message is displayed for informing the user to make a modification. Therefore, users can know the reasons that cause the computer peripheral device to operate abnormally and make the modification quickly and effectively.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target microprocessor with multiple execution units of a same type. The method includes selecting one of the execution units for testing and scheduling the parallel execution of program code and diagnostics code. The diagnostic code is scheduled to be executed on the selected execution unit. The program code is scheduled to be executed on remaining execution units of the same type.

Abstract: A program managing method in a web service system for providing a web service for testing a message which has been changed in response to a change made in interface definition information comprises steps for judging as to whether or not an error occurs when an access request made by a message is transmitted, which is caused by the change of the interface definition information indicative of an interface of a destination of the access request; changing the message in correspondence with a content of the changed interface definition information in the case that the error occurs which is caused by the change of the interface definition information; and transmitting an access request made by the changed message in a test mode. It then becomes possible to correct and test the program in a dynamic manner for preventing recurrence of this error.

Abstract: A simulated internet is connected to a corporate network to more easily and effectively facilitate testing the impact of internet security devices and settings on internet software. The simulated internet has communications pathways between two firewall devices, a web proxy and a publishing firewall, that also protect the corporate network. A test web server on the corporate network is published to the simulated internet by the publishing firewall through reverse proxy as a unique internet name that only exists on the simulated internet One or more test client machines on the corporate network are configured to use the forward proxy firewall of the corporate web proxy to access the unique internet name. With this configuration all the pieces are in place for what the Internet does, except the simulated internet is a private internet under the control of the software tester.

Abstract: There are provided a central processing unit (2), a high-speed serial communication interface circuit which can be utilized for a debugging interface, for example, a USB interface circuit (3), and an external bus interface circuit (5) which can be connected to an external memory. The USB interface circuit has a plurality of input buffers (EP 1, EP 2) therein and data can be output from one of the input buffers in parallel with an input operation to the other input buffer. In a debugging mode, the USB interface circuit receives a system program, and the system program thus received can be output from the external bus interface circuit together with a memory access control signal. When a target program is to be downloaded from a host computer into a target system, a speed of a data transfer can be increased.

Abstract: An integrated circuit is described that includes a stored program processor for test and debug of user-definable logic plus external interface between the test/debug circuits and the component pins. The external interface may be via an existing test interface or a separate serial or parallel port. Test and debug circuits may contain scan strings that may be used to observe states in user-definable logic or be used to provide pseudo-random bit sequences to user-definable logic. Test and debug circuits may also contain an on-chip logic analyzer for capturing sequences of logic states in user-definable circuits. Test and debug circuits may be designed to observe states in user-definable circuits during the normal system operation of said user-definable circuits.

Abstract: Described is a headless server appliance configured with a secondary actuation mechanism that when actuated, enters the headless server appliance into a diagnostic mode. For example, the diagnostic mode may correspond to a secondary operating system booted from a BIOS component activated by the secondary actuation mechanism. In the diagnostic mode, primitives may be communicated between a client device coupled (e.g., via a network or USB connection) to the headless server appliance, such as to provide the client device with access to the headless server appliance's hard disk. Other primitives, such as communicated via APIs, may provide the client device with access to the BIOS. The secondary operating system and/or client device may perform diagnostics and recovery operations on the headless server appliance. For example, the client device or similar source may restore or update the primary operating system image to a storage medium of the headless server appliance.

Abstract: A device that can autonomously scan a sensor panel is disclosed. Autonomous scanning can be performed by implementing channel scan logic. In one embodiment, channel scan logic carries out many of the functions that a processor would normally undertake, including generating timing sequences and obtaining result data; comparing scan result data against a threshold value (e.g., in an auto-scan mode); generating row count; selecting one or more scanning frequency bands; power management control; and performing an auto-scan routine in a low power mode.

Abstract: A system and method for autonomously scanning a sensor panel device, such as a multi-touch panel, is disclosed. In one embodiment, the system and method disables a sensor panel processor after a first predetermined amount of time has elapsed without the sensor panel device sensing any events. One or more system clocks can also be disabled to conserve power. While the processor and one or more system clocks are disabled, the sensor panel device can periodically autonomously scan the sensor panel for touch activity. Accordingly, if one or more results from the autonomous scans exceed a threshold, the sensor panel device re-enables the processor and one or more clocks to actively scan the sensor panel. If the threshold is not exceeded, then the sensor panel device continues to periodically autonomously scan the sensor panel without intervention from the processor. Furthermore, the sensor panel device can periodically perform calibration functions to account for any drift that may be present in the system.

Abstract: A network management apparatus performing trouble-shooting in each device state and improving the operation efficiency and workability in maintenance management operations. A table storage unit stores a device status table, a restriction condition table, and a trouble shooting table. An analysis unit determines whether a status change request satisfies the restriction conditions in the current device state. If the restriction conditions are not satisfied but trouble can be avoided, all the trouble shooting data are extracted until the restriction problems are eliminated. If the restriction conditions are not satisfied and trouble cannot be avoided, the cause for not being able to avoid trouble is extracted. Thus, an analysis of normality of the status change request is conducted. A user interface unit sends the extracted trouble shooting data or the cause for not being able to avoid trouble. A device communication unit transmits a command corresponding to the status change request.

Abstract: A software tool and method in which a source image is split into and spans across two or more image pieces having a data structure which fits onto a computer readable medium having an available storage capacity which is smaller than the size of the source image. Also, software tool and method which combines two or more image pieces of a source image on a destination medium into a re-combined image having a data structure corresponding to the source image.

Abstract: A method and system for monitoring a characteristic relating to real-time network health are described. The method includes detecting a functionality attribute of a service application accessed with a server of the network. Networking devices of the network are interrogated in relation to an operational status thereof. The real-time network health characteristic is inferred from the functionality attribute and/or the operational status detected.