Abstract: Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory addresson the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.

Abstract: A data processing system (10) includes a CPU (12) and debug circuitry (16). CPU (12) can execute instructions which provide direct input to one or more of trigger circuitry (32), multi-function debug counters (34), combining logic (36), and action select and control logic (38). Breakpoints can be cascaded, and separate breakpoint sequences can be triggered from a same trigger. A selected trigger (117) can produce a resulting action or trigger (119) but only if it occurs in a predetermined order compared to one or more other triggers (117). Multi-function debug counters (34) can perform a wide variety of programmable functions, can be started and stopped using the same or separate triggers, and can be optionally concatenated with each other.

Abstract: An automated system for improving the testing of computer devices designed for coupling with docking devices. A plurality of networked computing devices that are individually connected to a compatible docking device through a slave switch. Each slave switch independently connects or disconnects individual computing devices from an attached docking device based on commands obtained from a server. By controlling the electrical connection between the individual computing devices and attached docking devices, the slave switch can simulate the action of docking or undocking one or more selected computers without human intervention. As a result, the present invention provides a system and method that automates the action of docking or undocking a computer. For example, the present invention is suited for use in computer device testing systems wherein a shut down command is sent to a selected computer, after which the selected computer is disconnected from an attached docking device.

Abstract: A check for a knowledge automation engine to use in detecting product issues on products. A knowledge automation engine may evaluate a check against a fact to detect a product issue on a product and provide a user of the product remediation information. A check may contain a product issue description, a rule to evaluate against a fact in order to detect the product issue, and remediation information to help a user address the product issue if the product issue is detected on the product. Product issues may include product installation validation and known product bugs. Facts used by the knowledge automation engine may include product configuration facts.

Abstract: A system for creating and editing checks for a knowledge automation engine to use in detecting product issues on products. A knowledge automation engine may evaluate a check against a fact to detect a product issue on a product and provide a user of the product remediation information. A check may contain a product issue description, a rule to evaluate against a fact in order to detect the product issue, and remediation information to help a user address the product issue if the product issue is detected on the product. Product issues may include product installation validation and known product bugs. Facts used by the knowledge automation engine may include product configuration facts. Checks may be created and edited using a standard interface.

Abstract: A fault simulator includes a circuit identifying section that selects, as fault generation points, circuit components subjected to a simulation from timing simulation results obtained by a static timing simulation of an LSI circuit; a fault value computing section that generates delay faults corresponding to the fault generation points using information about delay time and timing of signal transmission in the timing simulation result; and a fault simulating section that performs, by using a test pattern of the simulation, a logic simulation of a normal circuit of the LSI circuit and that of a faulty circuit where the delay faults are inserted into the fault generation points, and verifies detectability of the delay faults by the test pattern from the compared results of both the logic simulations. The fault simulator can reduce the time of the fault simulation.

Abstract: A start processing unit conducts start processings including a self diagnosis processing and a BOOT processing of an operating system and then starts an application when power of a computer system is turned on. A trouble notification unit controls the power of the computer system and integrally monitors a trouble of the start processing unit and a trouble during system operation. The trouble notification unit, provided as a server management support board, acquires log information stored in the start processing unit and notifies an external remote maintenance system of the log information as well as an alarm message trough a dedicated network interface when the trouble notification unit detects the trouble of the start processing unit (system down).

Abstract: A method, a system and/or a computer readable medium for accessing design data including an electronic image of an integrated circuit to be tested; determining whether a pin of the integrated circuit has been assigned to a port in a multi-port automated test environment; enabling a displayable pin indicator based in part upon the determination of whether a pin is assigned to a port; and displaying the electronic image and the displayable pin indicator.

Abstract: A logical partition (LPAR) computer system for managing partition configuration data is disclosed, which includes a nonvolatile memory, and a plurality of logical partitions, each running independently from the other logical partitions. The system also includes a console coupled to the computer system for accepting logical partition configuration data input by an operator. The configuration data entered by the operator specifies the processors, I/O, and memory allocated to each logical partition defined for the system. The system further includes a set of tables maintained in the nonvolatile memory for storing the logical partition configuration data, such that the logical partition configuration data is persistent across system power cycles.

Abstract: A two-phase method to perform root-cause analysis over an enterprise-specific fault model is described. In the first phase, an up-stream analysis is performed (beginning at a node generating an alarm event) to identify one or more nodes that may be in failure. In the second phase, a down-stream analysis is performed to identify those nodes in the enterprise whose operational condition are impacted by the prior determined failed nodes. Nodes identified as failed as a result of the up-stream analysis may be reported to a user as failed. Nodes identifies as impacted as a result of the down-stream analysis may be reported to a user as impacted and, beneficially, any failure alarms associated with those impacted nodes may be masked. Up-stream (phase 1) analysis is driven by inference policies associated with various nodes in the enterprise's fault model.

Abstract: A bootstrap program is loaded into an area of memory previously occupied by a run time program in a service module. The bootstrap program is loaded after the service module is reset due to an error. The service module does not have a persistent storage. The bootstrap program captures a memory image of the memory. The captured memory image of the memory is compressed and transferred to a control module to be stored in a persistent storage of the control module. The control module receives captured memory images from one or more service modules.

Abstract: A program-controlled unit has debug resources that outputs trace information including selected addresses, data and/or control signals and that can be used to trace the course of the operations occurring within the program-controlled. The debug resources monitor whether a predefined change in the level of one or more predefined bits of the addresses, data and/or control signals contained in the trace information has taken place, and start or terminate the generation of trace information as a function of the result of this check. Additionally or alternatively, the trace information that is output is a component of messages having a variable length portion that contains the trace information. Additionally or alternatively, the trace information that is output is a component of messages, and it is possible to determine which trace information is located at which point within the message.

Abstract: A library to be used in an ASIC design system includes information to be used for verification of test structures. The library includes information regarding the ability to combine test pins for verification of the test structure and information regarding the sharing of ports for verification of the test structure. A user of the ASIC design system can include custom test structures in the library for verification.

Abstract: During debugging of target system by a host system, s single stack is used for an exception by a set of applications running on the processor of the target. To achieve this, the stack is dynamically loaded by the host to a reserved memory region, and a vector of the target is set to point to that reserved memory region. The exception handlers of each application then use the vector to access the stack.

Abstract: A system and method for debugging a program which is intended to execute on a reconfigurable device. A computer system stores a program that specifies a function, and which is convertible into a hardware configuration program (HCP) and deployable onto a programmable hardware element comprised on the device. The HCP is generated based on the program, specifies a configuration for the programmable hardware element that implements the function, and further specifies usage of one or more fixed hardware resources by the programmable hardware element in performing the function. A test configuration is deployable on the programmable hardware element by a deployment program, where, after deployment, the programmable hardware element provides for communication between the fixed hardware resources and the program. The program is executable by a processor in the computer system, where during execution the program communicates with the one or more fixed hardware resources through the programmable hardware element.

Abstract: An apparatus generally comprising a plurality of processors, a trace circuit, and a connector circuit. The trace circuit may be configured to present information at a port for debugging software in a selected processor of the processors. The connector circuit may be configured to (i) couple the trace circuit to the selected processor in response to a select signal and (ii) transfer the information from the selected processor to the trace circuit while the selected processor is executing the software.

Abstract: A data storage system is disclosed in which a 3-party hand-off protocol is utilized to maintain a single coherent logical image. In particular, the functionality of the data storage system is separated into distinct processing modules. Each processing module is implemented in a distinct central processing unit (CPU). Alternatively, the first type processing module and the third type processing module can be implemented in a common CPU. Isolating the different functions of the data storage system into distinct CPUs facilitates failure recovery. A characteristic of the 3-party hand-off protocol is that, if an abnormal state occurs, a surviving module has sufficient information to proceed to recover from said abnormal state after detecting the abnormal state, without depending on a failing module, by retrying the data storage operation with another processing module or the failing module or cleaning up after the failed data storage operation, resulting in improved failure recovery.

Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Abstract: A program-controlled unit is described. The program-controlled unit has a central processing unit (CPU), peripheral units that are connected to the CPU via an internal bus, and debug resources that can be used to trace and influence operations taking place in the program-controlled unit. The program-controlled unit that is described is characterized in that the debug resources and the peripheral units, which output data from the program-controlled unit and/or can receive and pass on data which is supplied to the program-controlled unit from the outside, are connected to one another via a second internal bus. The data that is to be transmitted between the debug resources and devices provided outside the program-controlled unit are transmitted via the second internal bus and individual, a plurality of, or all the peripheral units connected thereto.

Abstract: A method for managing a plurality of failures in a video and data network is provided. The method includes discovering a failure in the video and data network. The discovered failure is the root cause of the failure. Next, the root cause failure is correlated with the plurality of failures to determine related failures generated as a result of the root cause failure. The related failures are then suppressed. One or more user's affected by the root cause failure are determined. If the root cause failure is automatically resolvable, the root cause failure is automatically resolved.

Abstract: The invention includes an integrated circuit (IC). The IC includes an internal test bus (ITB). The IC also includes a number of deskew clusters connected to the ITB. The deskew clusters each include a deskew controller. The IC also includes an integrated test controller (ITC) connected to the ITB. Further, the IC includes a debug unit connected to the ITC. The ITC generates a single global control signal and the deskew controller generates a first local command signal.

Abstract: An integrated circuit chip comprising embedded digital processor and an on-chip emulation device coupled to said digital signal processor, said emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port for off-chip communication, the chip further comprising an on-chip interface having a first port connected to said communication port of said on-chip emulation device and a second port for connection to a non-proprietary bus wherein said interface is operable to convert between a format suitable for said on-chip emulation device and a format suitable for said non-proprietary bus.

Abstract: A debugging system comprising a host computer system and a target device, said target device having an embedded digital processor on an integrated circuit chip, an on-chip emulation device coupled to said digital processor, the on-chip emulation device being operable to control said digital processor and to collect information about the operation of said digital processor, the on-chip emulation device having a communication port operable to receive information from and emit information to the host computer system wherein said debugging system further comprises an interface on said integrated circuit chip having a first port connected to said communication port of said on-chip emulation device and a second port connected to a universal serial bus, said host computer system having a universal serial bus port connected to said universal serial bus wherein said host computer system comprises a proxy server program for managing the universal serial bus port to enable communication over said universal serial bus, a

Abstract: An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.

Abstract: Electronic apparatus, such as a personal computer, is described comprising main operative functionality and a power provisioning system for powering the apparatus from an external power source, the power provisioning system comprising:—a main power supply output for energizing the main operative functionality of the apparatus when said power provisioning system is connected to said external power source, and a standby power source for energizing a subset of the components of the apparatus when said main power supply output is not energized, the apparatus further comprising a self contained subsystem including a memory for storing at least one parameter reflecting an internal state of the apparatus, said self contained subsystem being powered by said standby power source and including an encoder for encoding the parameters in an output signal and a transducer for generating a wireless transmission from the output signal, which transmission can be detected in the vicinity of the apparatus, so as to enable the p

Abstract: A remote maintenance and diagnosis apparatus for making a diagnosis of a remote client appliance comprises a data acquisition unit that acquires data necessary to diagnose the client appliance, a diagnosing unit that make an automatic diagnosis of the client appliance based on the data acquired by the data acquisition unit, and an automatic diagnosis result reporting unit that reports a result of the automatic diagnosis to the client appliance.

Abstract: A host computer has a file with a subroutine required for operation of an application on a target. The file is dynamically loaded to memory of the target, whereby the file has an entry point at a dynamically-determined location. Data representative of the address of the entry point is stored in memory at a predetermined location. The application is then run on the target, causing the application to determine the entry point, thereby accessing the subroutine and allowing the subroutine to run.

Abstract: A debugger mechanism to support multiple active targets and efficient switching between multiple active targets, in particular, heterogeneous targets, in a multiprocessing environment.

Abstract: A method performed by a computer system is provided. The method includes detecting a test module interface associated with a test module and calling a function identified by the test module interface to cause a test configuration of the test module to be created.

Abstract: Disclosed is internet-based service system and method for remotely restoring damaged data and files through the internet in case that the data and files stored in the hard discs and floppy discs of client personal computers (PC) are partly or entirely damaged. If a user connects to a restoration server through the internet network, a restoration plug-in module of client PCs and a restoration plug-in module of the restoration server will be compared after judging whether the user is registered. The damaged data and files will be restored by using the restoration plug-in module stored at client PC, a restoration result will be recorded and transfer to the restoration server for analyzing the result and the analyzed result will be transferred to client PC and simultaneously recorded on database.

Abstract: The invention relates to performing a service operation on a computer. In one embodiment, information indicative of the need for a service operation is sent by a customer computer to a support center. Based on this received information, the support center then identifies the service operation to be performed on the computer, such as the replacement of a faulty component. The support center then creates a service task record describing this service operation, which is transmitted from the support center to a mobile computing device associated with an engineer who is to complete the service operation. This typically includes schedule information, detailing when and where the service operation is to be performed. When the engineer then arrives at the customer location, a direct communication link is established between the customer computer to be serviced and the mobile computing device, for example using an infrared link.

Abstract: System for providing distributed group-based protection switching at a network element in a communication network. The communication network includes a plurality of interconnected network elements, and wherein the network element includes first and second card logic coupled to the communication network to transmit and receive network traffic. The system comprises selector logic distributed between the first and second card logic that includes first and second switching engines that have associated activity states that indicate how the network traffic is routed at the network element. The switching engines generate new activity states based on selected fault indicators. A processing system operates to detect fault conditions, generate the selected fault indicators, and receive the new activity states from the switching engines to perform one or more switch reconfigurations at the network element based on the new activity states, and thereby implement the distributed group-based protection switching.

Abstract: A method, system, and recording medium of testing 1394 interface card are disclosed in the present invention. A plurality of ports for the 1394 interface card to be tested are respectively connected to ports of a reference 1394 interface card through cables. One port of the 1394 interface card to be tested and one port of the reference 1394 interface card are in enabled condition and the others are in disabled condition. Only a reference 1394 interface card and two PCI slots are used, the testing process is simplified, and the probability of testing error is decreased.

Abstract: A method of abstracting information through object interfaces is described. The object interfaces are used to present platform device information in a pre-boot service environment. Firmware tables such as Advanced Configuration and Power Interface and System Management Basic Input/Output System may be used to auto-configure diagnostic test suites through an abstracted software interface.

Abstract: A data processing system (10) includes a debug unit (14) that is capable of providing unobtrusive debug capabilities to the normal operation of the data processing system by controlling activation of all or a selected subset of a plurality of subsystems as needed for a debug operation. For example, power can be conserved by activating selected subsystems as needed for a debug operation. Furthermore, in one embodiment, the debug unit provides a level of activation, ranging from deactivation to full activation, to the selected subsystems which provides further control of the data processing system. In one embodiment, debug control and status registers (40) are provided for power management handshaking between the debug unit and the plurality of subsystems. The handshaking can be used to ensure that a debug operation may proceed properly since the selected subsystems are capable of providing status information to the debug unit.

Abstract: A distributed tester method and system communicates test recipes for testing electronic devices from a host computer over a network to a test site. The test site translates test recipes into test instructions for execution by a test engine that determines the status of the electronic device. For instance, in a tester for testing memory, a test recipe is defined and stored with a host computer to determine test data for storage on the memory device under test at the test site. The host computer controls execution of the test recipe over the network. The test recipe is defined and stored in an XML formatted data file transmitted over the network to a processor at the test site. The test site processor translates the XML formatted data into test instructions for execution by a test engine. The test engine determines whether the memory device under test accurately stores data and provides the results, such as erroneously stored data, to the host computer through the network.

Abstract: Building and testing complex electronic products especially large scale computer systems are handled with control remaining with the owner of the design while a contract manufacturer does the basic manufacturing processes and testing. Nearly all levels of testing are accomplished without sharing high level descriptions of the end product or its features by providing only low level files for test functions. Testing is accomplished without sharing the high level code descriptive of the system design so confidential information is retained. Testing using the low level data is made sufficient to identify what parts need repair despite the lack of high-level information transfer.

Abstract: A debugging circuit capable of debugging a plurality of possible microprocessors, and a switch for use in the same. The debugging circuit includes a debugging port, a plurality of microprocessor sockets each adapted to receive a microprocessor, and a plurality of switches corresponding to a respective microprocessor socket. The plurality of microprocessor sockets are adapted to form a serial signal path, and each of the switches is capable of automatically detecting whether a microprocessor is present in the corresponding microprocessor socket. If a microprocessor is present, the switch is automatically configured to include the microprocessor within the signal path, and if the microprocessor is not present, the switch is automatically configured so that the signal path bypasses that microprocessor socket.

Abstract: A method and system for analyzing a public switched communications network from a remote place via the public Internet. The system comprises an access device which collects data from one or more links in a public switched communications network. The system further includes a server computer which receives the collected data from the access device via a dedicated network or the Internet. The server computer executes one or more applications to perform protocol analysis based on the received data. A client computer executing a Web browser may be used to communicate with the server computer via the Internet and access the outcome of the protocol analysis.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A system and method for determining fault isolation in an enterprise computing system is disclosed. A method includes automatically troubleshooting errors in an enterprise computing system that receives at an analyzer engine a status notification from a first component. In response to receiving the status notification, the method automatically selects a first analyzer policy file from a set of analyzer policy files based on the status notification received at the analyzer engine, wherein the analyzer policy file contains troubleshooting logic for determining root causes for errors. The method automatically attempts to communicate with a second component based on the troubleshooting logic within the first analyzer policy file. The method automatically determines a root cause for the status notification based on the troubleshooting logic in the selected analyzer policy file and based on information obtained in connection with the attempt to communicate with the second component.

Abstract: The invention is a fault isolation method and apparatus for use in a network access server. The method includes allocating one or more modems in a group of modems associated with an access server to a debug modem pool; allocating one or more remaining modems in the group to a session modem pool; thereafter determining whether an incoming call to the access server meets predefined fault isolation criteria; and, if so, then allocating a debug modem from the debug modem pool to the incoming call and initiating a fault isolation session; and if not, then allocating a session modem from the session modem pool to the incoming call and proceeding with a normal session. Preferably, the defined criteria include at least one match between one or more user attributes associated with the incoming call and one or more corresponding fault isolation session attributes stored within the network access server. The criteria themselves may be configurable, e.g. definable by the user.

Abstract: A system for testing an application running on a point-of-sale (POS) terminal comprises a host running on a personal computer connected to the POS terminal, and a target running on the POS terminal. The host sends simulated keystrokes, card swipes and the like to the target, which passes these to the application under test. The target can send information to the host regarding the POS terminal status, such as the screen display, so that the host can send the simulated keystrokes, etc., to the target on a need basis. The host can also receive other data and send instructions to the target, e.g. it can obtain available RAM space details, file details and system clock details, and can send instructions to restart the application.

Abstract: Programmatic detection of time-gap defects in computer system hardware where data is corrupted without detection by the computer system. A detection module initiates data transfers between devices in a computer system. An interrupt service routine interrupts the process by inserting a delay into the data transfer. The detection module then checks for time-gap defects by determining if data was corrupted which went undetected by the computer system. The detection module may repeat the data transfer and insert successively longer delays until a time-gap defect is detected or until a maximum delay value is reached. The results of any time-gap defects found may be output to a user.

Abstract: The invention concerns a method for bit error injection into an equipment operating under the control of a given main programme, which consists in carrying out an interruption and introducing the bit error during the development of the interruption programme, wherein, when the error has to be injected into a target memory word stored at a site not directly accessible, the interruption programme comprises the following steps which consists in: placing in the stack (303) the content of a register (ACC), transferring (304) into the register (ACC) the content of the memory word, modifying (305) in the register (ACC) the repeated content of the target memory word to inject therein the selected error, transferring (306) the modified target memory word to its original site, unstacking (307) the register (ACC), and ending (308, 309) the interruption programme and returning to the main programme address indicated by the programme counter (PC).

Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.

Abstract: A method and a device for detecting risky types of data structures of a computer program code with a neural network. The neural network comprises neurons being related to each other by a topological arrangement involving a neighborhood definition. The neurons each comprising a vector for representing values of an input data space, at least one neuron having an associated label indicating the type of the neuron, and the data structures being detected comprising at least two elements. Information is extracted from at least two data elements from said at least one data structure and at least two input vectors are formed from said extracted information, the vectors being compatible with the vectors of the neurons. Said input vectors are compared with said vectors of the neurons, and the type of said basic data element is detected by using an associated label on the basis of said comparison.

Abstract: An LSI chip includes a plurality of output terminals and a test circuit. The test circuit includes a single test signal input terminal, a single test signal output terminal, a shift register, and a plurality of switches. The shift register includes an input terminal, which is connected to the test signal input terminal, output bits of the shift register being equal to a number of the output terminals of the LSI chip, and a voltage level of one of the output bits of the shift register being different from these of other output bits of the shift register in response to a clock pulse. Each switch includes an input terminal, an output terminal and a control terminal.

Abstract: Systems and methods are described for replicating virtual memory translation from a target computer on a host computer, and debugging a fault that occurred on the target computer on the host computer. The described techniques are utilized on a target computer having a processor that has halted execution. Virtual to physical address translation data from the target computer is transferred to the host computer. The host computer utilizes the virtual to physical address translation data to access data pointed by virtual memory addresses that were used by the target computer, and then debugs a fault by accessing the data by reading the physical memory address on the host computer. After the virtual to physical memory address translation data have been acquired, they can be cached at the host computer.

Abstract: Methods and systems are provided for monitoring a loosely coupled system, such as a web-based system and a business-to-business (B2B) system. In the case of a web-based system, exchanges between a web client and a web server may be monitored to determine quality and performance of the web-based system. The exchanges may include objects and attributes communicated from the web server to the web client. The exchanges may also include information about actions performed on objects as a user navigates through web pages displayed by the web client. For example, when the user selects a hyperlink, the monitoring system may recognize the hyperlink as an action. Accordingly, the actions along with the objects and their associated attributes may be recorded. The objects and their associated attributes may then be retrieved from the web server and the recorded actions may be played back against the retrieved objects based on the recorded attributes and the retrieved attributes.