Particular Access Structure Patents (Class 714/27)
  • Patent number: 6751569
    Abstract: A system that includes a computer system configured to boot using a system firmware is provided. The system firmware includes instructions for causing the computer system to provide a control code to a test apparatus configured to perform a functional test on the computer system and receive information provided by the test apparatus in response to the control code.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: June 15, 2004
    Assignee: Dell Products L.P.
    Inventors: Cynthia M. Merkin, Marc D. Alexander
  • Publication number: 20040098638
    Abstract: User logic within a PLD is debugged by way of the hub. The PLD includes a serial interface (such as a JTAG port) that communicates with a host computer. Any number of client modules are within the PLD and provide instrumentation for the PLD. A module is a logic analyzer, fault injector, system debugger, etc. Each client module has connections with the user logic that allows the instrumentation to work with the user logic. The hub communicates with each client module over a hub/node signal interface and communicates with the serial interface over a user signal interface. The hub routes instructions and data from the host computer to a client module (and vice-versa) via the serial interface and uses a selection identifier to uniquely identify a module. The hub functions as a multiplexor, allowing any number of client modules to communicate externally though the serial interface as if each node were the only node interacting with user logic.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 20, 2004
    Applicants: Altera Corporation, A Delaware Corporation
    Inventors: Nicholas James Rally, Alan Louis Herrmann
  • Patent number: 6738924
    Abstract: A disc drive includes a base and a disc rotatably attached to the base. A controller for a disc drive uses a system for mapping logical block addresses to actual location on a disc drive stores the number of skipped or defective sectors which occur prior to a target cylinder in a cylinder skip table. The system estimates a starting cylinder location for the selected logical block address. After estimating the cylinder location, a number of skipped defective sectors that have occurred prior to a cylinder start is determined. The starting location of the cylinder is slipped by this amount. A target track and associated head is also determined. Information in the track identification field is used to adjust the actual location on the track and to determine if a track seek to another track is needed.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: May 18, 2004
    Assignee: Seagate Tech. LLC
    Inventors: Steven S. Williams, Stanton M. Keeler, Daniel S. Fisher, Mike B. Propps, Edward S. Hoskins
  • Patent number: 6738929
    Abstract: An emulation controller (12) connected at a pin boundary of an integrated circuit (14) can be provided with concurrent access to concurrent debug signal activity of first and second data processing cores (core 2, core 1) embedded within the integrated circuit. A first signal path is provided from the first data processing core to a first pin (39) of the integrated circuit, for carrying a selected debug signal of the first data processing core to the first pin. A second signal path is provided from the second data processing core to the first pin of the integrated circuit for carrying a selected debug signal of the second data processing core to the first pin. A third signal path is provided from the second data processing core to a second pin (41) of the integrated circuit for carrying the selected debug signal of the second data processing core to the second pin.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: May 18, 2004
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Douglas E. Deao
  • Patent number: 6732295
    Abstract: The present invention provides a method of frequency modulated end-point detection. Control signals are sent to the manufacture device for performing the manufacturing process, wherein process signals are generated along with the manufacturing process. Process signals are filtered to obtain synchronization signals synchronized with the control signals. A judging standard is provided according to the synchronization signals corresponding to a specific state of the process. The synchronization signals are continuously monitored, and a process end-point is determined when the synchronization signals do not meet the judging standard.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: May 4, 2004
    Assignee: Winbond Electronics Corp.
    Inventor: Szetsen Steven Lee
  • Publication number: 20040083407
    Abstract: A system for analyzing bitmap test data includes a fault shape analyzer which continuously and automatically receives bitmap test data. In use, the user creates at least one failure pattern analysis order to be performed by the fault shape analyzer, the order specifying a particular failure pattern to be identified. Based on the order, the fault shape analyzer creates a bitmap display of a user-specified sector using selected bitmap test data. The fault shape analyzer identifies the user-specified failure pattern in the bitmap display by multiplying, at various locations, the bitmap display in the frequency domain and the failure pattern in the frequency domain. A comparison between the product of the multiplication process and the failure pattern is performed to locate failure patterns in the bitmap display. Failure patterns identified from the comparison process are saved as defect files which, in turn, are stored in a failure pattern classification database.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Xin Song, Stewart Hitelman, Chin-Jung Hsu
  • Publication number: 20040078668
    Abstract: According to the present invention, maintenance data about a plurality of distribution terminal devices which are different from each other in frequency with which they are in use and circumstances under which they are in use are transmitted to a host computer, whereby a lifetime of a semiconductor laser can be predicted and an occurrence of a trouble can be detected without receiving information from a user or shops in which the distribution terminal devices are installed.
    Type: Application
    Filed: September 26, 2002
    Publication date: April 22, 2004
    Inventors: Hidekazu Kamon, Eiji Tadokoro
  • Publication number: 20040078670
    Abstract: A communications processing section of a management apparatus sends a request for malfunction information via the Internet to one or more electrical devices being managed. A database manager of the management apparatus refers to data stored in a database and updates the record of the electrical device therein. A timing control section of the management apparatus carries out control so that the number of electrical devices requested upon by the management apparatus does not exceed a predetermined value. In this way, despite the management apparatus centrally manages the malfunction information of each electrical device, a peak quantity of the malfunction information received by the management apparatus can be suppressed and the workload on the management apparatus can be relieved, as opposed to the case where each electrical device sends the malfunction information at its own timing.
    Type: Application
    Filed: March 12, 2003
    Publication date: April 22, 2004
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Hidetaka Mizumaki
  • Publication number: 20040078669
    Abstract: The invention is characterized in that the data processing unit detects the error and then sends a first coded message to a central data processing facility. The central data processing facility decodes the signal and evaluates information on the error contained in the first message. Depending on the result of said evaluation, the central data processing facility then generates and/or selects an error elimination routine. The central data processing facility issues a program instruction that can be executed by the data processing unit. The program instruction is then coded by the data processing facility and sent to the data processing element as part of a second message.
    Type: Application
    Filed: December 6, 2002
    Publication date: April 22, 2004
    Inventors: Jurgen Lang, Bernd Meyer
  • Publication number: 20040068675
    Abstract: A circuit board with a boundary scan self-testing function comprises a substrate, a plurality of devices under test and an active testing device. The active testing device mounted the substrate can conduct circuit testing on the plurality of devices under test, and self-testing is allowed without employing any external testing equipment. The testing data of the active testing device is transmitted through a predetermined test route on the circuit board. Each of the devices under test is completely tested of all designated functions in either series connection or parallel connection with each other. The testing can help find out whether the devices have any defects.
    Type: Application
    Filed: September 2, 2003
    Publication date: April 8, 2004
    Inventor: Meng-Hsien Liu
  • Patent number: 6708291
    Abstract: Computer systems and methods of data processing are disclosed in which hierarchical descriptors define levels of fault/event management to intelligently monitor hardware and software and proactively take action in accordance with a defined fault policy. A fault policy based on a defined hierarchy ensures that for each particular type of failure the most appropriate action is taken. Hierarchical descriptors can be used to provide information specific to each failure or event. The hierarchical descriptors provide granularity with which to report faults, take action based on fault history and apply fault recovery policies. The descriptors can be stored in a master event log file or local event log files through which faults and events may be tracked and displayed to the user and allow for fault detection at a fine granular level and proactive response to events. In addition, the descriptors can be matched with descriptors in a fault policy to determine the recovery action to be taken.
    Type: Grant
    Filed: May 20, 2000
    Date of Patent: March 16, 2004
    Assignee: Equipe Communications Corporation
    Inventor: Joseph D. Kidder
  • Publication number: 20040049405
    Abstract: The invention relates to a management system for the provision of services, comprising telecommunication means enabling data to be exchanged between communication terminals associated with a master terminal and service providers, wherein the master terminal can transmit data, which enables a service provider to perform a service corresponding to an actual request, to the communication terminal of an available service provider.
    Type: Application
    Filed: August 11, 2003
    Publication date: March 11, 2004
    Inventors: Christof Buerger, Frank Elssner, Peter Poos
  • Publication number: 20040039965
    Abstract: One embodiment of the present invention provides a system that supports compatibility testing of functionality provided through an Application Programming Interface (API) on a computing device. During operation, the system loads a client testing module on the computing device. The system also loads a remote testing module on a server. Once the client testing module and the remote testing module have been loaded, the system identifies a communication protocol that is available between the computing device and the server, and configures a communication-protocol-specific portion of the client testing module to communicate with the remote testing module through the available communication protocol. The system then compatibility tests the functionality provided through the API on the computing device. During this compatibility testing, certain portions of the test execute within the client testing module while other portions of the test execute within the remote testing module.
    Type: Application
    Filed: August 22, 2002
    Publication date: February 26, 2004
    Inventors: Mikhail A. Gorshenev, Alexey V. Popov, Vasily N. Isaenko, Maxim N. Kurzenev
  • Patent number: 6697962
    Abstract: A remote monitoring system providing diagnostic and remedial functions to a computer system. The remote monitoring system comprises a service center and a diagnostic agent. The diagnostic agent is located proximate to the monitored computer system and electronically coupled to the monitored computer system such that the diagnostic agent can retrieve information about the various states of the monitored computer system. The diagnostic agent stores the retrieved information and further processes it for future use. Such information includes fault monitor information, accounting information, system performance information, and system management information. In addition, the diagnostic agent has control over the monitored computer system allowing it to perform diagnostic and remedial functions. Further, the diagnostic agent is electronically coupled to a service center located remotely to the monitored computer system.
    Type: Grant
    Filed: October 20, 2000
    Date of Patent: February 24, 2004
    Assignee: Unisys Corporation
    Inventors: Duane J. McCrory, Anthony P. Gold, Andrew Sanderson
  • Publication number: 20040034813
    Abstract: A validation device for a computer comprising hardware and software, the validation device being operable to;
    Type: Application
    Filed: February 26, 2003
    Publication date: February 19, 2004
    Inventors: Francois-Xavier Chaboud, Dany Drif, Eric Owhadi
  • Patent number: 6694204
    Abstract: A method and apparatus that includes a storage device for storing diagnostic executable code, a remote receiver and a processor that executes the diagnostic executable code. A remote signal is received at the remote receiver to access any portion of the code and obtain data from the processing of the diagnostic executable code.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: February 17, 2004
    Assignee: GSLE Development Corporation
    Inventors: Richard H. Bair, III, Bryan M. Elwood, Walter J. Tipton, Ronald W. Luyckx
  • Publication number: 20040010733
    Abstract: A fault identification system consisting of multiple reasoning engines and the blackboard analyzes alarm information and the associated contextual information to identify faults. The contextual information associated with an alarm is derived by analyzing the alarm along four spaces, namely, transaction-space, function-space, execution-space, and signal-space. The reasoning engines associated with these spaces infer and/or validate the occurrences of faults. Transaction reasoning engine, using the associated knowledge repository, processes the generated alarms to infer and validate faults. Monitor reasoning engine, using the associated knowledge repository, processes domain specific monitor variables to infer faults. Execution reasoning engine, using the associated knowledge repository, processes execution specific monitor variables to infer and validate faults. Function reasoning engine, using the associated knowledge repository, reasons to infer and validate faults.
    Type: Application
    Filed: July 10, 2002
    Publication date: January 15, 2004
    Inventors: Veena S., G. Sridhar, V. Sridhar, K. Kalyana Rao
  • Publication number: 20040003321
    Abstract: A system is initialized for operation in a protected operating environment by executing authenticated code that prepares various portions of the hardware for protection from non-trusted software. In one embodiment, initialization includes identifying and locking down specified areas of memory for protected processing, then placing trusted software into the specified areas of memory and validating the trusted software. In a particular embodiment, initialization may also include deriving and protectively storing identifying characteristics of the trusted software.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventors: Andrew F. Glew, James A. Sutton, Lawrence O. Smith, David W. Grawrock, Gilbert Neiger, Michael A. Kozuch
  • Publication number: 20040003322
    Abstract: The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to maintain the integrity of stored information. A system management processor detects an attempt to reboot the computer system and holds the system processor or processors in a reset state. While the system processor or processors are held in the reset state, the system management processor checks data such as the system BIOS to identify corruption. If the data checked by the system management processor is not corrupted, the system processor or processors are removed from the reset state and allowed to continue normal operation. If the data checked by the system management processor is corrupted, the system management processor repairs the corrupted data before removing the system processor or processors from the reset state.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: David L. Collins, Steven Ray Dupree
  • Patent number: 6662316
    Abstract: Electronic apparatus, such as a personal computer, is described comprising main operative functionality and a power provisioning system for powering the apparatus from an external power source, the power provisioning system comprising:—a main power supply output for energising the main operative functionality of the apparatus when said power provisioning system is connected to said external power source, and a standby power source for energising a subset of the components of the apparatus when said main power supply output is not energised, the apparatus further comprising a self contained subsystem including a memory for storing at least one parameter reflecting an internal state of the apparatus, said self contained subsystem being powered by said standby power source and including an encoder for encoding the parameters in an output signal and a transducer for generating a wireless transmission from the output signal, which transmission can be detected in the vicinity of the apparatus, so as to enable
    Type: Grant
    Filed: February 23, 2000
    Date of Patent: December 9, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Eric Owhadi
  • Patent number: 6651190
    Abstract: A remote maintenance device for monitoring and controlling a host computer and its operating system. The device is fully independent of the host computer's hardware and peripherals (including local power, network, and telephony) and fully independent of the host operating system. The remote maintenance device uses a wireless modem (GSM) or wireless IP (packet) interface to provide commands from a remote technician to the remote maintenance device. The wireless communication link also transfers data to a remote technician who can then diagnose problems. The host computer may be reset and the power toggled on and off without affecting the maintenance-device's operation because of an onboard battery. The maintenance devices accesses the host's operating system and BIOS via serial ports, I2C, ethernet, and similar communication connections.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: November 18, 2003
    Inventors: Christian B. Worley, Allan L. Worley
  • Publication number: 20030196141
    Abstract: In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 16, 2003
    Inventor: Mark Shaw
  • Publication number: 20030172319
    Abstract: System for providing distributed group-based protection switching at a network element in a communication network. The communication network includes a plurality of interconnected network elements, and wherein the network element includes first and second card logic coupled to the communication network to transmit and receive network traffic. The system comprises selector logic distributed between the first and second card logic that includes first and second switching engines that have associated activity states that indicate how the network traffic is routed at the network element. The switching engines generate new activity states based on selected fault indicators. A processing system operates to detect fault conditions, generate the selected fault indicators, and receive the new activity states from the switching engines to perform one or more switch reconfigurations at the network element based on the new activity states, and thereby implement the distributed group-based protection switching.
    Type: Application
    Filed: March 11, 2002
    Publication date: September 11, 2003
    Inventors: Kent Ryhorchuk, Eric Allard
  • Publication number: 20030149923
    Abstract: According to the present invention, a semiconductor testing method includes the steps of: permitting an ATE processing unit of a reference ATE (Automatic LSI Test Equipment) to accumulate and form summary data of some of the total amount of manufactured semiconductor devices of one lot; permitting the reference ATE to transmit the formed summary data to a host computer through a communication line; permitting the host computer to store the summary data in a recording unit; permitting a determination unit to read the summary data stored in the recording unit; permitting the determination unit to read a quality control reference value; permitting the determination unit to compare and determine the read summary data and the quality control reference value to determine a test item to be edited; permitting an edit unit to edit a test program including the test item to be edited on the basis of the determination by the determination unit; permitting a transmission/reception unit of the host computer to install the
    Type: Application
    Filed: September 20, 2002
    Publication date: August 7, 2003
    Inventor: Mikio Otaki
  • Patent number: 6601190
    Abstract: A method for servicing computers using diagnostics programs to capture and report comprehensive configuration information to customer service via email.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: July 29, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John E. Meyer, John S. Harsany, Tim J. Lyons, David E. Gorman, Hung K. Dinh
  • Patent number: 6594716
    Abstract: An integrated data storage control system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g., digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. Individual elements may have their outputs and inputs MUXed together such that individual elements can be selectively switched (during testing modes) such that the integrated circuit emulates or behaves in the same or similar manner as one of the prior art components. The present invention may be applied to magnetic hard disk drives (HDDs) or other types of storage devices such as floppy disk controllers, optical disk drives (e.g., CD-ROMs and the like), tape drives, and other data storage devices.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: July 15, 2003
    Assignee: Cirrus Logic, Inc.
    Inventors: Siamack Nemazie, Kaushik Popat, Balaji Virajpet, William R. Foland, Jr., Roger McPherson, Maoxin Wei, Vineet Dujari, Shiang-Jyh Chang
  • Patent number: 6571358
    Abstract: A system for integrated testing of one or more multi-service communications switches including a script execution environment for executing a test script. The script execution environment includes a hardware definition file storing a number of logical hardware device names corresponding to hardware devices used by the test script, including a system under test (SUT) and a number of hardware testing devices. The system further employs a network definition file including a plurality of logical connection names corresponding to connections between the hardware devices in the test environment. These connections in the network definition file are specified in terms of the logical hardware device names defined in the hardware definition file.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: May 27, 2003
    Assignee: Fujitsu Network Communications, Inc.
    Inventors: Mark K. Culotta, Mark F. Childs, Jeffrey L. Wise, Stephen C. Miller
  • Publication number: 20030093734
    Abstract: A system and method for implementing an assertion check in an ATPG scan cell is provided. The assertion check includes an error signal generator within a scan cell that generates an error signal when there is a violation of necessary conditions for testing the integrated circuit using APTG. According to the illustrative embodiment, the scan cell comprises a set-reset flip-flop paired with a latch. The flip-flop is used as a master storage element and the latch is used as a slave storage element to form a scan path. The master flip-flop and the slave latch are connected to form a shift register for shifting test data through the circuit under test. A system clock drives the standard operational mode of the storage elements and a shift clock drives the test mode. An enable clock is used to activate the system clock and switch the scan cell between the standard operational mode and the test mode.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: Sun Microsystems, Inc., Palo Alto, CA
    Inventors: Aiteen Zhang, Joseph Siegel
  • Patent number: 6564339
    Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: May 13, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, David R. Matt
  • Patent number: 6557116
    Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: April 29, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, David R. Matt
  • Patent number: 6553513
    Abstract: Emulation and debug circuitry is provided that can be incorporated into a variety of digital systems. A stop mode of operation is provided in which an associated processor stops processing instructions in response to a debug event. A real-time mode of operation is provided in which the processor stops processing background instructions in response to a debug event, but in which high priority interrupts are still processed. Interrupts are classified and processed accordingly when the processor is stopped by a debug event. While suspended for a debug event, a frame counter keeps track of interrupt debug state if multiple interrupts occur. While running or suspended, the emulation circuitry can jam an instruction into the instruction register of the processor to cause processor resources to be read or written on behalf of the emulation circuitry. Read/write transactions are qualified by an expected frame count to maintain correspondence between test host software and multiple debug/interrupt events.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: April 22, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, David R. Matt
  • Patent number: 6550021
    Abstract: An internet-implemented method of supports a component repair service. The service is rendered for a component of a computer that has an interface for communicating with a web site via the internet. While communicating via the internet, the computer operates under a first operating system that has a protection feature that precludes application-level programming from performing a function to test the component. The method comprises running a first program on the first operating system to cause a display prompt for input control to initiate a test of the component. The method comprises responding to the input control by: exiting from the first operating system and entering a second operating system; running a second program on the second operating system to perform an in situ test of the component to generate a test result; and responding to the test result to store a recorded test result.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: April 15, 2003
    Assignee: Western Digital Ventures, Inc.
    Inventors: Lawrence J. Dalphy, Thomas R. Harbert, David M. Smith
  • Patent number: 6543048
    Abstract: A collection of program instructions capable of executing on a host processor suitable for reading from a memory location of a target processor and suitable for creating a real-time data channel between said host and target processors.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: April 1, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Edward Kuzemchak, Deborah Keil, Leland Szewerenko
  • Patent number: 6539266
    Abstract: A computer system for detecting alteration of programs in which a plurality of check program portions are read from a storage medium which carries computer programs including the check program portions. Each check program portion is executed to detect alteration of at least one other check program portion.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: March 25, 2003
    Assignees: Konami Co., Ltd., Konami Computer Entertainment Tokyo Co., Ltd.
    Inventor: Hirotaka Ishikawa
  • Patent number: 6532500
    Abstract: A first data bus is coupled to communicate information from a subsystem for sensing operating parameters of peripheral components to a computer system. A second data bus is coupled to communicate data between peripheral components and the computer system. A first switch is coupled between the first data bus and the second data bus, the first switch being operable to allow signals from the first data bus to be communicated over the second data bus when operating power to the computer system is powered off. A second switch is coupled between the second data bus and the peripheral components, and the second switch is operable to allow signals from the second data bus to be communicated to the computer system when operating power to the computer system is powered on.
    Type: Grant
    Filed: January 24, 2000
    Date of Patent: March 11, 2003
    Assignee: Dell Products L.P.
    Inventors: Shaojie Li, Truc Nguyen
  • Publication number: 20030033557
    Abstract: This invention provides a semiconductor memory test system in which the test system will not conduct logic comparison for a particular block after a failure is detected in the block. In the test system which tests writing and erasing as a unit of block in the memory under test by using a match function includes a register (61) provided for each memory under test (MUTn) for holding a first failure generated in a particular block at a first control signal (Ca) from a pattern generator (2), establishes a match condition, a pass condition, and a write inhibit condition for the particular block for test cycles after the first failure; and resets the register at a cycle specified by a second control signal (Cb) from the pattern generator to release the match condition, pass condition, and write inhibit condition.
    Type: Application
    Filed: April 1, 2002
    Publication date: February 13, 2003
    Inventor: Tadashi Okazaki
  • Publication number: 20030005362
    Abstract: The present invention includes a system for and a method of a support system which includes an information manager to gather performance information and error condition-related information from a computer product which is sent by the information manager electronically to a support server. The support server, working with an associated database, attempts to solve the underlying error present in the computer product by analyzing the information received, comparing the information to a database containing previously reported error related information and identification of a proposed solution or corrective action from the database. This proposed solution, or corrective action is then sent to the information manager.
    Type: Application
    Filed: June 29, 2001
    Publication date: January 2, 2003
    Inventors: Jennifer J. Miller, Alex Lenart
  • Publication number: 20020178400
    Abstract: A system for testing an application running on a point-of-sale (POS) terminal comprises a host running on a personal computer connected to the POS terminal, and a target running on the POS terminal. The host sends simulated keystrokes, card swipes and the like to the target, which passes these to the application under test. The target can send information to the host regarding the POS terminal status, such as the screen display, so that the host can send the simulated keystrokes, etc., to the target on a need basis. The host can also receive other data and send instructions to the target, e.g. it can obtain available RAM space details, file details and system clock details, and can send instructions to restart the application.
    Type: Application
    Filed: April 10, 2001
    Publication date: November 28, 2002
    Inventor: Kartik Venkataraman
  • Patent number: 6487682
    Abstract: A semiconductor integrated circuit includes a semiconductor chip body, a plurality of input/output cells arranged on a surface of the semiconductor chip body at parts including a peripheral part and a central part the semiconductor chip body, and at least an internal logic circuit provided on the semiconductor chip body. Each of the input/output cells include a pad and a holding circuit coupled to the pad for holding incoming data. A plurality of holding circuits are coupled in series in a test mode to form a scan path circuit. The input/output cell which has the pad for receiving an external test signal in a test mode is arranged at the peripheral part of the semiconductor chip body, and the test data held in the holding circuit of the input/output cell which is arranged at a part other than the peripheral part of the semiconductor chip body is transferred to the internal logic circuit in the test mode.
    Type: Grant
    Filed: September 17, 1992
    Date of Patent: November 26, 2002
    Assignee: Fujitsu Limited
    Inventors: Takeshi Yamamura, Tadahiro Saitoh, Kazuhiro Kobayashi
  • Patent number: 6480972
    Abstract: A data processing system and method are described for permitting a server computer system to perform remote diagnostics on a malfunctioning client computer system coupled to the server computer system utilizing a network. The server computer system transmits a diagnostic command to the malfunctioning client computer system utilizing the network. A network adapter operating as a bus controller for an internal bus within the malfunctioning client computer system executes the diagnostic command. The network adapter transmits a result of the execution of the diagnostic command to the server computer system. In this manner, the diagnostic command is executed within a malfunctioning client computer system by a remote, server computer system.
    Type: Grant
    Filed: February 24, 1999
    Date of Patent: November 12, 2002
    Assignee: International Business Machines Corporation
    Inventors: Daryl Carvis Cromer, Brandon Jon Ellison, Eric Richard Kern, Howard Locker, Randall Scott Springfield, James Peter Ward
  • Patent number: 6467050
    Abstract: A method for controlling a set of services in a cluster computer system. The set of services is registered with a service controller in the cluster computer system. The set of services is monitored for a failure of a service within the set of services. In response to a failure of the service, a failure sequence is initiated. An appropriate start sequence is initiated when the failed service can be restarted.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: October 15, 2002
    Assignee: International Business Machines Corporation
    Inventor: Nam Sang Keung
  • Publication number: 20020133749
    Abstract: A system and method for managing and implementing tests for electronic equipment having a host device having a database containing selectable test options, a remote device to which information from the host device is downloaded, the information including at least one test selection, the remote device being capable of implementing a test protocol corresponding to the test selection by interfacing with and controlling testing equipment. The system optionally allows for the host to contain a database including identifiers for electronic equipment, and for the information to contain an equipment selection. Test results are optionally recorded and analyzed. An alternate embodiment of the system and methods integrates the functions of the host and remote device into a single device, either host or remote, and provides for wired, wireless, or network connection between the device and the testing equipment.
    Type: Application
    Filed: November 20, 2001
    Publication date: September 19, 2002
    Inventors: Michael B. Petersen, Steven T. Robbins
  • Patent number: 6438711
    Abstract: A method for managing a computer system includes initiating a reset of the computer system from a remote location. Diagnostic software on the computer system is downloaded from the remote location.
    Type: Grant
    Filed: July 15, 1998
    Date of Patent: August 20, 2002
    Assignee: Intel Corporation
    Inventor: Robert J. Woodruff
  • Patent number: 6415392
    Abstract: A remote diagnosis system includes a central computer system that receives user data related to a user request and deals with the user request data, and at least one kind of image-forming apparatus connected to the central computer system. Each image-forming apparatus has a user request data input device, through which data related to a user request is optionally input, and a user request data transmitting device that transmits the user request data to the central computer system. A data communication adapter collects the user request data from the at least one kind image forming apparatus and transmits the user request data to the central computer system. An interface interfaces the at least one kind of image-forming apparatus with the data communication adapter, and a public communication network connects the data communication adapter with the central computer system.
    Type: Grant
    Filed: December 7, 1998
    Date of Patent: July 2, 2002
    Assignee: Ricoh Company, Ltd.
    Inventors: Kobun Suzuki, Shin Yamaguchi
  • Patent number: 6415407
    Abstract: A debugging device is provided for use in a system controller chip on a computer motherboard, such as a Pentium-based computer motherboard, to facilitate a debugging procedure on the system controller chip whenever a malfunction occurs to the system controller chip. Consequently, internal signals of the chip are correctly connected to chip leads. Under normal operating conditions of the system controller chip, the debugging device connects the connecting-pad area to the control unit and disconnects the connecting-pad the control unit and connects the connecting-pad area successively in a predetermined sequence to the function blocks, allowing the function blocks to undergo an on-site debugging procedure one by one. The debugging device allows an on-site debugging procedure on the system controller chip in real time, and also allows the system controller chip to undergo a benchmark test to check for the reliability in the overall functionality of the system controller chip.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: July 2, 2002
    Assignee: Via Technologies, Inc.
    Inventor: Nai-Shung Chang
  • Patent number: 6411678
    Abstract: Public or private remote access infrastructures in a communication system are used to facilitate communications between a remote site and a centrally located diagnostic center using only local telephone calls. The diagnostic center as well as one or more remote sites at which monitored equipment is located are coupled to a wide area network (WAN). When data are to be transferred from a remote site to the central diagnostic center, the remote site initiates a local telephone call to a point-of-presence (POP) server on the WAN backbone. This could be an Internet Service Provider (ISP) if the Internet is used, or an intranet if a private network is used. Data are then transferred to the POP server. To complete the transfer, the diagnostic center retrieves the data from the POP server using the public or private wide-area network (the Internet or intranet). The data transfer can be performed either on a scheduled basis, or when an alarm condition is detected at the remote site.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: June 25, 2002
    Assignee: General Electric Company
    Inventors: Harold Woodruff Tomlinson, Jr., Michael James Hartman, Robert James Mitchell, Jr.
  • Patent number: 6374366
    Abstract: An automated method, system and computer readable media for repairing a hard drive of a computer system is provided. The method includes detecting a failure in the hard drive and then resuming work from a backup drive after the failure with the hard drive is detected. The repair of the hard drive includes launching a system diagnose engine that is configured to call on a footprint database to analyze physical and logical drive changes associated with the computer system. The footprint database includes information regarding the physical and logical drive of the computer system before the failure was detected with the hard drive. Then, an initial action that is to be taken in order to repair the hard drive is returned by the system diagnose engine.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: April 16, 2002
    Assignee: Adaptec, Inc.
    Inventor: Guido Maffezzoni
  • Patent number: 6357017
    Abstract: A method, system and computer program product for automated technical support in a computer network having a client machine and at least one server. The method begins by selecting a diagnostic map useful in gathering diagnostic data for evaluating a given technical problem requiring diagnosis and correction. The diagnostic map encapsulates a set of one or more methods that, upon execution, explore the client machine and gather data. The diagnostic map is then executed by a diagnostic engine to generate a data set indicative of a current operating state of the client machine. This data set is forwarded from the client machine to the server for analysis. Based on the analysis performed at the server node, the data gathering process is repeated at the client machine, iteratively, until given information is available to a user of the client machine to correct the given technical problem.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: March 12, 2002
    Assignee: Motive Communications, Inc.
    Inventors: Thomas William Bereiter, Brian Jay Vetter
  • Patent number: 6351825
    Abstract: A changer device according to the present invention includes: a plurality of storage media; a magazine for holding the plurality of storage media; a plurality of drives for reading and writing data to storage media, each of these drive reading and writing data to a storage medium selected from the plurality of storage media; and a media transporting device transporting the selected storage medium to the drive as well as transporting the moved storage medium to the magazine. When a request to write data is issued, the data and parity data are stored in a striped manner on the plurality of storage media at the plurality of drives. If data cannot be read or written to a storage medium at one of the drives, the media transporting device transports an operational storage medium to this drive. Then, using the storage media at the drives, the data on the failed storage medium is reconstructed. This reconstructed data is stored on the operational storage medium.
    Type: Grant
    Filed: October 6, 1998
    Date of Patent: February 26, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Yasunori Kaneda, Tadahiro Teraoka, Takashi Oeda
  • Publication number: 20010054161
    Abstract: A method for managing a computer system includes initiating a reset of the computer system from a remote location. Diagnostic software on the computer system is downloaded from the remote location.
    Type: Application
    Filed: July 15, 1998
    Publication date: December 20, 2001
    Inventor: ROBERT J WOODDRUFF