Of Memory Patents (Class 714/6.1)
  • Publication number: 20140068323
    Abstract: A method for handling media errors during a read operation on a data storage device. The method comprises detecting that a first file and a second file are duplicates, wherein the first file is stored on a first storage device. Metadata is written to the first storage device in association with the first file, wherein the metadata identifies the location of the second file that is a duplicate of the first file. Later, an application program requests a first read operation to read the first file. In response to a media error that results from the first read operation, the method reads the metadata associated with the first file to identify the location of the second file, performs a second read operation to read the second file instead of the first file, and provides the second file to the application program in satisfaction of the requested first read operation.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: International Business Machines Corporation
    Inventors: Gary D. Cudak, Christopher J. Hardee, Randall C. Humes, Adam Roberts
  • Patent number: 8667321
    Abstract: A memory controller including a detection module and a protection module is provided. The memory controller is applicable to a memory having a command transmission port and a data transmission port. The detection module detects whether an error condition occurs in an electronic device associated with the memory. When the error condition is detected, the protection module sends an interrupt command to the memory via the command transmission port to stop an operation associated with the data transmission port.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 4, 2014
    Assignee: MStar Semiconductor, Inc.
    Inventors: Steve Wiyi Yang, Chien-Yi Chen
  • Patent number: 8667323
    Abstract: Processing for file system volume error detection and processing for resultant error correction are separated to support system availability and user satisfaction. File system volumes for storing data structures are proactively scanned while the volumes remain online to search for errors or corruptions thereon. Found errors are scheduled to be corrected, i.e., spot corrected, dependent on the severity of the identified errors, error correction scheduling and/or at the determination of a file system administrator and/or user, to assist in maintaining minimal user and file system impact. When spot correction is initialized, one file system volume at a time is taken offline for correction. Spot correction verifies prior logged corruptions for the offline volume, and if independently verified, attempts to correct the prior noted corruptions. Volumes are retained offline only for the time necessary to verify and attempt to correct prior noted volume corruptions.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: March 4, 2014
    Assignee: Microsoft Corporation
    Inventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Daniel Chan, Craig A. Barkhouse
  • Patent number: 8667322
    Abstract: Technologies are described herein for achieving data consistency during a failover from a primary node to a secondary node in a storage cluster with a shared RAID array in a degraded mode. When the primary storage node receives a write I/O operation, a volume module on the primary node reads the missing data strip data from the failed disk belonging to the stripe targeted by the write I/O operation. The primary storage node communicates the missing data strip to the secondary storage node, which writes the missing strip data to an outstanding strip log. Upon the failure of the primary node, the secondary storage node reads the missing data strip from the outstanding strip log and writes the missing data strip to the shared RAID array, thus restoring data consistency to the stripe of the RAID array containing the missing data strip.
    Type: Grant
    Filed: July 25, 2012
    Date of Patent: March 4, 2014
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Sharon Samuel Enoch, Anandh Mahalingam, Suresh Grandhi
  • Patent number: 8661288
    Abstract: Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 25, 2014
    Assignee: Harman Becker Automotive Systems GmbH
    Inventors: Gerrit Fuchs, Krasnodar Jandrijevic, Juan Medrano
  • Publication number: 20140053015
    Abstract: A data writer is described comprising: a memory to store at least one amount of source data that is to be written to a data storage medium; a processor to arrange the source data into subsets and generate ECC data in respect of each subset, wherein the source data and the associated ECC data are to be written to a data storage medium via a plurality of individual data channels, and wherein the ECC data comprises at least a first degree of ECC protection having a first level of redundancy in respect of a first subset and a second degree of ECC protection having a second level of redundancy in respect of a second subset; a plurality of data writing elements, each to write data from an associated data channel, concurrently with the writing by the other data writing elements of data from respective data channels, to a data storage medium; and a controller, to control the writing by the data writing elements of the source data and the associated ECC data to the data storage medium.
    Type: Application
    Filed: May 19, 2011
    Publication date: February 20, 2014
    Inventors: John D. Hampton, Neil Thomas Hutchon
  • Patent number: 8656213
    Abstract: A method and controller for implementing storage adapter performance optimization with a predefined chain of hardware operations configured to minimize hardware and firmware interactions and a bridge code configured to select a firmware sequence for error recovery to complete the operations responsive to an identified error in the predefined chain, and a design structure on which the subject controller circuit resides are provided. A selected predefined chain is configured to implement a particular performance path to maximize performance. Responsive to an identified predefined error during hardware operations in the predefined hardware chain, a bridge code is configured to select a non-performance path firmware sequence for error recovery completion of remaining operations.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: February 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian E. Bakke, Brian L. Bowles, Michael J. Carnevale, Robert E. Galbraith, II, Adrian C. Gerhard, Murali N. Iyer, Daniel F. Moertl, Mark J. Moran, Gowrisankar Radhakrishnan, Rick A. Weckwerth, Donald J. Ziebarth
  • Patent number: 8650435
    Abstract: Recovery of a failed storage device of a RAID array to a replacement storage device is improved by initiating recovery before failure of the storage device occurs. If failure occurs before completing the transfer of all information from the failed storage device to the replacement storage device, then the RAID controller identifies untransferred information to recreate the failed storage device at the replacement storage device by re-building only the untransferred information with a parity operation using information stored at the array.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 11, 2014
    Assignee: Dell Products L.P.
    Inventors: Murty K. Vishnu, Syam Sreedhar M. Deepu, A. S. Nagendra, Agarwal Sandeep, Kumar Vaibhav
  • Patent number: 8650434
    Abstract: Systems and methods for reading and writing a set of data using a journaling service are provided. The journaling service may be used to identify and record data storage operations associated with one or more shares of data stored in one or more share locations. The journaling service may use logs to record each of the read and write requests to the share locations. In some embodiments, the log may be a queue data structure that stores information associated with failed data storage operations. In some embodiments, the journaling service may leverage both memory and disk storage in order to maintain the journaling queue. In some embodiments, the journaling queue may maintain information associated with the state of each share location. In some embodiments, this information may be used by the journaling service to determine when to monitor and record information regarding data storage operations associated with the share locations.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: February 11, 2014
    Assignee: Security First Corp.
    Inventors: Rick L. Orsini, Mark S. O'Hare
  • Patent number: 8650436
    Abstract: A method is disclosed for recovering data associated with a damaged file stored in a NAND gate array memory. The method includes the steps of: identifying all meta data associated with the damaged file; identifying each logical block address of all identified meta data; collecting all physical block addresses associated with one of the identified logical block addresses or the identified meta data; counting in a replace table (ReplTable) a number of matches to a physical block address of the damaged file for each physical block address of the damaged file; choosing a block in a linked list that corresponds to the physical block address of the block in the linked list; and linking all chosen blocks to form a replicated file.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 11, 2014
    Assignee: The Board of Governors For Higher Education, State of Rhode Island and Providence Plantations
    Inventors: Qing Yang, Weijun Xiao
  • Patent number: 8645749
    Abstract: Systems and methods are disclosed for storing the firmware and other data of a flash memory controller, such as using a RAID configuration across multiple flash memory devices or portions of a single memory device. In various embodiments, the firmware and other data used by a controller, and error correction information, such as parity information for RAID configuration, may be stored across multiple flash memory devices, multiple planes of a multi-plane flash memory device, or across multiple blocks or pages of a single flash memory device. The controller may detect the failure of a memory device or a portion thereof, and reconstruct the firmware and/or other data from the other memory devices or portions thereof.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: February 4, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Cory Reche
  • Patent number: 8645750
    Abstract: A computer system functions to dynamically assign the storage capacity to the host computer. If an event such as a failure occurs in the logical resources, the performance requirements of the virtual volumes must be guaranteed to the host computer. Accordingly, the computer system comprising a storage apparatus, wherein the storage apparatus detects the occurrence of an event in the logical resources, compares the performance of the logical resources where the event occurred with the performance of the virtual volumes and, in accordance with the result of the comparison, sets the correspondence relationship of the virtual volumes to the logical resources.
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: February 4, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Kaneko, Yukinori Sakashita
  • Patent number: 8645758
    Abstract: Embodiments of the invention relate to page faulting of memory operations in a subject code block. An aspect of the invention concerns an apparatus comprising a component for identifying a first object node having a first dependency path and second object node having a second dependency path, and a component for calculating a numerical difference between a first addressing value and a second addressing value, where the first and second addressing values are respectively associated with the first and second dependency paths. The apparatus may include a dependency generator for ordering a subject order list of the subject code block in an object dependency non-page-faulting order when the numerical difference is equal to or less than an assigned memory page size.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventor: Paul Michael Peter Brian Ronald Walker
  • Patent number: 8645796
    Abstract: Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: February 4, 2014
    Assignee: International Business Machines Corporation
    Inventors: Ekaterina M. Ambroladze, Michael Fee, Edward T. Gerchman, Arthur J. O'Neill, Jr.
  • Patent number: 8645754
    Abstract: A method and system of checkpointing single process application groups and multi-process application groups. In an exemplary embodiment, the method may include creating at least one full checkpoint for each application in an application group, and creating at least one incremental application checkpoint for each application in the application group. Further, each of the at least one incremental application checkpoint may be automatically merged against a corresponding full application checkpoint. Further, checkpointing may be synchronized across all applications in the application group. In the exemplary embodiment, each application may use both fork( ) and exec( ) in any combination.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: February 4, 2014
    Assignee: Open Invention Network, LLC
    Inventors: Keith Richard Backensto, Allan Havemose
  • Patent number: 8639968
    Abstract: Systems, methods, and computer-readable and executable instructions are provided for computing system reliability. A method for computing system reliability can include storing, on one of a plurality of devices, a checkpoint of a current state associated with the one of the plurality of devices. The method may further include storing the checkpoint in an erasure-code group across the plurality of devices.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: January 28, 2014
    Assignee: Hewlett-Packard Development Company, L. P.
    Inventors: Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman Paul Jouppi
  • Patent number: 8639969
    Abstract: A storage system comprises a first storage device having a first plurality of hard disk drives and a first controller. The first controller stores data in the first plurality of hard disk drives by stripes. Each stripe includes M data and N parity data allocated to M+N hard disk drives of the first plurality of hard disk drives. A first hard disk drive includes data or parity data of both a first stripe of the stripes and a second stripe of the stripes, while a second hard disk drive includes data or parity data of only one of the first stripe or the second stripe. During data recovery involving failure of one of the first plurality of hard disk drives, the data in the failed hard disk drive is recovered for each stripe by calculation using data and parity data in other hard disk drives for each stripe.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: January 28, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Tomohiro Kawaguchi
  • Publication number: 20140025989
    Abstract: An information processing system includes a first control unit including a first memory configured to store first software, and a first controller configured to perform processing based on the first software and to update the first software in a case where an instruction to update the first software is received, and a second control unit configured to be coupled to the first control unit, the second control unit including a second memory configured to store second software that is the same as the first software, a second controller configured to perform processing based on the second software, and a first power supply circuit configured to start power supply to the second controller in a case where a failure in the first control unit is detected.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: Fujitsu Limited
    Inventor: Ryota TANAKA
  • Patent number: 8635421
    Abstract: Embodiments of the invention relate to data replication and block allocation in a file system to support write transactions. Regions in a cluster file system are defined to support a block allocation. Blocks in the defined regions are allocated to support the data replication. A pipeline manager is provided to schedule population of the blocks in the allocated region(s) based upon network characteristics.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: January 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karan Gupta, Roger L Haskin, Prasenjit Sarkar, Dinesh K. Subhraveti
  • Publication number: 20140019800
    Abstract: An abnormal termination recovery is performed where storage is referenced shortly after the storage has been freed. More specifically, when storage is freed, and that storage is accessed, an abnormal termination error (e.g., a page translation exception event) occurs due to referencing storage that has not been obtained. When the abnormal termination error occurs, an abnormal termination recovery operation is accessed. The abnormal termination recovery operation scans a history of storage freeing operations (e.g., FREEMAIN operations) to determine whether the storage location accessed by the storage access that caused the abnormal termination error was recently freed from within the same address space. If the storage location was recently freed, then the abnormal termination recovery operation reverses the storage freeing operation by issuing a storage obtaining operation (e.g., a GETMAIN operation) to re-obtain the storage.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 16, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derek L. Erdmann, Dustin A. Helak, David C. Reed, Max D. Smith
  • Patent number: 8631303
    Abstract: A distributed storage network generates a plurality of data segments from a data object and stores each of the plurality of data segments as a plurality of encoded data slices generated from an error encoding dispersal function. When the distributed storage network receives a modification request for the data object, it determines a size of the plurality of data segments of the data object from a segment size field and identifies one of the plurality of data segments requiring modification. The identified data segment is reconstructed from the plurality of encoded data slices and modified in accordance with the modification request.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: January 14, 2014
    Assignee: Cleversafe, Inc.
    Inventors: Jason K. Resch, Bart Cilfone
  • Patent number: 8631271
    Abstract: Providing heterogeneous recovery in a redundant memory system that includes a memory controller, a plurality of memory channels in communication with the memory controller, an error detection code mechanism configured for detecting a failing memory channel, and an error recovery mechanism. The error recovery mechanism is configured for receiving notification of the failing memory channel, for performing a recovery operation on the failing memory channel while other memory channels are performing normal system operations, for bringing the recovered channel back into operational mode with the other memory channels for store operations, for continuing to mark the recovered channel to guard against stale data, for removing any stale data after the recovery operation is complete, and for removing the mark on the recovered channel to allow the normal system operations with all of the memory channels, the removing in response to the removing any stale data being complete.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kevin C. Gower, Lisa C. Gower, Luis A. Lastras-Montano, Patrick J. Meaney, Vesselina K. Papazova, Eldee Stephens
  • Patent number: 8626842
    Abstract: A content transaction management server device includes: a memory storing decryption keys used in decryption of encrypted content data; a communication unit for information; a payment-request reception unit receiving, through the communication unit, a first storage address indicating a storage area where the decryption keys of encrypted content data in the memory are stored and user identifiers identifying users who are purchasers of the encrypted content data; a payment-procedure processing unit implementing payment-procedure processes related to purchase transactions of encrypted content data by a user identified by user identifiers in the payment request; and a decryption-key transmission unit that, after payment-procedure processing based on the payment-procedure processing unit is completed, reads out, from the memory, decryption keys stored in the storage area indicated by the first storage address included in the payment request and transmits, through the communication unit, the decryption keys to the
    Type: Grant
    Filed: February 7, 2008
    Date of Patent: January 7, 2014
    Assignee: NTT DoCoMo, Inc.
    Inventors: Yasushi Onda, Izua Kano, Dai Kamiya, Yusuke Kushida, Keiichi Murakami, Eiju Yamada, Kazuhiro Yamada
  • Patent number: 8627024
    Abstract: Embodiments of the invention relate to data replication and block allocation in a file system to support write transactions. Regions in a cluster file system are defined to support a block allocation. Blocks in the defined regions are allocated to support the data replication. A pipeline manager is provided to schedule population of the blocks in the allocated region(s) based upon network characteristics.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Karan Gupta, Roger L Haskin, Prasenjit Sarkar, Dinesh K. Subhraveti
  • Patent number: 8627139
    Abstract: A method, a recording terminal, a server, and a system for repairing media file recording errors are disclosed in embodiments of the present invention. The method includes: generating description information about a recording error when a recording terminal identifies the recording error in live recording of a media file; sending a recording error repair request that carries the description information to a network device; and repairing the media file recorded by the recording terminal according to repair information when receiving the repair information sent by the network device according to the description information. With the present invention, the recording errors are repaired through a bidirectional network between the recording terminal and the network device, and reliability of repairing the recording errors is ensured.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: January 7, 2014
    Assignee: Huawei Device Co., Ltd.
    Inventor: Yunsong Fan
  • Publication number: 20140006847
    Abstract: Defect management logic extends a useful life of a memory system. For example, as discussed herein, failure detection logic detects occurrence of a failure in a memory system. Defect management logic determines a type of the failure such as whether the failure is an infant mortality type failure or a late-life type of failure. Depending on the type of failure, the defect management logic performs different operations to extend the useful life of the memory system. For example, for early life failures, the defect management logic can retire a portion of the block including the failure. For late life failures, due to excessive reads/writes, the defect management logic can convert the failing block from operating in a first bit-per-cell storage density mode to operating in a second bit-per-cell storage density mode.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Xin Guo, Yogesh B. Wakchaure, Kiran Pangal, Hiroyuki Sanda
  • Patent number: 8621270
    Abstract: A redundant array of independent nodes are networked together. Each node executes an instance of an application that provides object-based storage. The nodes are grouped into a plurality of systems each having multiple nodes. An object recovery method comprises: receiving, by a first system of the plurality of systems from a client application, a read request for an object, the object having been replicated to/from at least one second system among the plurality of systems; if the object of the read request is available in the first system, returning by the first system the object of the read request to the client application; and if the object of the read request is not available in the first system, performing a read from replica process by the first system to access a replica of the object from a second system among the plurality of systems and using the replica of the object to return the object of the read request to the client application.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: December 31, 2013
    Assignee: Hitachi Data Systems Corporation
    Inventors: Benjamin Isherwood, Donald P. Pannese, Richard Rogers, Vitaly Zolutusky
  • Patent number: 8621266
    Abstract: A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block.
    Type: Grant
    Filed: July 23, 2010
    Date of Patent: December 31, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang chul Kang, Seung hyun Han
  • Patent number: 8621264
    Abstract: Provided is a backup line allocation apparatus that determines which fail lines, in a memory provided with a plurality of backup lines, to allocate the backup lines to, comprising a bit counting section that, for each fail bit contained in each fail line, counts a number of orthogonal fail bits, which is a number of fail bits in a fail line that includes the each fail bit and has an orientation that differs from the orientation of the each fail line, and stores the number of orthogonal fail bits associated with the each fail bit; a weight calculating section that calculates a weighting coefficient for each fail line based on the number of orthogonal fail bits of the fail bits contained in the each fail line, and stores the weighting of the each fail line; and an allocating section that determines which of the fail lines to allocate the backup lines to, based on the relative sizes of the weighting coefficients calculated by the weight calculating section.
    Type: Grant
    Filed: January 25, 2010
    Date of Patent: December 31, 2013
    Assignee: Advantest Corporation
    Inventor: Toshiro Fujii
  • Patent number: 8621177
    Abstract: In a memory with block management system, program failure in a block during a time-critical memory operation is handled by continuing the programming operation in a breakout block. Later, at a less critical time, the data recorded in the failed block prior to the interruption is transferred to another block, which could also be the breakout block. The failed block can then be discarded. In this way, when a defective block is encountered during programming, it can be handled without loss of data and without exceeding a specified time limit by having to transfer the stored data in the defective block on the spot. This error handling is especially critical for a garbage collection operation so that the entire operation need not be repeated on a fresh block during a critical time. Subsequently, at an opportune time, the data from the defective block can be salvaged by relocation to another block.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: December 31, 2013
    Assignee: Sandisk Corporation
    Inventor: Sergey Anatolievich Gorobets
  • Patent number: 8621265
    Abstract: A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to store a data result from a processing module and determines whether to store the data result in an error encoded format. When the memory controller determines to store the data result in the error encoded format, it facilitates encoding the data result in accordance with a dispersed storage error coding function to produce one or more sets of encoded data slices. The memory controller then determines where to store the one or more sets of encoded data slices and provides the one or more sets of encoded data slices to one or more identified memories for storage.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 31, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8621269
    Abstract: A method begins by a processing module sending list digest requests to a set of dispersed storage (DS) units. The method continues with the processing module receiving list digest responses from at least some of the set of DS units and determining whether an inconsistency exists between first and second list digest responses of the list digest responses. The method continues with the processing module requesting at least a portion of each of the slice name information lists from first and second DS units of the set of DS units and identifying a slice name information error associated with the inconsistency based on the at least a portion of each of the slices name information lists of the first and second DS units when the inconsistency exists between first and second list digest responses of the list digest responses.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: December 31, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Sebastien Vas, Zachary J. Mark
  • Patent number: 8621276
    Abstract: Perceived corruptions encountered on file system volumes, and which cannot be initially remedied online, are processed to verify whether they are true, existing volume data structure corruptions or, alternatively, false positives. Upon the verification of one or more of a volume's corruptions, error scanning is performed to check for, and attempt to remedy online, all the existing corruptions on the volume. Subsequent to error scanning processing, if one or more verified corruptions continue to exist on a file system volume, at file system boot up time spot corruption correction is performed to attempt to remedy the existing, verified corruptions on the volume. Spot corruption correction is performed to attempt to correct verified data structure corruptions on a volume of the file system while the volume is maintained offline for the time necessary to attempt to correct its prior identified corruptions.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 31, 2013
    Assignee: Microsoft Corporation
    Inventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Daniel Chan, Craig A. Barkhouse, Lane Haury, Kiran Kumar G. Bangalore, Thiago Sigrist
  • Patent number: 8615688
    Abstract: A memory system includes an array of memory cells and a repair module. Multiple memory cells in the array are redundant to other memory cells in the array. The repair module iteratively tests the array. During the iterative testing of the array, the repair module, during each test of the array, (i) identifies one or more defective memory cells in the array, if any, and (ii) in response to one or more defective memory cells being identified during the test, respectively replaces the one or more defective memory cells with one or more memory cells that are redundant to other memory cells in the array. The repair module performs the iterative testing of the array until (i) the repair module does not detect a defective memory cell or (ii) no memory cells of the memory cells that are redundant remain available for replacement of a defective memory cell.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: December 24, 2013
    Assignee: Marvell Israel (M.I.S.L) Ltd.
    Inventors: Reshef Bar Yoel, Yosef Solt, Michael Levi, Yosef Haviv
  • Patent number: 8615678
    Abstract: A method, computer program product, and storage network system for detecting a failure of a highly-available, volatile, solid state cache memory system included within a storage network. The highly-available, volatile, solid state cache memory system includes cache data. The cache data is replicated onto a non-volatile, solid-state, cache memory system included within the storage network. At least one data request concerning the highly-available, volatile, solid state cache memory system is redirected to the non-volatile, solid-state, cache memory system.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: December 24, 2013
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, David W. DesRoches
  • Patent number: 8612796
    Abstract: A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 17, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 8612680
    Abstract: A system, computer program product, and computer-implemented method for defining a data stripe that spans one or more of N data storage devices and one or more of M erasure code devices. The one or more N data storage devices and the one or more M erasure code devices are included within a data storage system. A data chunk to be written to the data storage system is received. At least a portion of the data chunk is written to the portion of the data stripe that spans the one or more N data storage devices. Each of the N data storage devices and the M erasure code devices is included within a unique server computer.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 17, 2013
    Assignee: EMC Corporation
    Inventors: Kiran Madnani, Randall H. Shain, David W. DesRoches
  • Patent number: 8612797
    Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: December 17, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Larry J. Thayer, Andrew C. Walton, Mike H. Cogdill, George Krejci
  • Publication number: 20130332768
    Abstract: A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected.
    Type: Application
    Filed: June 6, 2012
    Publication date: December 12, 2013
    Applicant: HITACHI, LTD.
    Inventors: Tsutomu Koga, Koji Washiya
  • Patent number: 8607121
    Abstract: Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: December 10, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Patent number: 8607099
    Abstract: Data structure errors, or corruptions, identified during, e.g., normal computing device system processing, file system processing or user access processing, are verified prior to the file system identifying the error for offline correction or notifying the user or system administrator a data structure error exists. Identified data structure corruptions are verified while the file system volumes are maintained online and otherwise accessible to other processing tasks and user access. Verified data structure corruptions are logged for further corrective processing. Data structure corruptions that cannot be verified, i.e., false positives, are not further processed and are not identified to file system administrators or users as corruptions, freeing the file system to concentrate on normal processing and true, verifiable errors.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: December 10, 2013
    Assignee: Microsoft Corporation
    Inventors: Sarosh C. Havewala, Neal R. Christiansen, John D. Slingwine, Craig A. Barkhouse, Daniel Chan
  • Patent number: 8601227
    Abstract: A method includes determining an amount of memory space in a memory device available for memory mirroring. The method further includes presenting the available memory space to an operating system. The method further includes selecting at least a portion of the amount of memory space to be used for memory mirroring with the operating system. The method further includes adding a non-selected portion of the available memory to memory space available to the operating system during operation. An associated system and machine readable medium are also disclosed.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: December 3, 2013
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, John V. Lovelace, Larry D. Aaron, Jr., Sugumar Govindarajan
  • Patent number: 8601310
    Abstract: In one embodiment, an apparatus includes memory comprising a first portion in which data contained therein is mirrored and a second portion wherein data contained therein is not mirrored, a memory allocator for allocating the first portion of the memory to critical data and allocating the second portion of the memory to non-critical data, and a processor for mirroring the critical data and receiving an indication of a memory error. If the memory error occurs in the first portion of the memory, a mirrored copy of the critical data is used. If the memory error occurs in the second portion of the memory, the memory error is contained so that the apparatus can continue to operate programs using the memory not affected by the memory error.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 3, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Roland Dreier
  • Patent number: 8595566
    Abstract: Data storage services are provided for clients for backup of data objects from the clients. A data object is sent to a first location in a first storage device. A determination is made if the data object was successfully stored at the first location, and if so, meta data corresponding with the data object is stored, wherein the meta data includes first path information on a first data path of the data object to the first location. The data object is migrated from the first location to a second location in a second storage device. A determination is made if the data object was successfully stored at the second location, and if so, second path information on a second data path of the data object is added to the second location to the meta data corresponding with the data object, to update the meta data.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Colin S. Dawson, Glen Hattrup, Howard N. Martin, David M. Morton
  • Patent number: 8595549
    Abstract: Information system, including: first and second storage apparatuses connected to a host computer and including volumes designated by a common volume identifier, but being accessible via differing paths of differing priorities. A failure detection storage apparatus connected to the storage apparatuses includes a third volume. Any I/O request designating the common volume identifier, is first sent to the first volume though the first access path, but upon error is then sent to the second volume thorough the second access path. The first or second storage apparatus detecting failure stores, in the third volume, a failure information flag. Upon receiving an I/O request through the second access path, the second storage apparatus determines whether the failure information flag is stored in the third volume, and sends an error reply of the I/O request to the host computer if the failure information flag is stored in the third volume.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 26, 2013
    Assignee: Hitachi, Ltd.
    Inventor: Kenta Ninose
  • Patent number: 8589737
    Abstract: A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.
    Type: Grant
    Filed: June 20, 2008
    Date of Patent: November 19, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Rohleder, Gary Hay, Stephan Mueller, Manfred Thanner
  • Patent number: 8589730
    Abstract: Systems and methods are provided for handling errors during device bootup from a non-volatile memory (“NVM”). A NVM interface of an electronic device can be configured to detect errors and maintain an error log in volatile memory while the device is being booted up. Once device bootup has completed, a NVM driver of the electronic device can be configured to correct the detected errors using the error log. For example, the electronic device can move data to more reliable blocks and/or retire blocks that are close to failure, thereby improving overall device reliability.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: November 19, 2013
    Assignee: Apple Inc.
    Inventors: Matthew Byom, Kenneth Herman, Nir J. Wakrat, Daniel J. Post
  • Patent number: 8589725
    Abstract: According to one embodiment, a disk storage apparatus includes a write module, an operation module, and a controller. The write module is configured to write data, in units of blocks, in a designated write area of a disk. The operation module is configured to perform an exclusive OR operation on the blocks of data. The controller is configured to control the write module, causing the write module to write, in a designated block, recovery data that is a result of the exclusive OR operation on all data blocks written in the designated write area.
    Type: Grant
    Filed: January 13, 2011
    Date of Patent: November 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Takada, Kenji Yoshida
  • Patent number: 8583968
    Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: November 12, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takami Sugita, Hiroyuki Moro, Takahiro Nango
  • Patent number: 8583959
    Abstract: Parameters of a complementary metal-oxide semiconductor (CMOS) and an associated system time of a server are stored in a field-replaceable unit (FRU) of a baseboard management controller (BMC) of the server. If an error occurs and the CMOS is selected recovering from the BMC, the system time is selected from the FRU. The BMC reads the parameters from the FRU corresponding to the selected system time and sets the CMOS according to the read parameters.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: November 12, 2013
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventor: Shuang Peng