Abstract: A method for transmitting a data block in a wireless communication system and a transmitter are provided. The transmitter transmits the data block to a receiver and generates a retransmission block for the retransmission of the data block if it is determined that the transmission fails. The transmitter determines whether the channel access is performed according to a transmit time of the retransmission block.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device comprises a memory cell array, a write control circuit, a latch circuit, an address control circuit, a scan control circuit, and an address latch circuit. The write control circuit executes write and verify for each page of the memory cell array. The latch circuit holds data of the verify result. The address control circuit divides the page into zones and sequentially selects the address of each of the zones. The scan control circuit executes scan so as to count the number of fail bits in zone selected by the address control circuit and determine whether the number of fail bits is not more than the number of allowable bits. The address latch circuit holds the address of a no fail zone, out of the plurality of zones, in which the number of fail bits is 0.

Abstract: A method for detecting validity of downlink control information in telecommunication user equipment and a decoder and baseband receiver to perform the method are provided. The object of avoiding falsely detecting payload data and misinterpreting them is achieved by reverse encoding a bit output sequence of a Viterbi decoder; determining hard bits from a soft-bit input sequence of the decoder; determining a bit count of real received bits; comparing the reverse encoded bit stream to the determined hard bit stream and counting the number of mismatches to obtain an error count; comparing a bit error rate which is defined as a quotient of the error count and the bit count against a predefined threshold value; and rejecting the payload as invalid if said bit error rate is above said threshold value, even if a cyclic redundancy check of the payload gives a correct result.

Abstract: A method of receiving data. A plurality of data signals and clocking signals are received over a source synchronous communication channel. The plurality of data signals is strobed with the clocking signal at a plurality of coarse time offset delays (e.g., time offset delays spanning over a data bit period). The plurality of error rates associated with the strobing at the plurality of coarse time offset delays is determined. Strobing design of a transmitting component (e.g., edge-strobed, center-strobed, etc.) may be determined based on the plurality of error rates. The error rates of the plurality of data signals strobed with a plurality of time offset delays close to the determined strobing design of the transmitting component is calculated. A time offset delay is selected based on the error rates. The plurality of data signals can be strobed with the selected time offset delay to recover the transmitted data signals.

Abstract: System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Abstract: In a method and a device for determining a physical quantity from a number of measured values containing errors, grouping of the number of measured values containing errors into a plurality of subgroups of measured values is executed, wherein each subgroup includes a redundancy, so that more measured values than the number of measured quantities are contained in each subgroup. Hereupon, a reliability quantity for each subgroup is calculated based on the redundancy contained in the subgroup. Further, individual evidence is allocated to the measured values containing errors of each subgroup based on the reliability quantity for the respective subgroups. An evidence determiner determines one overall evidence each for each measured value containing errors based on the individual evidence quantities for a respective measured value. Hereupon, a processor calculates the physical quantity using at least some of the measured values containing errors and at least some of the overall evidences.

Abstract: An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

Abstract: A system and method for encoding information arriving from a host in order to store the coded information in flash memory, the method comprising encoding information arriving from a host for storage at a flash memory location including generating a number of redundancy bytes, the encoding proceeding at an encoding rate which is a function of the number of redundancy bytes generated, the encoding including determining an effective error rate, including an anticipated rate of expected reading errors, for the flash memory location; and selecting the encoding rate as a function of the effective error rate such that the number of redundancy bytes is sufficient to overcome the anticipated rate of expected reading errors with a predetermined degree of certainty.

Abstract: A method for predicting performance of a radio link in a wireless communication terminal including hypothesizing a second codeword including information associated with a hypothesized first codeword, obtaining channel state information from a received signal, and estimating a decoder error rate of the first codeword under a condition that the second codeword may not be decoded correctly, wherein the decoder error rate is estimated using the channel state information.

Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.

Abstract: A computer implemented method for efficiently allocating resources for an enterprise server system through a proportional integral derivative scheme is provided. The method includes defining a set point parameter for a resource being allocated and defining a proportional gain parameter, a proportional integral (PI) gain parameter and a proportional integral derivative (PID) gain parameter in terms of the proportional gain parameter. The method further includes calculating an initial maximum allocation for the resource based on a product of the proportional gain parameter with a difference of an initial operating parameter and the set point parameter and adjusting the initial operating parameter to the initial maximum allocation. A next allocation of the resource is calculated based on a product of the proportional gain parameter with the difference of an initial operating parameter and the set point parameter and a difference of the set point with a current operating parameter.

Abstract: A method of testing a processing includes performing a test of at least one logic block of a processor of a data processing system; receiving an interrupt; stopping the performing the test for the processor to respond to the interrupt, wherein the stopping the performing the test includes storing test data of the test to a memory prior to the processor responding to the interrupt; and after the processor responds to the interrupt, resuming performing the test, wherein the resuming performing the test includes retrieving the test data from the memory and using the retrieved test data for the resuming performing the test.

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract: According to an aspect of the embodiment, a signal transmission apparatus includes a sine wave output unit that outputs a sine wave to a transmission path, network analyzers and that analyze signals on the transmission path, an S parameter measurement unit that measures S parameters based on the analysis, a selection unit that selects a plurality of combinations of an amplitude, an emphasis characteristic, and an equalization characteristic based on the S parameters, measurement units that measure a BER or an eye opening of the transmission path for the plurality of combinations, and a setting unit that extracts single combination based on the measurement and that sets the amplitude, the emphasis characteristic, and the equalization characteristic to a transmission unit and a reception unit.

Abstract: A computer readable non-transitory medium storing a design aiding program causes a computer to execute a process of determining worst-case corner candidates for each of a plurality of condition sets. The design aiding program causes the computer to execute a process of mapping the worst-case corner candidates that are within an allowable range. The design aiding program causes a computer to execute a process of determining the worst-case corner candidates that minimize the number of the worst-case corner candidates mapped to the condition sets by handling the worst-case corner candidates thus mapped as a single worst-case corner candidate to be worst-case corners.

Abstract: Various embodiments of the present invention provide systems and methods for data processing.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.

Abstract: A time error estimating device for estimating a sampling time error of each of a plurality of sampling circuits when the sampling circuits generates a plurality of sampling output signals by performing sampling at timings shifted from one another has correlators each configured to obtain a correlation value representing a similarity between the sampling output signals, and a weight adder configured to estimate the sampling time error of the sampling circuits, based on a result obtained by adjusting a weight on the correlation value.

Abstract: An apparatus includes a communication device and an evaluation unit, wherein the communication device can be linked to a communication bus and can receive secure telegrams by way of the communication bus, and wherein a secure telegram includes user data and CRC data in each instance. In at least one embodiment, in order to improve the communication within the secure bus system, the evaluation unit can determine an error rate from received secure telegrams by way of a CRC check and if a threshold value of the error rate stored in the evaluation unit is exceeded, can effect a secure state of the apparatus.

Abstract: An interface with universal serial communication comprises a switching device, a medium device, and a data restoring device for transmitting the data and obtaining the serial communication via one signal line that is inter-strung by afore devices. By simplifying such communication device, the compatibility thereof could be enhanced. Moreover, during the data transmission, computation made by an error coefficient and an error beyond value in the switching device allows the transmitted data to be kept within an acceptable noise value, so that the accuracy of the data could be assured.

Abstract: A voice processing apparatus includes: an error detector which detects an error in a frame containing voice data; a correction value calculator which determines a level of the error detected by the error detector and calculates a correction value according to the level; and a voice data corrector which corrects the voice data by using the correction value calculated by the correction value calculator.

Abstract: The present invention provides a method for generating random jitter test patterns by generating a sequence of maximum-size asynchronous packets according to the P1394b standard and transmitting the sequence to the device under test. The present invention provides a method for generating jitter test patterns by disabling the transmitter data scrambler of the second device; clearing the port_error register of the device under test; and sending a test pattern to said device under test. The present invention provides for a method for generating supply noise test patterns comprising: transmitting a test pattern to the DUT comprising a maximum length asynchronous packet containing alternate 0016 and FF16 bytes.

Abstract: A data storage and replay device uses measurements of the evolution of performance of the storage medium (typically a flash memory circuit) to predict an error rate of retrieval from a region of the storage medium. The prediction is used as a basis for dynamically selecting an ECC for encoding the data prior to storage of the data. The ECC is selected from a plurality of available ECC's so that a fastest encodable ECC is selected that is predicted to produce no more than a predetermined post-decoding error rate given the information. On decoding the data, which is typically audio or video data, is decoded and replayed at a predetermined speed. In another embodiment, the data stored using a plurality of ECC's together and an ECC is selected dynamically for decoding, so that an output data rate can be maximized or power consumption on replay can be minimized.

Abstract: A method for enhancing verification efficiency regarding error handling mechanism of a controller of a Flash memory includes: providing an error generation module, for generating errors; and triggering the error generation module to actively generate errors of at least one specific type in order to increase an error rate corresponding to the specific type. An associated memory device and the controller thereof are provided, where the controller includes: a ROM arranged to store a program code; a microprocessor arranged to execute the program code to control access to the Flash memory and manage a plurality of blocks, and further enhance the verification efficiency regarding error handling mechanism of the controller; and an error generation module arranged to generate errors. The controller that executes the program code by utilizing the microprocessor triggers the error generation module to actively generate errors of at least one specific type to increase an error rate.

Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.

Abstract: Systems and methods are disclosed for improving throughput in a wireless system utilizing Hybrid Automatic Repeat Request (HARQ) retransmission. In general, prior to a HARQ-enabled transmission, one or more channel conditions for a corresponding transmit channel are obtained. Based on the one or more channel conditions, a set of target block error rates for the HARQ-enabled transmission are determined. In one embodiment, the set of target block error rates maximize throughput for the transmit channel utilizing HARQ retransmission. In another embodiment, the set of target block error rates optimize throughput and one or more additional parameters for the transmit channel utilizing HARQ retransmission.

Abstract: According to one embodiment, an information recording apparatus for recording, in a free area, first low-quality recorded data having an error rate not less than a first error rate upon finalization of a recording medium, the information recording apparatus includes a reader, a measurement module, a detector, and a recorder. The reader is configured to read recorded data from a recording area of the recording medium. The measurement module is configured to measure an error rate of the recorded data of each predetermined data block. The detector configured to detect the first low-quality recorded data based on an error rate measurement result of the measurement module. The recorder is configured to correct an error in the first low-quality recorded data, and record error-corrected recorded data corresponding to the first low-quality recorded data at a spare recording position of the free area of the recording medium.

Abstract: A method for selecting an audio data source for a multimedia device includes detecting an error state of audio data for generating a detection result, wherein the audio data is generated by a digital source of the multimedia device, generating an initial counting value, generating a counting result according to the detection result and the initial counting value, confining the counting result within a boundary for generating a limit result, and comparing the limit result with a threshold for generating a comparison result, for selecting the audio data source of the multimedia device.

Abstract: Adaptive error resilience for streaming video transmission over a network is provided. In one embodiment, a method of transmitting a plurality of packets comprises generating a first proactive repair redundancy information for a first data packet; adding the first proactive repair redundancy information to a second data packet; generating a second proactive repair redundancy information for the first data packet; adding the second proactive repair redundancy information to a repair packet; and transmitting the plurality of packets, wherein the plurality of packets includes the first data packet and at least one of the second data packet and the repair packet.

Abstract: Devices and methods for monitoring a bit error rate of an intra-panel data link (e.g., a chip-on-glass (COG) data link) between a timing controller and a display driver are provided. For example, an electronic display according to an embodiment may include a timing controller and display driver circuitry. The timing controller may send test data over a data link to the display driver circuitry. The test data may include a known or predictable stream of data. The display driver circuitry may receive the test data via the data link and detect bit errors based at least partly on the test data. An indication of the bit errors may be displayed on an array of pixels of the display or provided to the timing controller via a separate back channel data link.

Abstract: Embodiments of the present invention provide systems, methods, and computer-readable media for modifying frame error rates associated with a mobile device. In embodiments, a mobile device is assigned an initial frame error rate. In response to determining the initial frame error rate does not match a desired frame error rate, a frame error rate modification request is generated. The frame error rate modification request is transmitted to a base station. At the base station, a modified frame error rate that matches the desired frame error rate is associated with the mobile device.

Abstract: Scheduler 304 performs scheduling such that the communication terminal apparatuses to transmit packets to are determined according to the order in CIR information output from demodulator 303, and determines the modulation schemes and coding rates of the packets. Command detector 305 detects an ARQ command transmitted from the communication terminal apparatus determined in scheduler 304, outputs an ACK/NACK signals to buffer 306, and outputs a SUSUPEND signal or a GIVEUP signal to scheduler 304. Scheduler 304 stops retransmission upon receiving a SUSPEND signal or a GIVEUP signal from command detector 305, and redoes the scheduling. Thus, it is possible to improve overall system throughput in a wireless communication system that performs packet transmission.

Abstract: A soft error correction method is for a memory system having memory access controllers accessing memories for storing byte-sliced data in cycle synchronism, and a system controller receiving a memory access from an arbitrary one of MPUs and issuing a memory address to the memory access controllers. When a correctable error is detected in data read from one memory, an error address where the error was detected is held within a memory access controller, and an error notification is made to the system controller from the memory access controller. In response to the error notification, the memory access controller holds the error address from the system controller without intervention from the MPUs, and reads, corrects and rewrites the data to the error address.

Abstract: Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison.

Abstract: Consistent with the present disclosure, circuitry may be provided in an optical receiver that can determine a bit error rate (BER) associated with an incoming signal by dividing the number of errored bits in a frame alignment signals (FAS) by the number of bits in the FAS. Accordingly, although an optical signal may be severely degraded and forward error correction (FEC) cannot be performed, a BER may be obtained if the FAS can be identified. The BER can then be used in a feedback loop to control various optical or electrical components in the receiver to improve or reduce the BER to a level, for example, at which FEC can be performed.

Abstract: Provided are systems and methods for adaptive, error-tolerant pattern recognition in the transmission of digital data packets, in which an actual data pattern, including several bits, is detected and is compared with a theoretical data pattern; erroneous and/or correctly recognized bits are detected; erroneous and/or correctly recognized bits are added up (in each case); and the error sum (number of the errors) of the added-up erroneous bits is compared with a specifiable and changeable admissible maximum number of errors.

Abstract: A plurality of processing cores, are central storage unit having at least memory connected in a daisy chain manner, forming a daisy chain ring layout on an integrated chip. At least one of the plurality of processing cores places trace data on the daisy chain connection for transmitting the trace data to the central storage unit, and the central storage unit detects the trace data and stores the trace data in the memory co-located in with the central storage unit.

Abstract: A method according to one embodiment includes gathering information about monitor data from a plurality of memory devices having finite endurance and/or retention, the monitor data being (i) data of known content stored in dedicated memory cells of known write cycle count, and (ii) write protected for preventing the monitor data from being overwritten with user data; analyzing the monitor data information; and taking an action relating to at least one of the devices based on the analyzing. Additional systems, methods, and computer program products are also disclosed.

Abstract: Detection of faults in a transmitted signal stream occurs by recovering, from the information stream, a water mark embedded in the stream prior to transmission. The embedded watermark has data characteristic of stream quality. Thereafter, the at least one watermark property is analyzed to detect faults in the received information stream.

Abstract: An event data transmission scheme is provided for reducing positron emission tomography event losses. The event data transmission scheme employs a more effective use of available data bandwidth. Each of a plurality of detector data slots is connected directly to a data aggregation control interface, and the control interface is connected to a coincidence processor.

Abstract: An error correction code includes a separate error code portion for each of two or more separate burst erasure durations (or burst error durations). For each burst erasure duration, the code can be employed to recover from the burst erasure with a different delay time. Each error code portion has a particular parameter for burst duration (B) and delay (T), meaning that the code can be used to recover from a burst erasure of duration B with delay T. Each error code portion is based on separating the source symbols into sub-symbols and diagonally interleaving the sub-symbols based on the (B,T) parameters for the error code portion. Accordingly, different burst erasures are recovered from with different delays.

Abstract: A PHY abstraction mapping between the link level and system level performance is presented based on mapping between the mean RBIR (Received Bit Information Rate) of the transmitted symbols and their received LLR values after symbol-level ML detection in SISO/MIMO wireless systems, such as WiMAX. In MIMO antenna configuration, the mapping is presented for both vertical and horizontal encoding. An embodiment of this invention provides the PER/BLER prediction in the actual system, enabling the system to use more aggressive methods to improve the system performance.

Abstract: Implementations of the present principles include methods and systems for retransmitting un-recovered information within a cognitive radio, anti-jamming system. In accordance with aspects of the present principles, encoding schemes may be optimized for retransmission by utilizing a jamming rate and a number of un-recovered packets to minimize packet loss and thereby enhance throughput. In addition, rateless encoding features may be employed to re-encode un-recovered portions of an information sequence for efficient retransmission.

Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Abstract: A method and an apparatus for testing the physical layer of high speed serial communication devices and systems with protocol awareness is disclosed. The apparatus comprises of two major blocks: a General Purpose Platform (GPP) and an Analog Front End (AFE). Physical layer testing is divided into two sets of testing procedures: Receiver and Transmitter testing. This test system can be used in a traditional BERT setting where the test system commands the Device Under Test (DUT) to be placed into either a loop back mode, or into a more advanced mode where the test system is communicating with the DUT on a protocol level and counts the frame error ratio (FER). This FER is protocol dependent and each protocol receiver has its own way of reporting transmission errors to the transmitter. The protocol awareness of this invention is capable of detecting such a level of errors.

Abstract: A method and system for packet transmission in a hybrid automatic repeat request (ARQ) system. A modulation and a block length for a transmission are determined based on the average mutual information per bit. The average mutual information per bit is computed based on a current channel signal-to-noise ratio and a plurality of previous transmissions, each being transmitted with a respective coded block length, modulation form, and signal-to-noise ratio. A block error rate is computed for the potential block lengths and modulations based on the average mutual information per bit, and a throughput of the current transmission is determined based on the block error rate. The modulation form and the block length of the transmission are determined based on an analysis of the throughput. If the receiver cannot decode the current transmission, the transmitter repeats the computation to determine the modulation and the block length for retransmission.

Abstract: Systems, apparatus, methods, and manufactures for performing link adaptation in a communications system are described. The methods may employ an error rate table that has a channel condition value dimension and a transmission parameter dimension. The elements of the error rate table include expected error rates for data transmitted at various channel conditions according to various transmission parameters. Also, the various transmission parameters may each be associated with a data transmission rate. For a given channel condition value, the methods may determine expected throughputs for each of the transmission parameters according to the associated expected error rates and data transmission rates. A transmission parameter may be selected according to the expected throughputs.

Abstract: Provided is a method and system for calculating a bivariate Gaussian Q function using a univariate Gaussian Q function to thereby analyze an error probability of a communication system. A method of calculating an error probability of a communication system may include: receiving encoded communication information from another communication system; restoring information desired to be transmitted by another user by decoding the encoded communication system; and calculating the error probability by analyzing the restored information using a bivariate Gaussian Q function, the error probability indicating a probability that the restored information is different from the information desired to be transmitted by the other user. The calculating may include calculating the bivariate Gaussian Q function using a univariate Gaussian Q function.

Abstract: A data transmission method and apparatus encodes data to be transmitted over a wireless network on a unit basis, and provides the transmission data with information for allowing the transmission data to recover from an error being added thereto, transmits the transmission data to the wireless network, calculates a transfer success ratio depending on whether the transmission data have been successfully transmitted, and controls the transmission of the transmission data depending on whether the transfer success ratio is higher than a threshold value.

Abstract: A method is provided for quantizing an input signal. The number of equal quantized values during a period of time is counted thereby obtaining said number of counts. The counts exceeding a count threshold being defined as reliable counts, the counts lower than or equal to the count threshold being defined as unreliable counts. Two unreliable counts are calculated using a lower and a higher value for a first parameter in an extrapolating function. The first parameter is considered equivalent to the lower value if the two unreliable counts differ less than or equal to a count difference. The invention further discloses a corresponding tail extrapolator.