Abstract: In an interactive broadcasting system, television programming may be broadcast with interleaved web content information. The progress in broadcasting the web content information over one or more transports and over one or more channels within those transports, may be monitored to provide a time based indication of what content has been broadcast. In one embodiment, markers may be inserted into the data transmission flow and a method may be utilized to associate a handle with a particular marker. A method may be called which obtains the handle and another method may be utilized to invoke the handle to obtain current information about broadcast transmissions. This information may be used within a broadcast encoder or may be provided to a content provider, for example, through a log-in server.

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not.

Abstract: An Error Control Code (ECC) apparatus may include a control signal generator that generates an ECC control signal based on channel information. The ECC apparatus also may include: a plurality of ECC encoding controllers that output data respectively inputted via storage elements corresponding to the ECC control signal; and/or an encoding unit that encodes, using a plurality of data outputted from the plurality of ECC encoding controllers, encoding input data into a number of subdata corresponding to the ECC control signal. In addition or in the alternative, the ECC apparatus may include: a plurality of ECC decoding controllers that output data respectively inputted via the storage elements corresponding to the ECC control signal; and/or a decoding unit that decodes, using a plurality of data outputted from the plurality of ECC decoding controllers, a number of decoding input data corresponding to the ECC control signal into one piece of output data.

Abstract: A regenerative relay method includes the steps of: i) calculating an error rate of a transmission path between the first half apparatus and a main apparatus; ii) calculating an error rate of a transmission path between the main apparatus and the latter apparatus; iii) adding the error rates; iv) selecting the error correction code and data before the error is corrected in the main apparatus so as to be supplied to the latter apparatus if the added error rates are lower than a designated error correction threshold; and v) selecting data after the error is corrected in the main apparatus and the other error correction code generated from the data so as to be supplied to the latter apparatus if the added error rates are higher than the designated error correction threshold.

Abstract: A network system for judging abnormality of a self node with high precision on the basis of information from other nodes connected to a network is provided. In each node, a frequency at which data frames to be transmitted/received among nodes cannot be received is counted every communication partner node by a reception time-out error count unit. After some node is reset and restored, a start-up signal is transmitted with an initial data frame by a start-up signal transmitting unit of the node concerned. In the other nodes receiving the start-up signal, a count result of the transmission destination node of the start-up signal by a reception time-out error count unit is returned by the monitoring result returning unit, and upon reception of the count result, the node which transmits the start-up signal makes a self-diagnosis by a self-diagnosing unit.

Abstract: Embodiments of the invention provide methods and systems for improving the reliability of data stored on disk media. Logical redundancy is introduced into the data, and the data within a logical storage unit is divided into sectors that are spatially separated by interleaving them with sectors of other logical storage units. The logical redundancy and spatial separation reduce or minimize the effects of localized damage to the storage disk, such as the damage caused by a scratch or fingerprint. Thus, the data is stored on the disk in a layout that improves the likelihood that the data can be recovered despite the presence of an error that prevents one sector from being read correctly.

Abstract: A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

Abstract: The illustrative embodiments provide a computer implemented method and an apparatus for correcting data errors. An error correction unit receives data from a register. Responsive to receiving the data from the register, the error correction unit determines whether an error is present in the data. Responsive to identifying the error in the data, the error correction unit corrects the data to form corrected data. Responsive to correcting the error in the data, the error correction unit notifies a counter in the register to update.

Abstract: The DC offset of a differential signal can be changed by differentially shifting the DC offset of each of its signals. Techniques are presented for changing, in a controlled way, the DC offset of a differential signal as received by a receiver of a data transmission system. Several classes of example embodiments, utilizing digitally controllable voltage or current sources, are presented. The classes differ based upon such factors as coupling capacitor arrangement and use of termination resistors. Specific embodiments, within each class, differ based upon such factors as whether voltage or current sources are used and the characteristics of such sources. Once the DC offset of a differential signal has been changed, the effect of such change on a performance metric can be measured. Example applications include the ability to determine a differential signal level that results in BER having a particular level and determination of differential signal margin.

Abstract: Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.

Abstract: A receive test accelerator retrieves an adjusted jitter amount and an adjusted test time in which to test a device. The adjusted jitter amount and the adjusted test time correspond to an adjusted bit error rate that is extrapolated from a baseline bit error rate, which corresponds to a baseline jitter amount. In turn, the receive test accelerator tests the device, at the adjusted test time, using a data stream that is modulated by the adjusted jitter amount.

Abstract: A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a global error-counter, coupled to the OLT, for counting FEC-correctable errors, for each ONU, from a data stream from the GPON; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on the errors from the global error-counter. A system, for identifying faults in a GPON that includes an OLT and a plurality of ONUs, including: a grant-start error-counter, coupled to the OLT, for counting grant-start errors, for each ONU, from a data stream from the GPON; a grant-end error-counter, coupled to the OLT, for counting grant-end errors for each ONU; and a CPU for extracting an ONU status, indicative of a faulty ONU, contingent on a parameter selected from the group consisting of the grant-start errors, the grant-end errors, and a combination thereof.

Abstract: Provided is a deterministic component model determining apparatus that determines a type of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; a theoretical value calculating section that calculates a theoretical value of a spectrum for each of a plurality of predetermined types of deterministic components, based on the null frequency; a measured value calculating section that calculates a measured value of the spectrum for the deterministic component included in the probability density function, based on the standard deviation and the spectrum; and a model determining section that determines the type of the deterministic component included in the probability density function

Abstract: Disclosed is a method and apparatus for calibrating a time vernier in an automatic test equipment (ATE) system, the method including generating a data signal and a reference signal whose periods differ by a small amount (dt), using precession of the data signal and reference signal to create accurate delay increments, and creating a trigger signal for Bit Error Rate Test (BERT) counting, the trigger signal having a select frequency such than an integer number (N) of triggers are generated with a precession period (TPREC). Upon occurrence of each trigger, a BERT is initiated for measuring data to determine strobe positions with respect to the data signal.

Abstract: In a method of determining an iteration value for an iterative decoding process of a hard disk drive, a bit error rate (BER) of a digital signal is measured in multiple iterations. A difference is calculated between BERs of consecutive iterations, and the calculated differences are compared with a reference value. An adjusted iteration value is then determined based on the comparison.

Abstract: A method for maintaining reliable communication on a bidirectional communication link is provided. A receiver on the bidirectional communication link detects an error and maintains a count of detected errors. The transmitter on the bidirectional communication link polls the receiver in order to determine the count of detected errors, and performs a downshift evaluation for the bidirectional communication link. In response to performing the downshift evaluation for the bidirectional communication link, the transmitter maintains a transmission speed of the bidirectional communication link if the downshift evaluation determines that forgoing transmission speed downshift is required for the bidirectional communication link, and reduces the transmission speed of the path if the downshift evaluation determines that transmission speed downshift is required for the bidirectional communication link.

Abstract: A data slicer includes an error bit predictor, a DC level compensator, a co-channel detector, and an output device. The data slicer generates four bytes according to four slicing levels respectively. The four slicing levels are a DC level, a level generated by adding a predetermined offset to the DC level, a level generated by subtracting the predetermined offset from the DC level, and a compensated level generated by the DC level compensator. The co-channel detector determines if the compensated level has the co-channel interference. The output device generates an output byte according to indication signals generated by the co-channel detector and the error bit predictor and the parity check of the four bytes.

Abstract: The present specification describes techniques and apparatus that adjust filter tap values to be used in filtering a data value input to a detector and/or that increase or decrease a threshold value used to determine whether to adjust the filter tap values.

Abstract: A degree of conformity of error distribution of a digital signal to the Poisson distribution is quantitatively determined. The digital signal including error data, which is randomly generated at a predetermined error rate, is divided into data number of measurement units, wherein the data number is determined on the basis of the error rate. A sample number of the measurement units are acquired from the measurement units, and the number of errors contained in each measurement unit is measured as a measurement value. Further, the number of times of occurrence of each measurement value is calculated, a Poisson distribution function is calculated, and a degree of a bond between the Poisson distribution and the distribution of the number of times of occurrence is determined by using the chi-square goodness-of-fit test method.

Abstract: A system for processing errors in a processor comprising, an error counter, a pass counter, and a processing portion operative to determine whether a first error is active, increment an error counter responsive to determining that the first error is active, increment the pass counter responsive to determining that all errors have been checked, and clear the error counter responsive to determining that the pass counter is greater than or equal to a pass count threshold value.

Abstract: In random defect yield simulation, a specific defect size interacts with a specific physical design and has a calculated probability of failure associated with it. The failure model is in terms of probability of failure. It provides a solution to the random defect yield simulation problem of chips with a built-in redundancy scheme. The solution first defines the independent failure modes of the chip with a built-in redundancy scheme and efficiently models each mode. Then, it may accumulate the respective probability of failures according to the chip's architecture.

Abstract: Disclosed herein are systems, methods, and computer readable-media for detecting and identifying network faults. The method includes recording cyclic redundancy check (CRC) errors gathered by a data stream analyzer, if the number of CRC errors exceeds a threshold, sending a notification to an automated fault manager which (1) analyzes the number of CRC errors, (2) determines a cause of the CRC errors, and (3) takes appropriate corrective action based on the analysis. The method can further include storing CRC error measurements in a log organized by date and time, analyzing stored CRC error measurements to anticipate future CRC errors, and taking preventive action in advance of anticipated future CRC errors. The automated fault manager can be a rule-based fault/performance management system. The notification can be a Simple Network Management Protocol (SNMP) trap. The data stream analyzer can be an MPEG transport stream analyzer.

Abstract: A method of testing a proximity communication system for voltage margin by impressing a voltage upon the data link between the transmitter on one chip and the receiver on the other chip coupled to the transmitter through a capacitively coupling circuit formed by juxtaposed capacitor pads on the respective two chips. The impressed voltage is varied and the output of the receiver is monitored to determine an operational voltage margin. The floating inputs on the receiver may be continuously biased by connecting them to variable biasing supply voltages through high impedances. When the floating inputs are periodically refreshed to a refresh voltage during a quiescent data period, the refresh voltage is varied between successive refresh cycles. The variable test voltage may be applied to transmitter output when it is in a high-impedance state, and the output of the receiver is measured.

Abstract: An error rate sensitive error correction (ERSEC) system that applies a level of error correction that is inversely related to susceptibility to error as indicated by a signal-to-noise ratio (SNR) profile of a channel. The SNR profile is estimated, detected or retrieved from an external source. The ERSEC system is used with a channel for which the SNRs vary spatially, temporally or both.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: The disclosure proposes bit-error-rate (BER) and symbol-error-rate (SER) estimation techniques and its application to incremental-redundancy and rate-adaptation for modern-coded hybrid-ARQ systems. In particular, BER/SER estimators are proposed based on iterative refinement of mixture-density modeling of the bit/symbol decision metrics. For hybrid-ARQ systems, rate-adaptation functions are proposed based on BER/SER estimators for failed transmissions. Methods are disclosed for code-rate selection based on successfully decoded blocks as well as incremental parity size selection for retransmission of failed blocks Techniques disclosed here apply to forward-error-correction codes employed for digital data communication systems.

Abstract: Described embodiments provide for end-of-life (EOL) checking for NAND flash devices. An exemplary implementation of a computing environment comprises at least one NAND data storage device operative to store one or more data elements. In the illustrative implementation, the EOL data processing and storage management paradigm allows for the storage of data according using a selected EOL enforcement algorithm that can utilize current and/or historical correction levels. The NAND data storage EOL checking module can be operable to cooperate with one or more NAND data store components to execute one or more selected EOL operations to protect stored data.

Abstract: Systems and methods are described for managing bit errors present in a series of encoded bits representative of a portion of an audio signal, wherein the series of encoded bits is received over a communication link in an audio communications system. At least one characteristic of a portion of a received modulated carrier signal that is demodulated to produce the series of encoded bits is determined. A number of bit errors present in the series of encoded bits is then determined based on the at least one characteristic. Based on the estimated number of bit errors, one of a plurality of methods for producing a series of digital audio samples representative of the portion of the audio signal is selectively performed. The series of digital audio samples produced by the selected method is then converted into a form suitable for playback to a user.

Abstract: A calculating apparatus that calculates a characteristic of a target signal, including an input section that receives a bit error or a sampling timing, and a calculating section that calculates sampling timings over a range in which the bit error rate is less than a designated value or a bit error rate at a designated sampling timing, by using a relational expression between the sampling timing and the bit error rate. A transmission model for transmitting a signal having jitter includes a random component and a deterministic component having a prescribed probability density distribution. The relational expression is achieved by substituting, as parameters, a standard deviation of a random component and a peak-to-peak value of a deterministic component in a jitter of the target signal.

Abstract: Various read level control apparatuses and methods are provided. In various embodiments, the read level control apparatuses may include an error control code (ECC) decoding unit for ECC decoding data read from a storage unit, and a monitoring unit for monitoring a bit error rate (BER) based on the ECC decoded data and the read data. The apparatus may additionally include an error determination unit for determining an error rate of the read data based on the monitored BER, and a level control unit for controlling a read level of the storage unit based on the error rate.

Abstract: An approach is provided for bit error rate characterization. A test signal representing one or more Ethernet frames exhibiting a particular bit error rate is generated. The test signal is output to a device under test. Traffic is received from the device under test. A determination is made as to whether a link failure condition exists at a port on an Ethernet switch.

Abstract: A system that includes a first flip flop that is serially coupled to a second flip flop. The first flip flop includes a transfer circuit that is coupled between a master latch and a slave latch. The master latch of the first flip flop latches a scan data signal during a first portion of a cycle of a first clock signal that is provided to the first flip flop. The transfer circuit is conductive during a sub-portion of a second portion of the cycle of the first clock signal. The sub-portion starts after an occurrence of a predefined change in a control signal provided to the slave latch. The predefined change occurs after an estimated start of a first portion of a cycle of a second clock signal that is provided to the second flip flop. A master latch of the second flip flop latches the scan data signal during a first portion of a next cycle of the second clock signal.

Abstract: A method of measuring a state of a plurality of channels is provided. The method includes transmitting to a second device test signal information needed to transmit/receive a test signal for measuring the state of the plurality of channels; receiving an information received response from the second device, indicating that the second device has received the test signal; if the information received response is received, transmitting the test signal to the second device, using the test signal information, via the plurality of channels; and receiving from the second device the state information regarding the plurality of channels which has been measured by using the test signal.

Abstract: A memory controller includes a page configure module that communicates with a memory array comprising B memory blocks each including P pages. The page configure module selectively configures memory cells in the P pages of each of the B memory blocks to store from 1 to T bits per cell. The page configure module also generates a memory map based on the configuration. B, P, and T are integers greater than 1. At least one of a write module selectively writes data to the memory array based on the memory map or a read module selectively reads data from the memory array based on the memory map.

Abstract: This disclosure is related to systems and methods for low wear operation of solid state memory, such as a flash memory. In one example, a controller is coupled to a memory and adapted to dynamically adjust programming thresholds over the course of usage of the data storage device such that a signal-to-noise ratio from reading data stored in the data storage cells is no less than a minimum amount needed to recover the data using an enhanced error detection capability.

Abstract: A method for testing a storage apparatus, which includes: (a) writing a specific pattern to a storage unit of a storage apparatus; (b) reading the specific pattern written to the storage apparatus; (c) determining an error bit number of the specific pattern read in the step (b); and (d) determining that the storage unit has defect when the error bit number is larger than a error bit threshold value, wherein the error bit threshold value is smaller than a correctable bit number for a error correction code corresponding to the specific pattern.

Abstract: A system for estimating bit error rates (BER) may include using a normalization factor that scales a BER to substantially normalize a Q-scale for a distribution under analysis. A normalization factor may be selected, for example, to provide a best linear fit for both right and left sides of a cumulative distribution function (CDF). In some examples, the normalized Q-scale algorithm may identify means and probabilistic amplitude(s) of Gaussian jitter contributors in the dominant extreme behavior on both sides of the distribution. For such contributors, means may be obtained from intercepts of both sides of the CDF(Qnorm(BER) with the Q(BER)=0 axis, standard deviations (sigmas) may be obtained from reciprocals of slopes of best linear fits, and amplitudes may be obtained directly from the normalization factors. In an illustrative example, a normalized Q-scale algorithm may be used to accurately predict bit error rates for sampled repeating or non-repeating data patterns.

Abstract: An object of the invention is to provide a wireless communication apparatus which can correct error flexibly without wasting consumed resources while maintaining the improvement of reliability resulted from error correction.

Abstract: A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate.

Abstract: In a communication device, a multi-carrier signal with at least one group of signal carriers is received from a communication connection. For each of the signal carriers, at least one individual error value is evaluated or generated. From the individual error values, a combined error value is evaluated or generated. The combined error value is transmitted on a backchannel of the communication connection.

Abstract: A communication system includes a transceiver capable of receiving a data burst as part of a paging block and a processing logic capable of comparing at least part of the data burst to a plurality of permutations of the data burst to locate a matching permutation. The processing logic determines a bit error rate (BER) in accordance with a difference between the data burst and the matching permutation. The processing logic uses the BER to operate the communication system.

Abstract: A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.

Abstract: A method of monitoring network performance is disclosed and includes receiving a session initiation protocol (SIP) response message from one of a plurality of serving-call session control function (S-CSCF) systems at a centralized error monitoring server of an Internet Protocol (IP) Multimedia Subsystem (IMS). The SIP response message includes at least one error code that matches an error monitoring initial filter criterion included in a subscriber profile. The method also includes sending an alert message to a fault management system of the IMS when at least one threshold related to SIP error codes is met or exceeded based on the at least one error code.

Abstract: A server apparatus controls an FC card ? so as to access a disk array apparatus A. The FC card ? obtains response information sent from the disk array apparatus A in accordance with the present access. If the response information is a predefined specific access error in this event, the server apparatus controls the FC card ? so as to change the address of the present access to that of a disk array apparatus B that is different from the sender of the present response information, and then access the present post-change address.

Abstract: A particular device includes a transmitter. The transmitter is adapted to estimate a packet erasure rate for packets of a data window to be transmitted to a receiver. The transmitter is adapted to determine a number of proactive forward error control (FEC) packets for the data window based on the estimated packet erasure rate. The transmitter is adapted to determine a packet size for the packets in the data window based on a window size of the data window and the determined number of proactive FEC packets. The transmitter is also adapted to transmit the data window to the receiver. The packets in the transmitted data window have a size corresponding to the determined packet size and include the determined number of proactive FEC packets.

Abstract: A system and method for improving the linkage and security of records is provided. Generally, the present invention can be viewed as providing methods for selecting an ideal identifier, from a series of test identifiers, for linking more than one associated record. In this regard, one embodiment of such a method, among others, can be broadly summarized by the following steps: accessing several parameters for each test identifier; determining if an error rate of the test identifier is an improved error rate over an error rate of an existing identifier; determining if the test identifier reduces linkage error; and selecting the test identifier as the ideal identifier if the test identifier has a lower overall error rate, as determined by the steps of determining if an error rate of the test identifier is an improved error rate over an error rate of an existing identifier and determining if the test identifier reduces linkage error, compared to other test identifiers.

Abstract: This disclosure relates generally to low power data decoding, and more particularly to low power iterative decoders for data encoded with a low-density parity check (LDPC) encoder. Systems and methods are disclosed in which a low-power syndrome check may be performed in the first iteration or part of the first iteration during the process of decoding a LDPC code in an LDPC decoder. Systems and methods are also disclosed in which a control over the precision of messages sent or received and/or a change in the scaling of these messages may be implemented in the LDPC decoder. The low-power techniques described herein may reduce power consumption without a substantial decrease in performance of the applications that make use of LDPC codes or the devices that make use of low-power LDPC decoders.

Abstract: A method for storing data in a memory, which includes a plurality of analog memory cells, includes defining programming levels that represent respective combinations of at least first and second bits and are represented by respective nominal storage values. The data is stored by mapping the data to storage values selected from among the nominal storage values and writing the storage values to the memory cells. A condition is defined over two or more bit-specific error rates applicable respectively to at least the first and second bits. The bit-specific error rates include a first bit-specific error rate computed over the data stored by the first bits and a second bit-specific error rate computed, separately from the first bit-specific error rate, over the data stored by the second bits. The nominal storage values are set based on the bit-specific error rates so as to meet the condition.

Abstract: Various embodiments of the invention provide methods and systems for automated quality management and/or monitoring of organization operations, including for example data processing operations. In one aspect of the invention, a quality management system uses an error rate measurement module to automatically monitor the quality of an organizational operation. Information is processed by the organizational operation. The error rate measurement module samples the processed information. It also automatically determines, without human intervention, an error rate based on the sampled information. The error rate accounts for both a frequency of errors and an operational impact of errors.

Abstract: A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configured to hold preprogrammed data read from an area of the cell array; and a judging circuit configured to compare and check the program data with the preprogrammed data, and judge whether there are one or more disagreement bits therebetween or not.