Abstract: A method of decoding channel outputs using an iterative decoder to provide hard decisions on information bits includes activating each SISO decoder of the iterative decoder to provide soft-decisions associated with the information bits. The method also includes computing a fidelity estimate and stopping decoding based on the fidelity estimate.

Abstract: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.

Abstract: A receiving apparatus is disclosed which includes: an amplification section configured to amplify a received signal including a digital broadcast signal; a mixing section configured to mix the received signal amplified by the amplification section with a selective frequency signal so as to acquire an intermediate frequency signal; a demodulation section configured to demodulate the intermediate frequency signal acquired by the mixing section so as to acquire a demodulated signal of the digital broadcast signal; and a control section configured to control the amplification factor of the amplification section in a manner bringing to a target level the signal level of the intermediate frequency signal acquired by the mixing section, the control section being further configured to set variably the target level in accordance with bit error status of the demodulated signal acquired by the demodulation section from the digital broadcast signal.

Abstract: A blanking primitive masking circuit has a detection and handling circuit that receives data containing blanking primitives. The detection and handling circuit generates a dynamic blanking signal when blanking primitives are detected. The received data is delayed and provided to a pattern detector that generates a synchronization signal provided to a memory and a phase sync signal provided to the detection and handling circuit and to a comparator. The comparator receives reference data from the memory, the delayed data, and the dynamic blanking signal. The comparator compares the reference data with the delayed data and generates bit error outputs from mismatched reference data bits and delayed data bits when the dynamic blanking signal from the detection and handling circuit is absent and suppressing the generation bit error outputs when the blanking primitive are in the delay data and the dynamic blanking signal is present.

Abstract: A system including a summer, a comparator, a zero-crossing module, and a control module. The summer is configured to (i) receive a data input signal, and (ii) generate an equalized signal in response to the data input signal. The comparator is configured to generate a recovered data signal in response to the equalized signal. The zero-crossing module is configured to generate a zero-crossing signal in response to the equalized signal. The control module is configured to generate eye information in response to i) the recovered data signal and ii) the zero-crossing signal. The eye information includes characteristic data associated with the recovered data signal, and the characteristic data when plotted provides an eye diagram.

Abstract: In a method of determining an iteration value for an iterative decoding process of a hard disk drive, a bit error rate (BER) of a digital signal is measured in multiple iterations. A difference is calculated between BERs of consecutive iterations, and the calculated differences are compared with a reference value. An adjusted iteration value is then determined based on the comparison.

Abstract: An apparatus and a method for transmitting and receiving a signal in a communication system are provided. The method includes checking a type of the signal to be transmitted; determining a number of puncture bits according to the type of the signal; and puncturing an encoded signal to be transmitted according to the number of puncture bits.

Abstract: A system and method is disclosed for testing a communication device. In accordance with the described invention, a single vector signal generator (VSG) is utilized to test manufactured 2x2, 3x2 and 4x2 MIMO wireless devices to identify possible manufacturing defects that may impair or disable the device under test (DUT) receivers from properly receiving constituted MIMO TX signals and accurately decoding the bits/symbols conveyed by transmitted TX signals. Disclosed embodiments may include a VSG coupled to a DUT. The VSG being configured to transmit data packets as a first codeword and a second codeword, wherein the VSG includes software and hardware architecture to manipulate the first codeword and the second codeword as emulated first and second waveforms, wherein the first waveform is different than the second waveform. The DUT being configured to receive the emulated first and second waveforms as prescribed signals from the VSG.

Abstract: A non-volatile memory chip having SLC blocks acting as a write cache for MLC blocks for high density storage requires constant copying or folding of SLC blocks into MLC blocks. To avoid the time-consuming toggling out and in of the pages of the entire SLC block for ECC checking by a controller chip, only a small sample is checked. An optimal read point for reading the memory cells in the sample of the SLC block is dynamically determined by trying different read points so that the data is read within an error budget. Once the optimal read point is determined, it is used to read the entire SLC block without further error checking. Then the SLC block can be copied (blind folded) to the MLC block with the confidence of being within the error budget.

Abstract: A method and a module for estimating a plurality of relative channel-error for at least one signal with respect to a reference signal. The signals and are produced by an analog-to-digital module including parallel and time interleaved analog-to-digital converters and are received by an estimation module. The method is performed by the estimation module and includes defining a function representing a relationship between the reference signal and an arbitrary signal in the group of signals, selecting a first reference signal in the group of signals, selecting a second signal from the remaining signals in the group, optimizing the function so as to obtain an estimate of the plurality of relative channel-error, and repeating the selecting a second signal and optimizing the function for each remaining signal.

Abstract: An image processing apparatus of the present disclosure includes: a two-dimensional matrix barcode decoding unit configured to decode a two-dimensional matrix barcode in an image of image data; and a restoration determining unit configured (a) to obtain an error detection rate and error detection position information detected while the two-dimensional matrix barcode is decoded, (b) to compare the error detection rate with a predetermined threshold value, (c) on the basis of the comparison result, to determine whether the two-dimensional matrix barcode should be restored, and (d) to adjust the threshold value according to an error detection position determined from the error detection position information.

Abstract: A first module calculates a failure occurrence risk index of each data storage area address. A second module calculates a power saving index of each data storage area address. A third module calculates an access speed index per unit data volume necessary to access each data storage area address. A fourth module generates a distribution table that represents the failure occurrence risk index, the power saving index, and the access speed index for each candidate address, with respect to data to be distributed. A fifth module selects a candidate address in the distribution table such that the power saving index and the access speed index meet restricting conditions and the failure occurrence risk index is minimized, and distributes the data to the candidate address.

Abstract: A two-dimensional self-RAID method of protecting page-based storage data in a MLC multiple-level-cell flash memory device. The protection scheme includes reserving one parity sector across each data page, reserving one parity page as the column parity, selecting a specific number of pages to form a parity group, writing into the parity page a group parity value for data stored in the pages of the parity group. The parity sector represents applying a RAID technique in a first dimension. The group parity represents applying a RAID technique in a second dimension. Data protection is achieved because a corrupted data sector can likely be recovered by the two dimensional RAID data.

Abstract: A method and device for adjusting communications power are used for detecting a communications condition between a connection port and a connection target, and a communications-supporting power of the connection port that includes at least one of a transmitting power and a receiving power is adjusted according to a detected communications condition. Therefore, accuracy of data transmission and reception is ensured, and power used for data transmission and reception is reduced.

Abstract: An information processing apparatus includes a first parity production section for producing a first error detection code for detecting an error of data. A second parity production section produces a second error detection code for detecting an error of the data from the first error detection code. A first parity checking section detects an error of the retained data as a first error using the retained first error detection code. A second parity checking section detects an error of the retained data as a second error using the retained second error detection code. A control amount outputting section outputs, when an occurrence rate of a first error is equal to or lower than a first threshold value, a control amount for controlling a power supply voltage or a frequency using a second threshold value as a target value for an occurrence rate of a second error.

Abstract: A memory device (e.g., a flash memory device) includes power efficient codeword error analysis circuitry. The circuitry analyzes codewords stored in the memory of the memory device to locate and correct errors in the codewords before the codewords are communicated to a host device that requests the codewords from the memory device. The circuitry includes a highly parallel configuration with reduced complexity (e.g., reduced gate count) that a controller may cause to perform the error analysis under most circumstances. The circuitry also includes an analysis section of greater complexity with a less parallel configuration that the controller may cause to perform the error analysis less frequently. Because the more complex analysis section runs less frequently, the error analysis circuitry may provide significant power consumption savings in comparison to prior designs for error analysis circuitry.

Abstract: A method for initiating a refresh operation of a solid-state nonvolatile memory device coupled to a processor is disclosed. The method comprises determining an error number for a block of the solid-state nonvolatile memory. The error number corresponds to an amount of error bits in a page of the block having a greatest amount of error bits. The method further comprises comparing the error number with an error threshold and determining a reset number indicating an amount of times that the processor has been reset since a previous refresh operation was performed on the block of the solid-state nonvolatile memory. The method further includes comparing the number of resets with a reset threshold and refreshing the block of the solid-state nonvolatile memory when the number of errors exceeds the error threshold and the number of resets exceeds the reset threshold.

Abstract: A method for managing a flash storage device includes initiating a read request and reading requested data from a first storage block of a plurality of storage blocks in the flash storage device based on the read request. The method further includes incrementing a read count for the first storage block and moving the data in the first storage block to an available storage block of the plurality of storage blocks when the read count reaches a first threshold value.

Abstract: A method of deriving an indicator of the signal quality in an in-service packet-based network at least having means to detect errors in packets and means to determine the overall amount of network traffic received. The method comprises the steps of: obtaining a value of the number of packets received having errors therein; obtaining a value of the overall amount of the network traffic received; calculating the indicator of signal quality (eBER) using the ratio of the number of packets received having errors therein to the overall amount of network traffic received.

Abstract: A method of data classification for use in a wireless communication system includes obtaining decoder metrics from a decoder. The decoder metrics correspond to data generated by the decoder. The decoder metrics include a symbol error rate (SER) and an energy metric (EM). The method also includes classifying the data into a first category if the data fails a cyclic redundancy check (CRC) check, into a second category if the data passes the CRC check and is determined to be unreliable, or into a third category if the data passes the CRC check and is determined to be reliable. A reliability of the data is determined based on the decoder metrics and an EM threshold.

Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Abstract: A clock signal is received at a clock node of a latch module, and a data signal is received at a data node of the latch module. The data signal including information to be latched at a first latch of the latch module and at a second latch of the latch module. A first representation of the data signal to a first data node of the first latch is delayed relative to a second representation of the data signal to a corresponding first data node of the second latch to obtain a first timing requirement between the data signal and the clock signal relative to the first latch that is substantially different than a second timing requirement. An error signal is generated in response to different data being latched at the first latch than at the second latch.

Abstract: Embodiments of the present invention include computer-implemented methods for selectively applying remedial actions, according to a predefined order, for reducing the error rate in a computer memory system. In one embodiment, an ordered set of remedial actions are sequentially invoked in response to a single-bit error (SBE) in a DIMM reaching successive error thresholds. For example, in an air-cooled system, the remedial actions may include dynamically increasing a DIMM refresh rate, dynamically increasing a rate of airflow used to cool the DIMMs, and dynamically throttling the DIMMs. The remedial actions may be layered as they are successively invoked, to provide a cumulative remedial effect. At least two of the remedial actions may be simultaneously invoked in response to a multi-bit error rate reaching an associated threshold.

Abstract: A method for performing a program operation in a non-volatile memory device includes applying a programming pulse to a plurality of memory cells, verifying whether the plurality of the memory cells are programmed to produce a verification result, determining whether all of the plurality of the memory cells are programmed in response to the verification result to produce a first determination result and determining whether at least a first number of memory cells are programmed among the plurality of the memory cells in response to the first determination result to produce a second determination result.

Abstract: A data access apparatus includes: a flash memory controller; a mirror means; and a flash memory including at least one data region and at least one mirror region. The mirror means copies data to form mirror data to the mirror region when the flash controller writes the data into the data region. The flash memory controller reads the mirror data to replace the data if the flash memory controller determines that the data include error(s) while the data are being read.

Abstract: One embodiment of the present invention relates to a method of detecting potential performance degradation caused by neighboring identical scrambling codes. The method includes detecting an existence of identical scrambling codes in received signals from different cell at the user equipment, and selectively eliminating one or more signals from consideration in processing of received signals based upon the detection. The invention also includes a receiver configured to detect potential performance degradation caused by neighboring identical scrambling codes. The receiver includes a detection component configured to detect an existence of identical scrambling codes in received signals from different base stations at the user equipment, and an elimination component configured to selectively eliminate one or more signals from consideration in processing of received signals based upon the detection by the detection component.

Abstract: Systems and methods for determining whether or not one or pluralities of events, patterns, or data elements present within a given digital data stream should be delimited as anomalous. The system requires analyzes the data elements of the data stream using any acceptable user-specified, preset, or automatically determined analysis system. The results of the data processing, which are stored in a data storage structure such as a synaptic web or a data array for example, reveal synaptic paths (patterns) of characteristic algorithm values that function to individually define or delimit the selected data element(s) from the remainder of the original data stream.

Abstract: A wireless communication apparatus performs data communication with a base station using a plurality of transport channels (TRCHs) that share a frequency band, and selects a reference TRCH using coding schemes of data to be transmitted using the TRCHs. After that, the wireless communication apparatus performs outer loop control so that a block error rate (BLER) of the data to be transmitted using the reference TRCH is set to a target BLER.

Abstract: Apparatus, and an associated method, for estimating a bit error rate of data communicated to a receiving station of a digital communications system, such as a GSM/EDGE cellular communication system. Soft decision values, indicative of confidence levels that decided values have been correctly decided are compared with threshold values by a comparator. A count is accumulated by a counter to whose counted value is representative of decided data values having associated therewith low levels of confidence that the decided values are correct. The count value is used in the formulation of the BER estimation.

Abstract: The present disclosure is directed to implementing power savings features on storage drives within a storage subsystem. A controller determines a drive is inactive and directs a power connector to prevent power from being provided to the drive. The controller may receive an input/output request for the inactive drive, direct the power connector to allow power to be provided, and provide the input/output request. When the controller receives an input/output request for the inactive drive, the controller sends a notification to the request's originator that the drive is unavailable and to retry after a fixed period of time. The controller performs maintenance on the drive when the drive is not inactive. The controller determines a maintenance time when the drive will be inactive and performs maintenance at an accelerated rate.

Abstract: In embodiments of the present invention improved capabilities are described for sending a single cast frame from a first node to a second node in a mesh network; sending the single cast frame from the second node to a third node in a mesh network; using the first node to detect the single cast frame sent from the second node to the third node; and interpreting this detection within the first node as an acknowledgement of success in sending the single cast frame from the first node to the second node. An additional method described herein may send a second single cast from the second node to a third node in a mesh network, interpret detection of the second single class frame within the first node as an acknowledgement of success in sending the first single cast frame from the first node to the second node.

Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Abstract: A method for processing noise interference in a serial advanced technology attachment (SATA) interface. In the method, when a receiver does not receive a SOF primitive (start of frame primitive) but does receive an EOF primitive (end of frame primitive) or WTRM primitive (wait for frame termination primitive), the receiver outputs a R_ERR primitive (reception error primitive) to enable a transmitter to resend original data and thus to eliminate the interference. In addition, if the transmitter detects an error during the data transmission, a HOLD primitive (hold data transmission primitive) will be issued to temporarily stop the data transmission.

Abstract: Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: An electronic communication network supports delivery of video program Internet protocol packets. A source device transmits both first and second video program Internet protocol packets. A first recipient device is assigned as positive acknowledgment leader by the source device and a second recipient device is assigned as negative acknowledgement leader by the source device. The first recipient device is operable to transmit to the source device a positive acknowledgment of receipt of the first video program Internet protocol packet. The second recipient device is operable to transmit to the source device a negative acknowledgment of non-receipt upon not receiving the first video program Internet protocol packet. The source device responds to the negative acknowledgement of non-receipt by the second recipient device by multicast resending the second video program Internet protocol packet to both the first and second recipient devices.

Abstract: A test set for evaluating network performance is described, and which may include an output device, a processor, a power supply, a memory unit, and a control terminal. The test set may be configured to receive a user-entered selection of one of a plurality of different bit-error rate profiles and generate a test signal exhibiting the selected bit-error rate profile. The test set may also supply the test signal exhibiting the selected bit-error rate profile to a network under test. In addition, the test set may receive as an input, an output from the network under test. The output may include the test signal exhibiting the selected bit-error rate. The test set may evaluate the received test signal and determine the performance of the network in response to the received test signal exhibiting the bit-error rate. The test set may then output the results of the evaluation.

Abstract: Disclosed is means for quantifying resistance to soft errors in a logic circuit. A logic block group 120 having at least one set comprising a logic block having at least one logic circuit and a sequential circuit that inputs the output of the logic block is arranged in an irradiation region 110 of a high-energy particle irradiation device, and subjected to irradiation with high-energy particles. A control section 101 calculates the error rate of the logic circuit from the value obtained by subtracting the number of errors of the sequential circuit when the logic block of the logic block group 120 is bypassed, from the number of errors of the sequential circuit and the logic block of the logic block group 120.

Abstract: Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.

Abstract: A method for detecting validity of downlink control information in telecommunication user equipment and a decoder and baseband receiver to perform the method are provided. The object of avoiding falsely detecting payload data and misinterpreting them is achieved by reverse encoding a bit output sequence of a Viterbi decoder; determining hard bits from a soft-bit input sequence of the decoder; determining a bit count of real received bits; comparing the reverse encoded bit stream to the determined hard bit stream and counting the number of mismatches to obtain an error count; comparing a bit error rate which is defined as a quotient of the error count and the bit count against a predefined threshold value; and rejecting the payload as invalid if said bit error rate is above said threshold value, even if a cyclic redundancy check of the payload gives a correct result.

Abstract: Cross-decoding assists decoding of an otherwise uncorrectable error when decoding a desired page of a multi-level-cell technology flash memory. A solid-state disk (SSD) controller adjusts space allocated to redundancy respectively within various pages (e.g. upper, middle, and lower pages) such that the respective pages have respective effective Bit Error Rates (BER)s, optionally including cross-decoding, that approach one another. Alternatively the controller adjusts the allocation to equalize decoding time (or alternatively access time), optionally including decoding time (accessing time) accrued as a result of cross-decoding when there is an otherwise uncorrectable error. The adjusting is via (a) respective ratios between allocation for ECC redundancy and user data space, and/or (b) respective coding rates and/or coding techniques for each of the various pages.

Abstract: A storage device with self-status detection and an inspection method thereof are provided. The storage device includes a plurality of storage areas (i.e., block tables), a plurality of memory blocks, and a status detection unit. The storage areas respectively have a corresponding weight value, and the addresses of memory blocks which have the same number of error correct codes (ECCs) are recorded in the same storage area. The status detection unit obtains a status of the storage device according to the number of addresses of the memory blocks recorded in a storage area and the corresponding weight value of the storage area.

Abstract: An encoding of K blocks of information for transmission on N subchannels, responsive to a number of redundant blocks M, employs one of multiple check codes depending on the number of redundant blocks M and employs multiple processes for determining a code for the K blocks of information depending on the number of redundant blocks M and K blocks of information together.

Abstract: A technique for managing hard failures in a memory system employing a locking is disclosed. An error count is maintained for units of memory within the memory system. When the error count indicates a hard failure, the unit of memory is locked out from further use. An arbitrary set of error counters are assigned to record errors resulting from access to the units of memory. Embodiments of the present invention advantageously enable a system to continue reliable operation even after one or more internal hard memory failures. Other embodiments advantageously enable manufacturers to salvage partially failed devices and deploy the devices as having a lower-performance specification rather than discarding the devices, as would otherwise be indicated by conventional practice.

Abstract: Methods, apparatuses and systems for physical link error data capture and analysis. A receiver is coupled to receive a data stream via a point-to-point serial link. A control circuit is coupled with the receiver to cause the receiver to selectively sample the data stream according to an offset parameter and an interval parameter. Comparison circuitry compares the data stream sample to expected data values to determine a bit error rate.

Abstract: Handling of integrity check failure in a wireless communication system can safely send the mobile station to the idle mode upon detection of security failure. Alternatively or in addition, attempts to recover from the security failure situation can be enabled without forcing the mobile station to enter idle mode. The mobile station autonomously transitions to idle mode when the integrity check failure is detected a certain threshold number ‘X’ times during a specified period ‘Y’. Whereupon, the mobile station initiates the Radio Resource Control (RRC) connection re-establishment procedure after integrity check failure is detected. In the RRC connection re-establishment procedure, the security parameters are re-initialized to provide a possibility to recover from the failure situation.

Abstract: An apparatus and method for reduction of bit errors in continuous data transmission via a data transmission medium comprising. The apparatus (1) comprises a monitoring unit (1A) for monitoring of transceiver parameters of at least one transceiver (3) transmitting said data and/or medium parameters of said data transmission medium (4) and a calculation unit (1B) for predicting a time and a duration of an occurrence of at least one event affecting a bit error rate (BER) of said continuous data transmission depending on the monitored parameter; and a control unit (1C) for throttling a bandwidth of a data switch (6) connected to said transceiver (3) during the predicted duration of the event for bit error reduction.

Abstract: A system and method for providing adaptive backoff including one or more transmitters configured to transmit a first data request to a media module at a scheduled time, poll the media module to determine accessibility of the media module, and transmit a second data request to the media module at a rescheduled time determined by the one or more processors. The system and method may also include one or more processors configured to determine that the media module is inaccessible and set the rescheduled time for the media box to transmit a second data request to the media module when the media module is accessible, wherein the rescheduled time is based at least in part on optimizing system capacity of the media module. The system and method may also include one or more receivers configured to receive one or more responses to the polling indicating accessibility of the media module and receive data from the media module based on the second data request.

Abstract: Method for improving a TFCI transportation performance, including the steps of (1) coding TFCI information bits to be transported through each radio frame, (2) repeating a TFCI code word produced by the coding for an arbitrary times, (3) applying puncturing patterns different from each other to the repeated code words produced as many as the repeated times, and puncturing the repeated code words at locations different from each other, and (4) dividing, inserting, and transporting the punctured fixed length repeated code words in each slot of the radio frame, whereby improving TFCI information transportation performance, and embodying the receiver side decoder to be identical to a case when a 32 bit code word are transported perfectly.

Abstract: Method for improving a TFCI transportation performance, including the steps of (1) coding TFCI information bits to be transported through each radio frame, (2) repeating a TFCI code word produced by the coding for an arbitrary times, (3) applying puncturing patterns different from each other to the repeated code words produced as many as the repeated times, and puncturing the repeated code words at locations different from each other, and (4) dividing, inserting, and transporting the punctured fixed length repeated code words in each slot of the radio frame, whereby improving TFCI information transportation performance, and embodying the receiver side decoder to be identical to a case when a 32 bit code word are transported perfectly.