Abstract: An apparatus and method for reduction of bit errors in continuous data transmission via a data transmission medium comprising. The apparatus (1) comprises a monitoring unit (1A) for monitoring of transceiver parameters of at least one transceiver (3) transmitting said data and/or medium parameters of said data transmission medium (4) and a calculation unit (1B) for predicting a time and a duration of an occurrence of at least one event affecting a bit error rate (BER) of said continuous data transmission depending on the monitored parameter; and a control unit (1C) for throttling a bandwidth of a data switch (6) connected to said transceiver (3) during the predicted duration of the event for bit error reduction.

Abstract: A system and method for providing adaptive backoff including one or more transmitters configured to transmit a first data request to a media module at a scheduled time, poll the media module to determine accessibility of the media module, and transmit a second data request to the media module at a rescheduled time determined by the one or more processors. The system and method may also include one or more processors configured to determine that the media module is inaccessible and set the rescheduled time for the media box to transmit a second data request to the media module when the media module is accessible, wherein the rescheduled time is based at least in part on optimizing system capacity of the media module. The system and method may also include one or more receivers configured to receive one or more responses to the polling indicating accessibility of the media module and receive data from the media module based on the second data request.

Abstract: A receiver circuit is described. In the receiver circuit, an analog-to-digital converter (ADC) generates first samples of a data signal based on a first clock signal, and a clock-data-recovery (CDR) error-detection circuit generates second samples of the data signal based on a second clock signal. In addition, the CDR error-detection circuit estimates intersymbol interference (ISI) at a current sample in the second samples from an adjacent, subsequent sample in the second samples. Based on the second samples and the estimated ISI, a CDR circuit generates the first clock signal and the second clock signal, which involves modifying the skews of either or both of these clock signals so that the current sample is associated with a zero crossing of a pulse response of a communication channel from which the data signal was received, thereby reducing or eliminating the ISI from the adjacent, subsequent sample.

Abstract: A digital system is provided that converts compressed data using an indexed transcoding lookup table. A stream of compressed data samples has data samples that represent one of n values corresponding to the first compression format. The transcoding table has at least n indexed entries, and each of the n indexed entries contains a data value corresponding to a second compression format. The transcoding table is accessed by using each of a portion of the received data samples as an index into the table to form a set of transcoded data samples that have a second compression format. The set of transcoded data samples form a stream of compressed data samples that have the second compression format. The transcoding table may be augmented to perform transcoding error correction by concatenating an error value with the data sample to index the table.

Abstract: A transmitting station includes: an error detecting code attachment block that attaches error detecting codes respectively to a plurality of data pieces; a transmitter block that transmits the plurality of data pieces with the error detecting codes attached thereto to a receiving station by using different radio frequencies, respectively; a receiver block that receives, from the receiving station, the results of error detections that the receiving station applies respectively to the plurality of data pieces on the basis of the error detecting codes attached respectively to the plurality of data pieces; and a transmission data managing block that controls retransmission of the data to the receiving station on the basis of the received results of the error detection.

Abstract: For an error rate QBER, threshold values are preset, including a threshold value Qbit for frame synchronization processing, a threshold value Qphase for phase correction processing, and a threshold value QEve for eavesdropping detection. Upon the distribution of a quantum key from a sender to a receiver, when the measurement value of QBER is deteriorated more than Qbit, frame synchronization processing is performed. When the measurement value of QBER is deteriorated more than Qphase, phase correction processing and frame synchronization processing are performed. When QBER does not become better than QEve even after these recovery-processing steps are repeated N times, it is determined that there is a possibility of eavesdropping, and the processing is stopped.

Abstract: Systems, controllers and methods are disclosed, such as an initialization system including a controller that receives patterns of read data coupled from a memory device through a plurality of read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of read data received through the read data lanes. The controller then adjusts the manner in which the read data received through the read data lanes during normal operation are divided into frames. The controller can also couple patterns of command/address bits to the memory device through a plurality of command/address lanes. The memory device can send the received command/address bits back to the controller through the read data lanes. The controller is operable to detect any lane-to-lane skew in the patterns of command/address bits received through the read data lanes to adjust the manner in which the command/address bits coupled through the command/address lanes during normal operation are divided into frames.

Abstract: When a secure counter malfunction detection unit 212 deters a malfunction in a secure counter 211, a content playability judgment unit 206 performs a content playability judgment based on information managed by a malfunctioning-state playback processing management unit 214. The malfunctioning-state playback processing management unit 214 stores a malfunctioning-state playback condition composed of information such as a playback count and a playback time. The content playability judgment unit 206 judges that content is playable when the malfunctioning-state playback condition is met, and a content playback unit 210 splays the content.

Abstract: Pluggable transceiver modules with additional functions and circuitry contained within the module. In a first embodiment, additional circuitry is added to determine bit error rates at the point of the module itself. This allows a much better diagnostic evaluation of location of problem. In an alternate embodiment, various logic is placed in the module. In a first alternate embodiment encryption/decryption units are placed in the converter module so that encryption and decryption operations on the serial bitstream do not need to be performed in a switch. Existing switches can be used but the interconnecting links can still be encrypted. A second alternate embodiment includes compression/decompression units placed in the module to allow effective higher throughput on the selected links.

Abstract: The disclosure relates to optical fiber transmission systems, and in particular, pertains to the transceiver cards in an optical fiber transport system. In particular the disclosure teaches an improved transceiver card architecture that allows high density, flexibility and interchangeability of functionality.

Abstract: A method for providing error-resilient video content may include receiving video data reflective of multiple video frames and encoding the video data to generate a plurality of packets. The method may also include transmitting the first group of packets to at least two receivers and receiving feedback information regarding receiving status of respective ones of the plurality of packets, the feedback information being indicative of packets not received correctly. The method may further include examining error indications based on the feedback information and implementing a first error-correction policy if a variation in the error indications among the at least two receivers is below a first error threshold and a second error-correction policy if the variation is above the first error threshold. At least one of the first and second error-correction policies may include transmitting or retransmitting at least one packet using a different coding scheme.

Abstract: An integrated circuit (“IC”) may include circuitry for use in testing a serial data signal. The IC may include circuitry for transmitting the serial data signal with optional jitter, optional noise, and/or controllably variable drive strength. The IC may also include circuitry for receiving the serial data signal and performing a bit error rate (“BER”) analysis in such a signal. The IC may provide output signals indicative of results of its operations. The IC can operate in various modes to perform or at least emulate functions of an oscilloscope, a bit error rate tester, etc., for testing signals and circuitry with respect to jitter-tolerance, noise-tolerance, etc.

Abstract: An IC that includes an eye viewer and a BER checker coupled to the eye viewer, where the BER checker receives a serial data signal from the eye viewer, is provided. In one implementation, the BER checker receives the serial data signal from the eye viewer without the serial data signal passing through a deserializer. In one implementation, the BER checker compares the serial data signal against a reference data signal to determine the BER for the serial data signal. In one implementation, the IC includes an IC core coupled to the eye viewer and the BER checker, where the BER checker is outside the IC core. In one implementation, the BER checker is a dedicated BER checker. In one implementation, the BER checker includes an exclusive OR gate, a programmable delay circuit coupled to the exclusive OR gate, and an error counter coupled to the exclusive OR gate.

Abstract: One embodiment provides an error detection method wherein single-bit errors in a memory module are detected and identified as being a random error or a repeat error. Each identified random error and each identified repeat error occurring in a time interval is counted. An alert is generated in response to a number of identified random errors reaching a random-error threshold or a number of identified repeat errors reaching a repeat-error threshold during the predefined interval. The repeat-error threshold is set lower than the random-error threshold. A hashing process may be applied to the memory address of each detected error to map the location of the error in the memory system to a corresponding location in an electronic table.

Abstract: An ACS unit of a Viterbi decoder and a method for calculating the bit error rate (BER) before Viterbi decoder are provided. The ACS unit includes a state calculator and a BER calculator. The state calculator calculates the state metric of a corresponding target state in the trellis diagram and selects one of two candidate source states as the selected source state of the target state. The state calculator also provides a selection signal indicating the selected source state. The BER calculator is coupled to the state calculator for providing the sum of the BER of the selected source state and the bit error count (BEC) of the transition from the selected source state to the target state as the BER of the target state.

Abstract: System and method for testing jitter tolerance by using a built-in jitter modulation circuit is disclosed. An embodiment comprises a jitter modulation circuit, a transmitter, a receiver and a data comparison unit. The jitter modulation circuit includes a plurality of data latches, a phase-select block and a multi-phase clock generator. The multi-phase clock generator is capable of generating a plurality of signals having different phase shifts wherein one signal having a phase shift from the system clock signal is selected by the phase-select block. The selected signal alters the data by injecting jitter through a plurality of data latches. The jitter-contaminated data is transmitted to a data comparison unit through a transmitter and a receiver. The on-chip test circuit compares the jitter-contaminated data with the original data and calculates the bit error rate so as to determine whether the jitter tolerance of this semiconductor device satisfies the specification.

Abstract: This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

Abstract: An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether the first signal is valid and a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.

Abstract: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.

Abstract: An apparatus, system, and method are disclosed for rapidly grading the operating condition of computer storage. A storage log module 312 logs error information regarding any error in a storage subsystem 302 that occurs during normal operation. A storage test module 314 performs a cursory check 318 of the storage subsystem 302 as requested by a user. A storage diagnostic module 316 grades the storage subsystem 302 on an operating condition scale based at least in part upon the error information logged and upon results of the cursory check 318. In one embodiment, the storage subsystem 302 is graded as pristine if no error has been logged and no error was detected by the cursory check 318, as potentially failing if any error has been logged but no error was detected by the cursory check 318, and as failing if any error was detected by the cursory check 318.

Abstract: Memory cells are programmed and read, at least M=3 data bits per cell, according to a valid nonserial physical bit ordering with reference to a logical bit ordering. The logical bit ordering is chosen to give a more even distribution of error probabilities of the bits, relative to the probability distributions of the data error and the cell state transition error, than would be provided by the physical bit ordering alone. Preferably, both bit orderings have 2M?1 transitions. Preferably, the logical bit ordering is evenly distributed. The translation between the bit orderings is done by software or hardware.

Abstract: A non-volatile memory device including: a memory cell array storing an electrically rewritable resistance value as data in a non-volatile manner; a first cache circuit configured to hold program data to be programmed in the cell array; a second cache circuit configured to hold preprogrammed data read from an area of the cell array; and a judging circuit configured to compare and check the program data with the preprogrammed data, and judge whether there are one or more disagreement bits therebetween or not.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Abstract: In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a normal range set for each one, thus indicating a fatigue condition. If any cell indicates a fatigue condition, the data from the block of cells indicating the fatigue is moved to another block. In one embodiment, an error detection and correction process is performed on the data prior to being written into another memory block.

Abstract: Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: An apparatus used in a communication system having a plurality of time slots includes a signal processing circuit, a signal detector, and a controlling circuit. The signal processing circuit receives an input signal. The signal detector detects the input signal to generate a detection result. The controlling circuit controls the signal processing circuit according to the detection result. When the detection result does not meet a predetermined criterion, the controlling circuit adjusts the signal processing circuit for reducing power consumption of the signal processing circuit.

Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.

Abstract: Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: Shadow selection logic is used to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. In addition, shadow compare logic is used to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare Shadow counters are used to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

Abstract: Apparatuses, computer program products, and methods for authenticating digital signals are provided in which copies of a watermark are extracted from a digital signal with at least some of the copies potentially having distorted values. The original values of the watermark may be reconstructed exclusively based on the extracted copies of the watermark. The method includes estimating one or more bit error rates without training or reference information. The bit error rates are modeled as being equivalent to transmitting the copies through binary symmetric channels. The estimated bit error rates and the distorted values are combined to reconstruct the original values of the watermark. The reconstructed watermark may be compared to an original watermark for authenticating the received digital signal. Also, the estimated bit error rates may be compared to a random sequence of bits for verifying the presence of the watermark without knowing the original values of the watermark.

Abstract: Each of a control panel node 2 and an input/output node 3 has a safety data processing unit 7 and a high reliability communication unit 8. At the time of transmission, the safety data processing unit 7 creates a safety data packet including data about safety and the high reliability communication unit 8 creates a communication data packet including the safety data packet from the safety data processing unit 7 and transmits the communication data packet a predetermined number of times. At the time of reception, the high reliability communication unit 8 acquires and outputs a safety data packet by determining one of one or more communication data packets having the same contents which it has received properly as an effective packet, and the safety data processing unit 7 analyzes a state concerning the safety of a system on the basis of the data about safety acquired from the safety data packet from the high reliability communication unit 8.

Abstract: The present invention is to provide a signal analyzing apparatus which can easily identify a pattern high in error rate and a pattern causing bit errors in comparison with the conventional device.

Abstract: A signal receiver includes a data recovery module that generates an equalized data signal and a recovered data signal based on a data input signal. An error module generates an error information signal based on the equalized data signal and an error threshold signal. An eye measurement control module generates an eye characteristic signal based on the recovered data signal and the error information signal.

Abstract: Architecture that implements error correcting pointers (ECPs) with a memory row, which point to the address of failed memory cells, each of which is paired with a replacement cell to be substituted for the failed cell. If two error correcting pointers in the array point to the same cell, a precedence rule dictates the array entry with the higher index (the entry created later) takes precedence. To count the number of error correcting pointers in use, a null pointer address can be employed to indicate that a pointer is inactive, an activation bit can be added, and/or a counter, that represents the number of error correcting pointers that are active. Mechanisms are provided for wear-leveling within the error correction structure, or for pairing this scheme with single-error correcting bits for instances where transient failures may occur. The architecture also employs pointers to correct errors in volatile and non-volatile memories.

Abstract: A method and apparatus for evaluating and optimizing a signaling system is described. A pattern of test information is generated in a transmit circuit of the system and is transmitted to a receive circuit. A similar pattern of information is generated in the receive circuit and used as a reference. The receive circuit compares the patterns. Any differences between the patterns are observable. In one embodiment, a linear feedback shift register (LFSR) is implemented to produce patterns. An embodiment of the present disclosure may be practiced with various types of signaling systems, including those with single-ended signals and those with differential signals. An embodiment of the present disclosure may be applied to systems communicating a single bit of information on a single conductor at a given time and to systems communicating multiple bits of information on a single conductor simultaneously.

Abstract: Systems and methods are disclosed for detecting temporary high level impairments, such as noise or interference, for example, in a communications channel, and subsequently, mitigating the deleterious effects of the dynamic impairments. In one embodiment, the method not only performs dynamic characterization of channel fidelity against impairments, but also uses this dynamic characterization of the channel fidelity to adapt the receiver processing and to affect an improvement in the performance of the receiver. For example, in this embodiment, the method increases the accuracy of the estimation of the transmitted information, or similarly, increases the probability of making the correct estimates of the transmitted information, even in the presence of temporary severe levels of impairment. The channel fidelity history may also be stored and catalogued for use in, for example, future optimization of the transmit waveform.

Abstract: Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a plurality of counters, the scheduling unit operable to detect a single-bit error in data read from the memory device, and to increment a value in a particular one of the plurality of counters, the particular one of the plurality of counters corresponding to the particular bit in the accessed data which incurred the single-bit error in the read data.

Abstract: A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: A multiplexing method for data switching is disclosed. In the method, a continuous data is received, and the continuous data includes a plurality of super frames, and each super frame includes a plurality of frames. These super frames are divided into a set of even super frames and a set of odd super frames. The frames included in the set of odd super frames are sorted by corresponding required bit error rate of each frame decreasingly or increasingly. The frames included in the set of even super frames are sorted by the required bit error rate of each frame increasingly or decreasingly. An encoder is used to encode these sorted super frames.

Abstract: A test and measurement instrument includes a pattern detector for detecting a beginning sequence in a signal under test (SUT), and generates a synchronization signal. In response to the synchronization signal, a memory outputs a reference test pattern. A symbol comparator compares the reference test pattern with the SUT. The symbol comparator can produce a symbol error rate. One or more 8b to 10b converters receives the SUT from the input and the digitized data from the memory, and converts the data from an 8b coded format to a 10b coded format. A bit comparator compares the 10b coded reference test pattern with the 10b coded SUT in response to the symbol comparator. The bit comparator is coupled to a bit error counter, which produces a bit error rate independent of any disparity errors that may be present in the incoming digitized data received by the test and measurement instrument.

Abstract: An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking circuit and a controller. The controller includes an error recovery module configured to retry a data communication when an error is detected and deactivate the SerDes lane when a rate of errors on the SerDes lane exceeds a threshold error rate value. Other devices, systems, and methods are disclosed.

Abstract: A method for measuring business transaction performance, includes the steps of, at a top-level component, assigning a correlation tag and original time stamp to a server request, passing the original time stamp with any server requests from the top-level component to one or more subsequent components, and computing an aggregate latency over a predetermined interval at the top-level component and at each subsequent component based on the original time stamp.

Abstract: A method includes monitoring a use of a cable assembly that includes a communication cable terminated by a termination module. Data indicative of the use is written to a writeable non-volatile memory in the termination module. The use of the cable assembly is acted upon by reading the data from the non-volatile memory.

Abstract: During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller during normal operation of the memory device. In one embodiment, the memory test is for a programmability test to determine if the memory block can be programmed. An indication of programmability is stored in each block in a predetermined location.

Abstract: Methods of calculating a compensation voltage and adjusting a threshold voltage, a memory apparatus, and a controller are provided. In the present invention, data is written into a rewritable non-volatility memory, and the data is then read from the rewritable non-volatility memory and compared with the previously written data to obtain error bit information. The compensation voltage of the threshold voltage is calculated according to the error bit information, and the threshold voltage is adjusted according to the compensation voltage.

Abstract: A data reading method for a writable non-volatile memory module having physical pages is provided. The method includes grouping the physical pages into a plurality of physical page groups. The method also includes reading first data from a physical page of a first physical page group by applying a first threshold voltage set. The method still includes, when the first data can be corrected by an error checking and correcting circuit and an error bit number corresponding to the first data is not smaller than an error bit number threshold, calculating compensation voltages for the first threshold voltage set. The method further includes adjusting the first threshold voltage set by the compensation voltages and applying the adjusted first threshold voltage set to read data from the physical pages of the first physical page group. Accordingly, data stored in the rewritable non-volatile memory module can be correctly read.

Abstract: A transmitter/receiver device includes: a transmitter unit including a parallel/serial converting circuit, a waveform deteriorating circuit, and a transmitter circuit; and a receiver unit including a receiver circuit, a serial/parallel converting circuit, and an error detecting circuit. The parallel/serial converting circuit converts a transmitter-side parallel signal to a transmitter-side serial signal. The waveform deteriorating circuit deteriorates a signal waveform of the transmitter-side serial signal. The transmitter circuit transmits to the receiver unit the signal whose waveform is deteriorated. The receiver circuit receives, as a receiver-side serial signal, the signal transmitted from the transmitter circuit. The serial/parallel converting circuit converts the receiver-side serial signal to a receiver-side parallel signal. The error detecting circuit detects a bit error rate of the receiver-side parallel signal.

Abstract: A communication terminal device and a reception environment reporting method produce a more excellent throughput, by making a report of a reception environment with higher accuracy. An SIR measuring section measures an SIR from a reception signal that has been received from a base transceiver station. A CQI converter converts the SIR that has been measured by the SIR measuring section into a CQI value. A BLER calculating section calculates a block error rate of the reception signal. A CQI correcting section corrects the CQI value that has been calculated by the CQI converter, in accordance with the block error rate. A CQI transmitter transmits the CQI value that has been corrected by the CQI correcting section, to the base transceiver station.

Abstract: In a header decompression apparatus 709, a header decompressor 703 refers to reference information stored in a reference information manager 707 to decompress a compressed header of a packet received by a packet receiver 704. An error detector 702 detects a CRC error in the packet with its header decompressed by the packet receiver 704, and outputs only a correct packet. A successive error counter 705 counts the number of successive errors detected by the error detector 702. A successive decompression success counter 706 counts the number of decompression successes that successively appear. By referring to these counted numbers, an update request unit 708 transmits an update request to a transmitting side as required. The reference information manager 707 manages the reference information for header decompression. With this structure, the header decompression apparatus can request update of the reference information based on the state of the error.