Abstract: A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: A sequential semiconductor device tester, and in particular to a sequential semiconductor device tester is disclosed. In accordance with the sequential semiconductor device tester, a function of generating a test pattern data for a test of a semiconductor device and a function of carrying out the test are separated to sequentially test the semiconductor device, to maintain a signal integrity and to improve an efficiency of the test by carrying out a test under an application environment or an ATE test according to the test selection command.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of these applied data signals have been properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group of applied data signals. A second group of the applied data signals are then captured after the first group. The second group of applied data signals are determined to have been properly captured when the second captured group of applied data signals corresponds to the group of expect data signals. In this way, when capture of the applied series of data signals is shifted in time from an expected initial capture point, subsequent captured groups of applied data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured.

Abstract: A test pattern generation apparatus extracts processing that coincides with input combinational test confirmation processing from program test patterns stored in a file, extracts execution conditions of the extracted processing from program test pattern lists, rearranges the execution conditions, generates one test pattern, extracts data handling processing that satisfies conditions in the test pattern lists, and generates and displays a combinational test pattern list.

Abstract: There is provided a semiconductor testing system capable of achieving a higher speed in transmission of signals while holding back an increase in the number of transmission paths, and preventing occurrence of a delay time difference between the respective transmission paths. Processing is executed in the semiconductor testing system whereby upon generation of pattern signals by the pattern generator, the pattern signals are subjected to the serial conversion to be transmitted to the test head, while the pattern signals transmitted via the transmission cables subjected to parallel conversion. Another processing is executed whereby the plural kinds of the pattern signals are allocated one by one on an address-by-address basis to be stored in the respective phase control memories to thereby detect the start address storing the pattern signal matching the first pattern signal at the start of the reading, in respect of phase.

Abstract: A system and method for testing a device with multiple interfaces by generating a predetermined data pattern within the device, transmitting the pattern to a test analyzer, generating a second predetermined data pattern within the test analyzer, and simultaneously transmitting the second test pattern to the device where the second test pattern is verified. The first and second test patterns may be the same or different, depending on the application. Further, the transmit and receive paths may be tested separately and independently in addition to simultaneously.

Abstract: A system and method are provided for built-in-self test of any bits that have slipped from their appropriate positions within a frame character clock cycle. If a bit has slipped, then the built-in-self test mechanism can also implement either a clock generation stretch operation or a barrel shift operation to readjust the frame boundary output from a receiver with a 1-to-N deserializer. A pseudo-random bit sequence can be generated having the same logic value in both the receiver and transmitter, where the output of the deserializer which receives the transmitted bits is compared bit-by-bit with the receiver-generated bits as part of the built-in-self test mechanism. If a bit is determined to have been slipped, then error correction occurs with aliasing and phase jitter in mind.

Abstract: An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.

Abstract: A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter unit (FTM) with response unit (RP) for providing a required data width for storing the test vectors therein.

Abstract: A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).

Abstract: Scan tests tolerant to indeterminate states generated in an integrated circuit (IC) when employing signature analysis to analyze test outputs. Bits with indeterminate-state are masked when scanning out the bits from the scan chains to force such indeterminate bits to a known logic level. This prevents a signature generator receiving the outputs of a scan test from generating an invalid signature. In an embodiment, masking information is stored in encoded form in a memory. A decoding circuit decodes the masking information and provides mask data under control from a mask controller. Mask data is sent to a masking circuit which also receives corresponding bits from scan-out vectors, with each scan-out vector being generated by a corresponding one of multiple scan chains. The output of the masking circuit may be provided in a compressed form to the signature generator circuit.

Abstract: In one embodiment, a method may include generating a test code segment including a number of selected opcodes and executing the test code segment for a plurality of iterations. The method may also include saving a first test result of the execution of the test code segment after a first iteration and comparing additional test results of each subsequent iteration with the first test result. The method may further include determining whether any of the additional test results are different than the first test result.

Abstract: A method for optimizing a pattern generation program used in a signal generator comprising a generator for generating a signal pattern based on a pattern generation program, a memory for storing the signal pattern, and an output for outputting on a predetermined cycle the signal pattern stored by the memory, this optimizing method comprising an evaluation step for evaluating for each command of the pattern generation program whether it is necessary to develop the command in question of the program and a development step for developing the command.

Abstract: A semiconductor device includes an output path; an input path; and a test signal generating circuit. The test signal generating circuit generates an input test data signal by changing at least one of an amplitude and a phase of an output test data signal which is generated from a test data in the semiconductor device and transferred on the output path, and supplies the input test data signal onto the input path. The output path and the input path are tested by using the output test data signal and the input test data signal, respectively.

Abstract: A methodology for generating scan based transition patterns (i.e., ATPG pattern generation for transition delay faults (“TDF”)) wherein when either a slow-to-rise (STR) or a slow-to-fall (STF) transition fault is detected, that specific fault is removed from a fault universe as well as its companion TDF, wherein the companion fault is a fault on the same node as the detected fault but has the opposite transition. In other words, if a slow-to-rise (STR) transition fault is detected, the slow-to-rise (STR) transition fault is removed from the fault universe as well as its corresponding slow-to-fall (STF) transition fault (and vise versa). By removing companion faults as well as those which are specifically detected, pattern generation run time is reduced as well as the total pattern count for the final delay test pattern.

Abstract: A method, apparatus and computer program product are provided for implementing deterministic based broken scan chain diagnostics. A deterministic test pattern is generated and is loaded into each scan chain in the device under test using lateral insertion via system data ports applying system clocks. Then each scan chain is unloaded and a last switching latch is identified. The testing steps are repeated a selected number of times. Then checking for consistent results is performed. When consistent results are identified, then the identified last switching latch is sent to a Physical Failure Analysis system.

Abstract: A switch control apparatus for controlling a switch is provided, the switch control apparatus including: a sequence memory for recording a sequence pattern, which includes open/close instruction data which instruct the switch thereon to open/close; an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from the sequence memory; and an open/close state storage module for storing an open/close state instructed by changed open/close instruction data, when the open/close instruction data retrieved by the address control module is changed, wherein the open/close state stored by the open/close state storage module is provided to the switch such that the switch opens or closes in response to the open/close state.

Abstract: A method and apparatus are disclosed for using a general purpose input-output (GPIO) interface to test a user input device such as a wireless keyboard or mouse. Operation of key-scan logic can be tested by the GPIO interface by temporarily disconnecting the outputs of the various rows and columns and substituting signals generated by a test algorithm into the input terminals of the key-scan logic. The test signal is processed by the key scan circuitry and a key-scan output signal is generated. This key-scan output signal is then compared to a known reference output signal to determine if the key-scan logic and associated circuitry is operating properly. Other embodiments of the GPIO testing system can be used to test other user devices such as a computer mouse/scrolling device.

Abstract: In a semiconductor integrated circuit 11, there is constructed a test expected value programming circuit 100 having an input/input-output pad 103 for retrieving a ground/power-source signal 104 from a ground terminal 30 or a power source terminal 31 connected to the semiconductor integrated circuit 11, a switch 105 for selectively switching the outputting of the ground/power-source signal 104 inputted via the input/input-output pad 103, and an expected value generation circuit 13 for generating a test expected value signal 21 based on a switch output signal 122 outputted from the switch 105.

Abstract: Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner.

Abstract: Representative embodiments are generally directed to storing compressed test pattern data on an automated test equipment (ATE) device. In one embodiment, the test pattern data is compressed according to a linear feedback shift register (LFSR). The LFSR may possess a low probability of occurrence of linear dependencies associated with compression of stimulus patterns to enable relatively highly compacted patterns to be compressed. Additionally or alternatively, repeat-filled test pattern data is run length encoded using variable length code words to facilitate parallel decompression within the ATE device.

Abstract: Specific bits of an incoming transmission are compared against a predetermined bit pattern. If the selected bits do not match the predetermined bit pattern, then the incoming transmission is rejected as a false packet. The predetermined bit pattern can include legal values for predetermined bits in a plurality of fields. Notably, these legal values are set by a networking standard. A parity check may check may be performed in addition to checking for predetermined bits in other fields. A user interface can be used to determine the predetermined bit pattern.

Abstract: In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular ? the number of inputs of the test unit (3) that are contained in the base of a cone (5).

Abstract: An input/output device includes a creating unit that creates a first data pattern that is different from a second data pattern created last time, a writing unit that writes the first data pattern as a written data pattern, and a judging unit that reads out a data pattern written in the input/output device as a read data pattern and judges whether the written data pattern and the read data pattern coincide with each other.

Abstract: Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.

Abstract: A multi-device system having a daisy chain system bus structure and related method of operation are disclosed. A reference signal having a defined oscillation period is communicated around the daisy chain bus structure. Total signal transmission time around the daisy chain bus structure as well as signal transmission time to each one of a plurality of client devices connected to a host device by the daisy chain bus structure may be readily determined.

Abstract: A test specification and test program set for a given unit under test and a given automated test equipment platform is generated in an automated manner using information stored in a repository.

Abstract: Techniques are provided for modeling memory operations when generating test cases to verify multi-processor designs. Each memory operation has associated therewith a set of transfer attributes that can be referenced by a test generator. Using the transfer attributes, it is possible to generate a variety of interesting scenarios that handle read-write collisions and generally avoid reloading or resources. The model provides accurate result prediction, and allows write access restrictions to be removed from sensitive memory areas, such as control areas.

Abstract: Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated from the captured first group. A second group of applied data signals is then captured and determined to have been properly captured when the second group corresponds to the group of expect data signals. In this way, when a captured series of data signals is shifted in time from an expected capture point, subsequent captured data signals are compared to their correct expected data signals in order to determine whether that group, although shifted in time, was nonetheless correctly captured. A pattern generator generates expect data signals in this manner, and may be utilized in a variety of integrated circuits, such as an SLDRAM.

Abstract: A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal; and a comparing unit that compares a response signal, which is output from the DUT in response to the input of the test signal, and the reference signal by offsetting the test signal contained in a composite signal of the test signal and the response signal and the test signal contained in the comparison signal. The DUT is determined to be defective or not based on a result of comparison by the comparing unit.

Abstract: A test method and implementation is described to test an internal data path within a DDR DRAM during a read operation. A worse case test sequence and a compliment of the worse case test sequence is stored within memory. The test sequence and its compliment are arranged within a data word such that upon read out of the data word, the test sequences or the compliment of the test sequences is applied to a plurality of wire connections of the internal data path. Each test sequence comprises a plurality of logical bits of the same value followed by a bit of the opposite value, which tests for charge buildup on each element of the internal data path. Adjacent elements of the internal data path connect test sequences that are compliments to maximize voltage differentials and enhance possibility of signal coupling between wire elements of the internal data path.

Abstract: An apparatus for testing an IC device includes a test signal generator for generating a predefined sequence of test signals that are input to the IC device. A timing skew monitor is provided for monitoring the test signals input in the IC device and a signal output from the IC device for a predetermined time period, and creating an array indicating an execution or a nonexecution of signal timing combinations of one of the test signals relative to at least one of the other test signals within the predetermined time period by the IC device. A determination as to whether the desired signal timing combinations of the test signals have been executed by the IC device is made by an operator.

Abstract: A method for diagnosing a degree of interference between a plurality of faults in a system under test, the faults being detected by means of applying a test suite to the system under test, includes: 1) for each of the plurality of faults, and for each of a plurality of test syndromes, where a test syndrome is a pattern of passing and failing tests of the test suite, determining relative frequencies at which particular ones of the faults are coupled with particular ones of the syndromes; and 2) using the relative frequencies at which particular ones of the faults are coupled with particular ones of the syndromes to calculate and display to a user, via a graphical user interface, and for the test suite as a whole, test suite degrees of interference between pairs of the faults. Other embodiments are also disclosed.

Abstract: There is provided a pattern generator that generates a test pattern for testing an electronic device using test data previously supplied. The pattern generator includes a cache memory, a main memory operable to store a plurality of test data blocks of which each block is the test data of the magnitude capable of being stored on the cache memory, and an instruction memory operable to store instruction information showing sequence in which the plurality of test data blocks should be stored on the cache memory, in which the pattern generator sequentially outputs the test data blocks stored on the cache memory as the test pattern. It is preferable that the instruction memory stores the instruction information showing all sequence of the test data blocks to be stored on the cache memory in order to generate the test pattern before beginning to generate the test pattern.

Abstract: A system, method, and computer program product for scan testing a device under test (DUT). In one embodiment, compressed test data comprising packets are received at a serial test data input. The packets contain encoded data characterizing a test data bit stream and each includes a bucket select field and a fill value field. The bucket select field contains an bucket select value that maps to a length of a bit-string. The fill value field contains a fill value indicating the uniform binary value of the bit-string. The compressed test data is then expanded and the expanded test data is scanned into internal structures of the DUT to test internal structures of the DUT. In a preferred embodiment, the compressed test data is received at a first clock rate. The test data is expanded and scanned into the internal structures of the DUT at a second clock rate that is higher than the first clock rate.

Abstract: Disclosed herein are methods and systems for generating test vectors for use in verification of a circuit design and for hardware testing on a fabricated circuit representative of the circuit design. The system and methods can systematically and automatically perform functional and structural testing on selected paths of the circuit design and, in turn, generate one or more test vectors to increase PDT test coverage using the results of the structural test on the selected path.

Abstract: A testing device that tests an electronic device includes a test pattern outputting unit operable to output a test pattern to the electronic device, a deciding unit operable to decide whether an output signal from the electronic device satisfies a predetermined condition, an instruction storing unit operable to store a plurality of instruction codes, a first instruction pipeline operable to generate a condition satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal satisfies the condition based on the plurality of instruction codes, a second instruction pipeline operable to generate a condition non-satisfaction instruction stream including a plurality of instructions that causes the test pattern outputting unit to output the test pattern to be supplied to the electronic device when the output signal does not satisfy the condition based on the plurality of instru

Abstract: An all solutions automatic test pattern generation (ATPG) engine method uses a decision selection heuristic that makes use of the “connectivity of gates” in the circuit in order to obtain a compact solution-set. The “symmetry in search-states” is analyzed using a “Success-Driven Learning” technique which is extended to prune conflict sub-spaces. A metric is used to determine the use of learnt information a priori, which information is stored and used efficiently during “success driven learning”.

Abstract: An integrated circuit tester is described that utilizes methods of programming parallel coupled Algorithmic Pattern Generators (APGs) to generate test vector sequences and part commands with sub-instruction repeats. This enables simpler test programming and ease of test conversion to new part speed grades, steppings, or part designs. In one embodiment, a sub-instruction repeat is utilized to enable adjustment of the timing of test vector sequences and part commands sent to an integrated circuit device under test (DUT) so that the test can be adjusted for new part speed grades and/or steppings. In another embodiment, a sub-instruction repeats are utilized to enable adjustment of the timing of a memory device inputs, memory commands and test vector sequences so that the test can be adjusted for new memory device speed grades.

Abstract: A system and method for modifying a test pattern to control power supply noise are provided. A portion of a sequence of states in a test sequence of a test pattern waveform is modified so as to achieve a circuit voltage, e.g., an on-chip voltage, which approximates a nominal circuit voltage, such as produced by the application of other portions of the sequence of states in the same or different test sequences. For example, hold state cycles or shift-scan state cycles may be inserted or removed prior to test state cycles in the test pattern waveform. The insertion/removal shifts the occurrence of the test state cycles within the test pattern waveform so as to adjust the voltage response of the test state cycles so that they more closely approximate a nominal voltage response. In this way, false failures due to noise in the voltage supply may be eliminated.

Abstract: The present invention provides a method, an apparatus, and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: Determining a scan vector which would test an integrated circuit (IC) while ensuring counts in respective portions of the IC would not exceed corresponding thresholds. In an embodiment, the threshold represents a number of toggles in the corresponding portion. The toggles can include the transitions that would be caused by the logical operation of the combinatorial elements in the IC as well as the transient glitches caused by arrival of input signals at different time points.

Abstract: Built-in self-test (BIST) devices and methods are disclosed. A BIST section (100) according to one embodiment can include a built-in seed value memory (150) that stores multiple seed values. In a BIST operation, a seed value can be transferred from a built-in seed memory (150) to a test pattern generator (106) to generate multiple test patterns for scan chains (104-0 to 104-n). Successive seed values can be transferred to generate multiple test patterns sets at a clock speed and/or to achieve a desired test coverage.

Abstract: A temperature compensation circuit for effectively compensating the difference of a switching timing due to temperature change of a switching element included in a logic circuit is provided. The temperature compensation circuit includes a temperature detecting section for detecting a value corresponding to the temperature of the switching element, and a correction section for correcting the voltage of a logic signal inputted from a previous circuit to the logic circuit in order to reduce the difference of the switching timing due to the temperature change of the switching element based on the value corresponding to the temperature.

Abstract: Testing capability for an integrated circuit having more than one serializer/deserializer (SERDES) block includes embedding a tester within each block, so that the blocks can be tested independently and concurrently. In one embodiment, a tester includes a functional test controller (FTC) for mode setting and a functional test interface (FTI) for implementing the test procedures. The FTI of each tester is inserted between the SERDES of the same block and core processing logic that is also embedded within the integrated circuit. The FTCs are all interconnected via a test bus that is connected to an input/output controller (IOC) for communication between the testers and an external source, such as a personal computer. Optionally, a built-in-self-tester (BIST) state machine is connected to the test bus.

Abstract: For detecting a failure of a logic circuit 11 provided in a semiconductor integrated circuit due to deterioration with age, or the like, there is provided a reference-producing circuit 12 using a logic different from the logic of the logic circuit 11. The reference-producing circuit 12 produces an abnormal/normal determination reference S for a predetermined output signal out output from the logic circuit 11. The reference-producing circuit 12 is made from only a portion of the logic of the logic circuit 11 or with a logic totally different from the logic of the logic circuit 11 to produce the determination reference S, so that the circuit scale of the reference-producing circuit 12 is smaller than that of the logic circuit 11. The determination reference S from the reference-producing circuit 12 and the output signal out from the logic circuit 11 are compared with each other by a determination circuit 13.

Abstract: Embodiments herein may enable an algorithmic pattern generator (APG) to present iterative values of one or more operational parameters to a device under test (DUT). At each iteration, one or more test patterns may be presented to the DUT. The APG may capture test results from a set of iterations of the operational parameters. The APG may also write values associated with a next operational parameter to be iterated to a test parameter configuration space within the device tester.

Abstract: A test apparatus for testing a device-under-test includes: a pattern generator configured to generate an address signal, a test signal, and an expected value signal; a logical comparator configured to compare an output signal outputted from the device-under-test with the expected value signal. The logical comparator generates a fail signal when the output signal is different from the expected value signal; and a failure analysis memory configured to receive the address signal from the pattern generator and to receive the fail signal from the logical comparator. The failure analysis memory includes: a first storage section configured to store a fail address value that corresponds to the fail signal and a fail data value included in the fail signal as a set of data; and a second storage section configured to read the set of data from the first storage section and to store the fail data value.