Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: System and methods for performing decoding error detection in a storage device are provided. Data bits of a data polynomial may be retrieved from a storage device. The data bits may be arranged in a first order. Error correction may be performed on the retrieved data bits of the data polynomial to produce an error polynomial based on error correction parity information encoded in the data polynomial. Bits of the error polynomial are arranged in a second order that is reverse to the first order. A first remainder of the error polynomial may be computed based on data bits corresponding to the data polynomial arranged in the second order. An error in the error polynomial may be detected based on the computed first remainder.

Abstract: A method for transmitting information data by using a Reed-Muller coding scheme in a wireless communication system is disclosed. The method includes the steps of dividing the information data to first information data and second information data if a bit size O of the information data is equal to or larger than a predetermined number; applying RM coding on each of the first information data and the second information data; concatenating the coded first information data and the coded second information data, and transmitting the concatenated data.

Abstract: In accordance with the teachings described herein, systems and methods are provided for calculating a Cyclic Redundancy Check (CRC) code for a message. A system includes a first CRC calculator and a second CRC calculator. The first CRC calculator is configured to receive a first data block of the message, and to calculate a first CRC value based at least in part on the first data block, the message including the first data block and a second data block. The second CRC calculator is configured to receive the first CRC value and the second data block of the message, and to calculate a second CRC value based on the first CRC value and the second data block, the second CRC calculator being different from the first CRC calculator.

Abstract: An encoding method and an encoder for creating a low-density parity check convolution code (LDDC-CC), sending a signal sequence after subjecting the code to an error-correction using the low-density parity check convolution code, and creating a low-density parity check code of a time-variant period (3g) by linear operations of first to 3g-th (letter g designates a positive integer) parity check polynomials and input data.

Abstract: An encoder and a decoder employ an encoding scheme corresponding to a parity check matrix which is derivable from a bipartite protograph formed of variable nodes and check nodes, with each variable node corresponding to a codeword symbol position. The protograph has a plurality of groups of nodes, each group of nodes comprising both variable nodes and check nodes. Each of the check nodes in a group is of degree 2 and has connections to two variable nodes in the same group. The protograph also has a plurality of check nodes of degree n, where n is the number of said plurality of groups, wherein each of the plurality of check nodes has a connection to a variable node in each group such that the symbol positions in a codeword are interleaved between the groups of nodes.

Abstract: According to one embodiment, an error correction encoding apparatus includes a linear encoder and a low-density parity check (LDPC) encoder. The linear encoder supports a linear coding scheme enabling a parity check to be carried out by a division using a generating polynomial and applies the generating polynomial to input data to obtain linear coded data. The LDPC encoder applies a generator matrix corresponding to a parity check matrix for an LDPC code to the linear coded data to obtain output data. The parity check matrix satisfies Expression (1) shown in the specification.

Abstract: Provided is a decoding apparatus capable of reducing the error rate of the decoding results and also the circuit scale. A computing unit computes a plurality of distances only for a number of code word candidates of code words from demodulated data, the number being smaller than a number of values the code words can express, the code words having a possibility of being transmitted. A decoding unit decodes the code words from the plurality of computed distances. This invention is applicable to a decoding apparatus for Long Term Evolution (LTE).

Abstract: A method of de-mapping non-binary Galois field symbols from physical layer code-words in a data communication system, in which at least one physical layer code-word includes portions mapped from more than one non-binary Galois field symbol is provided. The method includes calculating at least a provisional likelihood estimate for values of a first non-binary Galois field symbol having at least portions within a first physical layer code-word, the calculating including selecting a first number of values of a second non-binary Galois field symbol having at least portions within the first physical layer code-word, the first number forming a subset of the possible values of the second non-binary Galois field symbol.

Abstract: Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

Abstract: An error correction code (ECC) decoder processing data read from a storage media includes a plurality of processing elements for detecting an error in at least one of a plurality of channel data, wherein the plurality of channel data is received via a plurality of channels, and wherein the plurality of processing elements are driven independently from the plurality of channels.

Abstract: Provided is a method for generating codewords. The method comprises the following steps: receiving an information bit; generating a generating matrix in which a size of a column is identical with a length of the information bit, a size of a row is 24 rows, and values of symbols that are elements of the matrix are 0 or 1; modifying the generating matrix by dividing the generated generating matrix into an upper group and a lower group having an identical size and replacing rows so that the number of symbols having a value of 1 in the upper group is identical with the number of symbols having a value of 1 in the lower group; and obtaining inner products from the information bit and each row of the modified generating matrix and generating codewords from remainders obtained by dividing the inner products by 2.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: The ECC circuit includes a Chien search unit configured to determine whether there is an error in each bit of a data sequence. The Chien search unit selects a coefficient of a nonlinear term from among terms of an error locator polynomial as a nonlinear coefficient, separates the error locator polynomial into a first location equation including only linear terms and a second location equation including only nonlinear terms, determines a third location equation by dividing the first location equation by the nonlinear coefficient, determines a fourth location equation by dividing the second location equation by the nonlinear coefficient, and determines whether there is an error for each of the bits by performing an XOR operation on a result of the third location equation using the substitution value and a result of the fourth location equation using an arbitrary element of the error locator polynomial as a substitution value.

Abstract: A data processing system 2 includes an instruction decoder 22 responsive to polynomial divide instructions DIVL.PN to generate control signals that control processing circuitry 26 to perform a polynomial division operation. The denominator polynomial is represented by a denominator value stored within a register with an assumption that the highest degree term of the polynomial always has a coefficient of “1” such that this coefficient need not be stored within the register storing the denominator value and accordingly the denominator polynomial may have a degree one higher than would be possible with the bit space within the register storing the denominator value alone. The polynomial divide instruction returns a quotient value and a remainder value respectively representing the quotient polynomial and the remainder polynomial.

Abstract: A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and generates a corrected data unit by correcting data bit errors in the data unit based on the error correction code if the number of data bit errors in the data unit does not exceed an error correction capacity of the error correction code. Otherwise, the data storage device generates a modified data unit based on the data unit by negating at least one erroneous data bit the data unit based on the bit error indicator and corrects any remaining data bit errors in the modified data unit based on the error correction code.

Abstract: Disclosed is an error correcting method which includes detecting an error of meta data having a seed used to randomize user data; correcting the error of the meta data when the error is detected from the meta data; receiving the user data based upon seed confirmation information associated with an error existence of the seed or an error correction result of the seed; detecting an error of the user data; and correcting the error of the user data when the error is detected from the user data.

Abstract: An automotive sensor reads from memory previously stored back-calculated diagnostic-code values for which a fixed cyclic-redundancy-check (“CRC”) value is valid and transmits the previously stored back-calculated diagnostic-code values read from memory each paired together with the fixed CRC value.

Abstract: A technique of determining a message residue includes accessing a message and simultaneously determining a set of modular remainders with respect to a polynomial for different respective segments of the message. The technique also includes determining a modular remainder with respect to the polynomial for the message based on the set of modular remainders and a set of constants determined prior to accessing the message. The modular remainder with respect to the polynomial for the message is stored in a memory.

Abstract: A method for encoding data using a parity check matrix is disclosed. The method for encoding data using a parity check matrix comprises generating a fourth base matrix by applying a row permutation pattern and a column permutation pattern to rows and columns of a third base matrix, respectively, the third base matrix including a plurality of indexes, each of the plurality of indexes indicating a sub-matrix; generating the parity check matrix by replacing each index of the fourth base matrix with a corresponding sub-matrix; outputting an encoded bit stream by encoding an input bit stream using the generated parity check matrix; and permuting an order of sequences of the encoded bit stream according to an inverse of the column permutation pattern.

Abstract: Various examples are provided for encoding for 100G-KR networking. In one example, among others, a coding method uses certain forward error correcting codes based on a given transcoding method and delivers the codes according to burst interleaving. In another example, a coding method includes receiving source data from a plurality of physical lanes, combining data from the physical lanes to generate a block, transcoding the block and encoding a data stream including the transcoded block.

Abstract: Digital communication coding methods resulting in rate-compatible low density parity-check (LDPC) codes built from protographs. Described digital coding methods start with a desired code rate and a selection of the numbers of variable nodes and check nodes to be used in the protograph. Constraints are set to satisfy a linear minimum distance growth property for the protograph. All possible edges in the graph are searched for the minimum iterative decoding threshold and the protograph with the lowest iterative decoding threshold is selected. Protographs designed in this manner are used in decode and forward relay channels.

Abstract: Provided is an error check and correction (ECC) circuit which includes a Chien search unit configured to determine whether there is an error in a data string. The Chien search unit includes a circuit configured to calculate a first bit string by multiplying a plurality of elements of Galois Field GF(2n) and a value of (n-k)-bit, and calculate a second bit string by multiplying the plurality of elements and a value of k-bit; and a plurality of Chien search circuits configured to combine the first bit string and the second bit string to calculate the arbitrary element. The plurality of Chien search circuits are arranged in a matrix along a row direction and a column direction. The first bit string is provided in the row direction or the column direction, and the second bit string is provided in a direction different from the direction of the first bit string.

Abstract: Described embodiments provide a wideband code division multiple access (W-CDMA) system that employs a rate matching rule having a modified puncturing algorithm. The modified puncturing algorithm defines the input variables of the rate matching rule in a manner that provides for identification of relations between non-punctured data bit position addresses in the output data stream through an iterative process, from which absolute bit position addresses of non-punctured output bits might then be generated. A counter, in accordance with instruction generated by a processor or state machine, for example, might implement the modified puncturing algorithm on an input string of bits to provide an output string of bits based on the absolute bit position addresses of non-punctured output bits, thereby providing for rate matching in the communications channel.

Abstract: An electronic device comprises an error correction coding device. The error correction coding device comprises a parity code generator. This generator is a circuit for computing a remainder polynomial by dividing a user data polynomial by a generator polynomial and generating a parity code from this remainder polynomial. This generator computes the remainder polynomial by dividing and inputting either a bit string comprising coefficients of the generator polynomial, or a bit string comprising coefficients of the generator polynomial and a bit string comprising coefficients of the generator polynomial, and dividing a minimal unit multiple times based on either a division width of the user polynomial or a division width of the user polynomial and the generator polynomial, and outputs a bit string comprising the coefficient of this remainder polynomial.

Abstract: A partial voltage level read is made on memory cells of a solid state memory device during a voltage settling time after the memory cells are charged (e.g., by a pulse from a charge pump). Digital values representing partial voltage levels are checked for errors (e.g., by an error correction code (ECC) engine). If the values can be corrected, then the values are released for host access. If the values cannot be corrected, then a full voltage read is performed on the memory cells after the voltage levels have substantially settled. Digital values corresponding to the full voltage reads can be released for host access. The use of partial voltage reads results in faster read of solid state memory devices.

Abstract: A method for identifying a corrupted received signal that includes symbols is described. Each symbol may have a value of a Galois field associated therewith. The receiver may be configured to store a logarithm of normalized probability mass functions and corresponding Galois field values for each of the symbols. The normalized probability mass functions may be normalized with respect to a greatest probability mass function of a given symbol. The method may include comparing, for each symbol, a logarithm of normalized probability of an n-th best probability value with a respective threshold, counting a number of the logarithms that exceed the respective threshold and generating, for each symbol, a score corresponding to the number. The method may also include calculating a moving average of the scores, and comparing the moving average with an output threshold and flagging a just received symbol as corrupted based upon the comparison.

Abstract: To store bits in one or more cells, an adaptive mapping of bits to ranges of a physical parameter of the cell(s) is provided, in accordance with respective initial values of the physical parameter, by steps including encoding the bits as a codeword by partitioning the bits into subsets and finding a factor bit string such that the codeword is a concatenation of the factor bit string and separate Galois field products of all the subsets with the factor bit string. The initial values of the physical parameter are adjusted accordingly as needed.

Abstract: A decoding device comprises two check node processing devices of feedback shift register type, each of which node processing includes a plurality of registers and a plurality of comparator circuits. A multiplexer and a demultiplexer switch between the two check node processing devices, and a memory holds the two sorts of data. The comparator circuits are interposed between registers of the check node processing device.

Abstract: A computer-implemented method and computer program product comprising optimal, systematic q-ary codes for correcting all asymmetric and symmetric errors of limited magnitude are provided.

Abstract: A method and system for storing data in a multi-level cell (MLC) flash memory device are described. The method includes receiving data for storage in the flash memory device, the flash memory device comprising an array of MLC flash memory cells, and encoding the received data into non-binary symbols according to a trellis-coded modulation scheme. The method further includes writing each of the non-binary symbols to a respective flash memory cell set, wherein each flash memory cell set comprises a plurality of MLC flash memory cells.

Abstract: A matrix multiplier multiplies the signal output from a first adder by an inverse matrix T?1 of a partial matrix T of a parent parity check matrix, and outputs the multiplication result to a first switch. The output of the matrix multiplier becomes a second parity vector P2. A second switch is switched on at a transmission time of the information word vector ‘s’, a third switch is switched on at a transmission time of the first parity vector P1, and the first switch is switched on at a transmission time of the second parity vector P2. When a puncturing scheme is applied to the parent parity check matrix, a controller controls the first and second switches to puncture the parity according to the corresponding coding rate.

Abstract: Methods and circuits process a data block of first bits. A circuit includes a register and a parallel combiner. The register is configured to store second bits. The second bits are iteratively a partial parity for each of multiple frames of the data block. The parallel combiner is coupled to the register and configured to generate a combination of bits from third bits and the second bits from the register. These third bits are iteratively those of the first bits within each of the frames of the data block. The circuit also includes respective exclusive-or circuits associated with the second bits. These exclusive-or circuits are coupled to the parallel combiner and the register. The respective exclusive-or circuit for each second bit is configured to generate the second bit from the combination of bits.

Abstract: A method for decoding an ECC, in a decoder that includes at least first and second root search units, includes accepting at least first and second Error Locator Polynomials (ELPs) that have been computed over respective first and second code words of the ECC. A criterion depending on the ELPs is evaluated. One of first and second modes is selected based on the criterion. One or more first roots of the first ELP and one or more second roots of the second ELP are found using the selected mode, and the first and second code words are decoded using the first and second roots. In the first mode, the first and second root search units are combined and simultaneously find the first roots. In the second mode, the first and second root search units operate separately, and simultaneously identify the first roots and the second roots, respectively.

Abstract: An error locator polynomial is incrementally generated by flipping a bit pattern Yi at a symbol Xi an initial dataword to obtain a first test error pattern. A bit pattern Yj at a symbol Xj within the first test error pattern is flipped to obtain a second test error pattern, wherein i?j.

Abstract: A system receives a first word on which to perform error correction; identifies combinations in which encoded bits, within the first word, can be inverted; generates candidate words based on the first word and the combinations; decodes the candidate words; determines distances between the decoded words and the first word; selects, as a second word, one of the decoded words associated with a shortest distance; compares the second word to the first word to identify errors within the first word; generates a value to cause a reliability level of the first word to increase when a quantity of the errors is less than a threshold; generates another value to cause a reliability level of the first word to decrease when the quantity of the errors is not less than the threshold; and outputs a third word based on the first word, and the value or the other value.

Abstract: An apparatus of processing polynomials includes at least one reconfigurable module and an encoder controller. The reconfigurable module includes a plurality of linear feedback shift registers. The encoder controller can control the reconfigurable module to factor a generator polynomial into a factorial polynomial. In the reconfigurable module, the linear feedback shift registers can register a plurality of factors of the factorial polynomial respectively.

Abstract: An apparatus for performing sequence detection on a stream of incoming bits comprises a memory and circuitry coupled to the memory. The circuitry is operative, for each bit of the stream of incoming bits, to overwrite a first binary number presently stored in the memory with a second binary number, and to provide an output indicative of when the second binary number is equal to a predetermined value. The output indicative of when the second binary number is equal to the predetermined value is, in turn, indicative of when a binary number constructed by the stream of incoming bits is divisible by a prescribed integer.

Abstract: A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: ?(n)=f1n?fnn2 mod K, where the QPP coefficients f1 and f2 are designed to provide good error performance for a given block length K.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first linear error-correcting code in systematic form and the data chunks. For each of m rows of the data chunks, one or more split row code chunks are generated using the data chunks of the row, wherein the split row code chunks are generated so that a linear combination of m split row code chunks from different rows forms a first word code chunk of a first codeword including the data chunks and the word code chunks. The rows of data chunks and the split row code chunks and the word code chunks are stored.

Abstract: Single CRC polynomial for both turbo code block CRC and transport block CRC. Rather than employing multiple and different generation polynomials for generating CRC fields for different levels within a coded signal, a single CRC polynomial is employed for the various levels. Effective error correction capability is achieved with minimal hardware requirement by using a single CRC polynomial for various layers of CRC encoding. Such CRC encoding can be implemented within any of a wide variety of communication devices that may be implemented within a wide variety of communication systems (e.g., a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system, etc.). In addition, a single CRC check can be employed within a receiver (or transceiver) type communication device for each of the various layers of CRC of a received signal.

Abstract: A method and a system of multidimensional encoding and/or decoding to be processed by a computer or a digital hardware system. The method utilizes an error correcting code which is chosen from the group comprising RS, BCH, BCH algebraic, RM (Reed-Muller), among others. The method is carried out by the steps of attribution of a dimension for each bit in the symbols set of a message, with symbols with at least two bits, so the error correcting code will be performed over the dimensions and not over the symbols; grouping of the dimensions in the same position of the origin symbols in a new symbol, so the symbols will be treated as symbols in both stages of the code, in that the error correcting code is performed in every dimension; and processing of each dimension in parallel or in an independent manner, using an error correcting code.

Abstract: Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first encoded group of data are then encoded using a second layer of code to form a second encoded group of data. A processor may request access to an individual portion of the group of data. The encoded version of the requested individual portion is retrieved from memory and decoded using the second layer of code to recover the requested individual portion. If the recovery of the requested individual portion fails, the remaining encoded portions of the group are retrieved from memory and decoded using the first layer of code to recover the requested individual portion.

Abstract: A memory system that facilitates probabilistic error correction for a failed memory component with partial-component sparing. The memory system accesses blocks of data, each block including an array of bits logically organized into R rows and C columns. The C columns include (1) a row-checkbit column containing row-parity bits for each of the R rows, (2) an inner-checkbit column containing X=R?S inner checkbits and S spare bits, and (3) C-2 data-bit columns containing data bits. Each column is stored in a different memory component. When the memory system determines that a memory component has failed, the memory system examines the pattern of errors associated with the failed component to determine if the failure affects a partial component associated with S or fewer bits. If so, the memory system corrects and remaps data bits from the failed partial component to the S spare data bits in the inner-checkbit column.

Abstract: Circuitry for, in p parallel streams, searching a codeword having n symbols for roots of a cyclic code polynomial having a number of terms includes a plurality of multipliers, a source of constants derived from roots of the polynomial, and at least one counter that supplies an index. For each received symbol of the codeword, the multipliers multiply respective terms of the polynomial for a previous received symbol by constants from the source of constants, the counter advances to select respective products of the constants and the respective terms for the previous received symbol.

Abstract: A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.

Abstract: Data storage techniques and solutions simultaneously provide efficient random access to information and high noise resilience. The amount of storage space utilized is only slightly larger than the size of the data. The solution is based on locally decodable error-correcting codes (also referred to as locally decodable codes or LDCs). Locally decodable codes are described herein that are more efficient than conventional locally decodable codes. Such locally decodable codes are referred to as “multiplicity codes”. These codes are based on evaluating multivariate polynomials and their derivatives. Multiplicity codes extend traditional multivariate polynomial based (e.g., Reed-Muller) codes. Multiplicity codes inherit the local decodability of Reed-Muller codes, and at the same time achieve substantially better parameters.

Abstract: Storing data in memory using wear-focusing techniques for improved endurance. A method for storing the data includes receiving write data to be written into a memory that is logically divided into a plurality of regions. The plurality of regions includes a first region and a second region that are implemented by the same memory technology. The memory is subject to degradation as a result of write operations. The write data is classified as dynamic data or static data. The write data is encoded using a first type of encoding in response to the write data being classified as dynamic. The write data encoded using the first type of encoding is stored in the first region of the memory. The write data is encoded using a second type of encoding and stored in the second region of the memory in response to classifying the write data as static data.