Abstract: An apparatus generally having a port, a first circuit and a second circuit is disclosed. The port may be configured to receive a current length of a codeword. The current length may be less than a maximum length of the codeword that the apparatus is designed to decode. The first circuit may be configured to calculate in parallel (i) a sequence of intermediate syndromes from the codeword and (ii) a sequence of correction values based on the current length. The second circuit may be configured to generate a particular number of updated syndromes by modifying the intermediate syndromes with the correction values. The particular number is generally twice a maximum error limit of the codeword.

Abstract: Embodiments of the present disclosure describe devices, apparatus, methods, computer-readable media and system configurations for processing elementary check nodes associated with an iterative decoder in a manner that conserves computing resources. In various embodiments, first and second sets of m tuples may be received, e.g., as input for the elementary check node. Each tuple may include a symbol and a probability that the symbol is correct, and the first and second sets of m tuples may be sorted by their respective probabilities. In various embodiments, less than all combinations of the first and second sets of m tuples may be computed for consideration as output of the elementary check node, and some computed combinations may be eliminated from consideration as output. In various embodiments, the elementary check node may output a set of m output tuples with the highest probabilities. Other embodiments may be described and/or claimed.

Abstract: An apparatus generates a checksum for a payload having a number of payload symbols. The apparatus includes a coder for coding the payload. The coder is configured to combine a current payload symbol and a previous coding symbol or an initialization symbol to obtain a combined symbol, and map the combined symbol using a mapping rule to obtain a current coding symbol. The mapping rule is based on a power of two or more of a companion matrix of a characteristic polynomial of a linear feedback shift register. The apparatus is configured such that the checksum corresponds to the current coding symbol, when the number of payload symbols is processed by the coder, the number being one or greater than one.

Abstract: The present invention relates to using a barrel shifter in a cyclic shift device for an LDPC decoding device, a television receiver, and/or a reception system, whereby reduction in size of the device can be realized.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data encoding.

Abstract: Described herein are an apparatus, system, and method for encoder assisted decoding of linear systematic block codes. The apparatus comprises a first logic unit to receive a codeword from a memory, the codeword having a data portion and a corresponding parity portion; an encoder to encode the data portion of the received codeword and to generate a corresponding parity of the data portion of the received codeword; a second logic unit to generate a first parity portion from the corresponding parity portion of the codeword received by the first logic unit and the corresponding parity portion generated by the encoder; and a correction unit to correct the data portion of the codeword via the generated first parity portion.

Abstract: The codec includes an encoding/decoding operation module and a basic matrix storage module. In the stored basic matrix Hb, for all girths with length of 4, any column element of i, j, k or l constituting the girths in anti-clockwise or clockwise always satisfies inequality: (i?j+k?1) mod z?0, wherein z is the extension factor. When generating the basic matrix, firstly the number of rows M, number of columns N, and weight vectors of the rows and columns are determined, an irregularly original basic matrix is constructed; then the position of ‘1’ is filled by a value chosen from set {0, 1, 2, . . . , z?1} to obtain the basic matrix Hb. The basic matrix Hb obtained by storing constitutes the desired encoder/decoder. The encoder/decoder according to the present invention can effectively eliminate error-floor phenomenon of LDPC codes and accelerate the falling speed of BER curve.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for skewed orthogonal coding techniques. In one aspect, a method includes receiving a block of data comprising a plurality of data chunks. One or more rows of word code chunks are generated using a first error-correcting code in systematic form and the plurality of data chunks. For each row of a plurality of rows of the data chunks, one or more row code chunks for the row are generated using a second error-correcting code in systematic form and the data chunks of the row. The rows of data chunks and the row code chunks and the rows of word code chunks are stored.

Abstract: Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.

Abstract: Disclosed herein is a coding apparatus handling quasi-cyclic codes in which a given code word cyclically shifted by p symbols provides another code word, wherein parallel processing is executed in units of mp (a multiple of p) symbols; mp generator polynomials are used; and the generator polynomials gj(x) are selected such that a coefficient of degree deg(gi(x)) of x becomes zero for all gi(x) lower in degree than that and circuits in which these generator polynomials gj(x) are combined are connected with each other.

Abstract: Embodiments of the present invention provide high density, multi-level memory. Thus, various embodiments of the present invention provide a memory apparatus in accordance with various embodiments of the present invention includes a memory block comprising a plurality of cells, each cell adapted to operate with multi-level signal. Such a memory apparatus also includes a channel block adapted to code data values in accordance with a coding scheme that favorably effects a distribution of the multi-levels of the multi-level signals, and to output the corresponding multi-level signals of the coded data values to the memory block. Other embodiments may be described and claimed.

Abstract: Techniques to support low density parity check (LDPC) encoding and decoding are described. An apparatus includes at least one processor and a memory coupled to the at least one processor. The at least one processor is configured to encode or decode a packet based on a base parity check matrix and a set of lifting values. In a particular embodiment, the set of lifting values is limited to lifting values that are each a different power of two. The memory is configured to store parameters associated with the base parity check matrix.

Abstract: A method is for transmitting a binary information word (MI) coded on r bits to which is attached a redundancy (CRC) coded on s bits, s and r being integers. The redundancy (CRC) signals the appearance of erroneous bits after the transmission, and is obtained by carrying out a Euclidian division of the information word (MI) to be transmitted by a generator polynomial coded on at most s bits. The generator polynomial is chosen so that it satisfies at least one of the following conditions, namely that the Hamming weight of the multiples of the generator polynomial is greater than or equal to a chosen threshold, or the generator polynomial allows the detection of at least 2s-1-3 consecutive erroneous bits.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data structures, groups or streams.

Abstract: An error-correcting coding method generates code words of m bits from useful data blocks of n bits. The method adds k check bits to a block of n useful data bits in order to generate a code word of m=n+k bits, said check bits being defined according to the combination rules defined by a parity matrix H consisting of binary elements and having k rows and m columns such that H·V=0, V being a column matrix whose m elements are the m bits of the code word to be generated. The k check bits are separated into two groups, on the one hand a group of k1 bits called total parity bits PT and on the other hand a group of k2 bits called conventional check bits VC, the values of k, k1 and k2 satisfying the conditions k=k1+k2 and k>k1>2, the matrix H whose columns can be swapped being broken down into six submatrices A, B, C, D, E and F. Another method detects multiple errors in code words generated by the coding method.

Abstract: Methods and apparatus for generating cyclic redundancy checks (CRCs). In one aspect of the present invention, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a selected cyclic redundancy check generator polynomial, at least one cyclic redundancy check is calculated based upon a first subset of the plurality of bits with a certain bit ordering, and at least another cyclic redundancy check is calculated based upon a second subset of the plurality of bits with a different bit ordering. The second subset of bits may overlap with the first subset of bits. In another aspect, a plurality of cyclic redundancy checks are calculated based upon a plurality of bits by using a plurality of different cyclic redundancy check generator polynomials.

Abstract: A system and method for transmitting and receiving acknowledgement information are provided. A method for communications device operations includes determining a hybrid automatic repeat request (HARQ) response for each CC in a set of configured CCs, thereby producing a set of HARQ responses, generating an information vector from the set of HARQ responses, encoding the information vector, and transmitting the encoded information vector. A sub-vector of one or more bits selected from the information vector is assigned a fixed vector value independent of HARQ responses for CCs not in a set of CCs when the set of CCs is not empty, where the set of CCs comprises at least one CC whose HARQ response is equal to DTX.

Abstract: To feedback MIMO channel conditions, a codeword from a codebook is selected. To reduce signalling, the codewords are organized into codeword subsets. The receiver signals an index of a codeword into a current codeword subset previously made known to the transmitter. The current codeword subset is adaptively selected based on a threshold criterion. For example, if the best codeword from the current codeword subset is not sufficiently similar to the best codeword in the full codebook, a switch in the codeword subset is made.

Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.

Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

Abstract: An apparatus for correcting at least one bit error within a coded bit sequence includes an error syndrome generator and a bit error corrector. The error syndrome generator determines the error syndrome of a coded bit sequence derived by a multiplication of a check matrix with a coded bit sequence.

Abstract: A device and method of detecting and correcting errors in data having a control unit, a coefficient computation unit, an error computation unit, and an error detection and correction unit, where errors such as garbled data, missing data, and added data are either detected and corrected or just detected.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.

Abstract: The present invention is a configurable binary BCH encoder having a variable number of errors. The encoder may implement a universal multipole block which may be configured for receiving an error number input, which may include a maximum error number limit for the encoder, and for calculating a plurality of error coefficients based on the error number input. The encoder may be further configured for receiving a plurality of information bits of an information word. The encoder may be further configured for transmitting/outputting a first (ex.—unmodified) subset of the information bits as an encoder output. The encoder may be further configured for calculating a plurality of parity bits based on a second subset of the information bits and the error coefficients. The encoder may be further configured for transmitting/outputting the calculated parity bits as part of the encoder output.

Abstract: An error detection module includes a known-syndrome computing unit, an unknown-syndrome computing unit, and an error detection unit. The known-syndrome computing unit is operable to convert a received signal into a target signal, to obtain known syndromes based upon the target signal, and to generate an errata-locator polynomial based upon an erasure-locator polynomial and the known syndromes. The unknown-syndrome computing unit is operable to compute unknown syndromes based upon the errata-locator polynomial and the known syndromes. The error detection unit is operable to obtain a syndrome set that includes the known syndromes and the unknown syndromes, to obtain an error detection signal according to the syndrome set, and to provide an error correction module coupled thereto with the syndrome set and the error detection signal for enabling the error correction module to correct an error of the received signal.

Abstract: Embodiments of systems and methods for implementing a file system utilizing a media library are disclosed. In particular, embodiments may present a network based file system to one or more host devices. These host devices may utilize the network based file system to organize, store, read or perform other operations in association with files. These files may be managed in conjunction with the media library.

Abstract: Efficient secure password protocols are constructed that remain secure against offline dictionary attacks even when a large, but bounded, part of the storage of a server responsible for password verification is retrieved by an adversary through a remote or local connection. A registration algorithm and a verification algorithm accomplish the goal of defeating a dictionary attack. A password protocol where a server, on input of a login and a password, carefully selects several locations from the password files, properly combines their content according to some special function, and stores the result of this function as a tag that can be associated with this password and used in a verification phase to verify access by users.

Abstract: Data communication, with improved error detection, of a signal having a plurality of data blocks, by: error checking a received data block in a first sequence using a first polynomial, beginning with a first predetermined initial error checking state, producing a first checksum; error checking the received data block in a second sequence using a second polynomial, using the first checksum as a second predetermined initial error checking state, producing a second checksum; comparing the second checksum to the first predetermined initial error checking state to detect errors in the data communication; and repeating the above steps for sequential data blocks of the data communication, wherein the first polynomial is an inverse of the second polynomial.

Abstract: There is provided a method of encoding and decoding data using an error control code having a codebook G. The codebook G is a sub-codebook of a codebook P. Each codeword g in the sub-codebook G has an autocorrelation amplitude that is different from and higher than each correlation amplitude between g and each of the other codewords in the sub-codebook G. In one specific embodiment in which the codebook P is that of a Reed-Muller code, using G instead of P reduces the likelihood of the presence of more than one maximum correlation amplitude when computing the non-coherent decision metric during decoding.

Abstract: A method, system and device for monitoring error code of CPRI link are disclosed. The method comprises: a CPRI link data transmitting end forming data to be transmitted into frames, outputting data, and calculating to obtain FCS of each frame; the CPRI link data transmitting end adds FCS of a former frame into FCS field of a current frame when forming frame; a CPRI link data receiving end splitting frame of received frame data to obtain FCS of the former frame carried in the current frame, calculating received frame data to obtain FCS of the current frame, caching FCS of the current frame, comparing FCS of the former frame which is carried in the current frame with cached FCS of the former frame, and judging CPRI link has error codes if the comparison result is inconsistent. Error code condition of CPRI link can be monitored without influencing normal service operation.

Abstract: A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

Abstract: A data processing system includes a memory configured to receive data and an encoder configured to encode data being transferred to the memory. The encoder includes an outer encoder configured to generate an outer codeword by encoding the data being transferred to the memory, and an inner encoder configured to generate a plurality of inner codewords by encoding the outer codeword.

Abstract: Methods include receiving data and an ECC code read from a memory array, generating an ECC code from the received data, and determining whether the received data is corrupted by evaluating the generated ECC code against the ECC code read from the memory array. If the received data is determined to be corrupted, a correction algorithm and a recorded likely state of a known bad/questionable bit of the received data may be used to correct error in the received data. Alternatively, if the received data is determined to be corrupted, the correction algorithm and a recorded location of a known bad/questionable bit of the received data may be used to correct error in the received data.

Abstract: A redundant code generation method includes: dividing original data into data strings; dividing each data string into a number of bit strings that accords with an extended Galois field operation; storing each of the bit string in a different memory area of a memory; and executing an exclusive OR operation among vectors, which are extracted from the respective bit strings stored in the memory, according to an operational expression to compute bit strings that make up redundant code data strings without carrying out a bit shift operation within the vectors. A predetermined plural number of bits is taken as a data unit and the number of bits as elements constituting each vector is equal to the data unit. The operational expression includes a companion matrix of a primitive polynomial of the Galois field and defined the generation of the redundant code data strings.

Abstract: Disclosed are a method and apparatus for detecting frame boundary for a data stream received at an Ethernet FEC layer, as well as a decoding method and system for the same. The apparatus for detecting frame boundary may comprise: a buffer for buffering data in a data stream, a length of the data in the buffer being greater than one frame; a syndrome generator for calculating a current syndrome based on a first data item, a second data item, and an intermediate calculation result of a previous syndrome, wherein the first data item is the last bit in a current candidate frame, and the second data item is a bit preceding the current candidate frame; and a comparator for using the current syndrome to check whether the bit preceding the current candidate frame is a frame boundary of an Ethernet FEC layer. The apparatus for detecting frame boundary can improve the speed of frame boundary detection.

Abstract: An encoding/decoding apparatus and method using a low-density parity-check code (LDPC code) is disclosed. Basic column group information, serving as a set of information regarding positions of rows with weight 1, is extracted from a reference column in each column group of a predetermined parity-check matrix. Column group information transforms the positions of rows with weight 1 into positions whose lengths are within a required parity length. A parity-check matrix is generated according to the generated column group information. Data is encoded or decoded based on the generated parity-check matrix.

Abstract: The present invention relates to channel decoding and provides ways and means for improved channel decoding of data frames. The frame has been channel encoded and transmitted to a receiver. The frame includes a part with information that is unknown to the receiver and another part with information for which the receiver generates at least one data hypothesis predicting its information content. The receiver performs a hypothesis-based decoding of the received encoded frame, wherein the at least one data hypothesis is used to improve a probability of successful decoding. The invention may advantageously be used to improve decoding of frames containing short control messages with fill bits, e.g. acknowledgement messages.

Abstract: Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

Abstract: Methods and systems are disclosed herein for generating parity information for using information in a low-density parity check (LDPC) encoder. A quasi-cyclic LDPC generator matrix K can be generated based on the non-invertible parity-check matrix H. Parity information can be generated by the LDPC encoder based at least in part on the user information, the non-invertible parity check matrix H, and the quasi-cyclic LDPC generator matrix K.

Abstract: The invention provides a method for encoding and decoding an error correction code. First, raw data is received and then divided into a plurality of data segments. A plurality of short parities corresponding to the data segments is then generated according to a first generator polynomial. The short parities are then appended to the data segments to obtain a plurality of short codewords. The short codewords are then concatenated to obtain a code data. A long parity corresponding to the code data is then generated according to a second generator polynomial, wherein the first generator polynomial is a function of at least one minimum polynomial of the second generator polynomial. Finally, the long parity is then appended to the code data to obtain a long codeword as an error correction code corresponding to the raw data.

Abstract: The apparatus for appending CRC to the data or signaling to be transmitted in the communication systems is proposed in present invention. If the length of the CRC-bit sequence is 16, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 18, one of the CRC generation polynomials listed in present invention can be adopted. If the length of the CRC bit sequence is 20, one of the CRC generation polynomials listed in present invention can be adopted. With the optimized CRC generation polynomials proposed in present invention, mistakes in signaling detection can be effectively reduced so that system spectrum utility can be improved.

Abstract: In one embodiment, an LDPC decoder has a controller and an extrinsic log-likelihood (LLR) value generator. The extrinsic LLR value generator is selectively configurable to operate in either (i) a non-averaging mode that updates extrinsic LLR values without averaging or (ii) an averaging mode that updates extrinsic LLR values using averaging. Initially, the extrinsic LLR value generator is configured to generate non-averaged extrinsic LLR values, and the decoder attempts to recover an LDPC-encoded codeword using the non-averaged extrinsic LLR values. If the decoder is unable to recover the correct codeword, then (i) the controller selects the averaging mode, (ii) the extrinsic LLR value generator is configured to generate average extrinsic LLR values, and (iii) the decoder attempts to recover the correct codeword using the average extrinsic LLR values. Averaging the extrinsic LLR values may slow down the propagation of erroneous messages that lead the decoder to convergence on trapping sets.

Abstract: A method and an apparatus that has Chien search capabilities, the apparatus includes a first hardware circuit and a second hardware circuit. The first hardware circuit evaluates an error locator polynomial for a first element of a finite field over which the error locator polynomial is defined to provide a first set of intermediate results and a first Chien search result and provides the first set of intermediate results to the second hardware circuit; the second hardware circuit evaluates the error locator polynomial for a second element of the finite field to provide a second Chien search result in response to the first set of intermediate results. The first hardware circuit may be substantially bigger than the second hardware circuit and the first element may differ from the second element.

Abstract: A method for recovering transmission errors, comprising: receiving a data packet comprising an error detection code associated to data contained in the packet, wherein the data associated to the error detection code comprises primary data and secondary data, checking the error detection code of the received packet to detect an erroneous state of the associated data, when the erroneous state is detected, determining a finite set of candidate values for the primary data and, for each values of the set: determining a marginal likelihood of the candidate value as a function of the error detection code of the received packet, determining a first correlation between the primary data of the received packet and the candidate value, and selecting a corrected value for the primary data among the set of candidate values as a function of said marginal likelihoods and said first correlations.

Abstract: A method of communicating information includes receiving a data stream from the host computer, the data stream including a plurality of bytes, one or more bytes of the plurality of bytes being associated with obtaining medical related information, and parsing one or more bytes in the data stream at the sensor device. As a result of parsing the one or more bytes, the method includes identifying a type of medical related information, obtaining the medical related information from the sensor device, and sending the medical related information to the host computer. The parsing of the one or more bytes in the data stream is performed using a single pass through the data stream, one or more data validity checks being performed during the single pass, the medical related information being obtained after the data stream is parsed in the single pass through the data stream.

Abstract: An error detection coding processing section of the radio base station performs an error detection coding process with data including both first control data to be used for receiving a downlink signal and second control data to be used for sending an uplink signal as a unit. A sending section sends data on which the error detection coding process has been performed by the error detection coding processing section to the mobile station.

Abstract: A method for decoding an Error Correction Code (ECC) includes accepting coefficients, including at least first and second coefficients, of an Error Locator Polynomial (ELP) that is defined over a vector space and has at least one root that is indicative of a location of an error in a set of bits, which represent data that has been encoded with the ECC. The first coefficient is represented using a first basis of the vector space, and the second coefficient is represented using a second basis of the vector space, different from the first basis. Using processing circuitry, the root of the ELP is identified by applying algebraic operations to the coefficients, such that the algebraic operations are applied to the first coefficient using the first basis, and to the second coefficient using the second basis. The error is corrected responsively to the identified root of the ELP.