Abstract: In accordance with the teachings described herein, systems and methods are provided for calculating a Cyclic Redundancy Check (CRC) code for a message. A system includes a first CRC calculator and a second CRC calculator. The first CRC calculator is configured to receive a first data block of the message, and to calculate a first CRC value based at least in part on the first data block, the message including the first data block and a second data block. The second CRC calculator is configured to receive the first CRC value and the second data block of the message, and to calculate a second CRC value based on the first CRC value and the second data block, the second CRC calculator being different from the first CRC calculator.

Abstract: Methods, apparatus, and fabrication processes relating to implementing cyclic redundancy checks (CRCs) in processors, such as CRC32 instructions in x86 computer architectures. A method may comprise extracting a first CRC value from a data packet, performing a carryless operation upon the data packet to determine a second CRC value, and determining that a data error is present in the data packet when the first and second CRC values do not match.

Abstract: Systems, methods, apparatus, and techniques are presented for processing a codeword. A Reed-Solomon mother codeword n symbols in length and having k check symbols is received, and the n symbols of the received Reed-Solomon mother codeword are separated into v Reed-Solomon daughter codewords, where v is a decomposition factor associated with the Reed-Solomon mother codeword. The v Reed-Solomon daughter codewords are processed in a respective set of v parallel processes to output v decoded codewords.

Abstract: According to one embodiment, a memory controller in an embodiment includes an encoding unit configured to generate a first parity group from first group data including first and second unit data using G1 (x), generate a second parity group from second group data including third and fourth unit data using G1 (x), and generate a third parity group from the first and second group data and the first and second parity groups using G2 (x), a root of which continues form a root of G1 (x). The memory controller writes the first to fourth unit data and the first to third parity groups in different pages of a nonvolatile memory.

Abstract: According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N?J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J?L) rows×qL columns.

Abstract: A dual redundant process controller is provided. The controller comprises a process control application that executes on a first and a second module. When executed by the first module, a first application instance writes a first synchronization information to the second module, reads a second synchronization information from the first module, and, when the second disagrees with the first synchronization information after passage of a time-out interval, performs a resynchronization function; and wherein, when executed by the second module, the second application instance writes the second synchronization information to the first module, reads the first synchronization information from the second module, and, when the first disagrees with the second synchronization information after passage of the time-out interval, performs the resynchronization function.

Abstract: According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1<=s<t). The search processing unit calculates the root of the error position polynomial, with a concurrency of computation being “1”, when the number of error bits exceeds the predetermined value s.

Abstract: Systems, methods, apparatus, and techniques are provided for decoding a codeword. A plurality of syndrome values is received corresponding to a received codeword and a value of an error locator polynomial corresponding to the received codeword is initialized. The value of the error locator polynomial is iteratively updated by processing the plurality of syndrome values, where each iterative update includes determining a current degree of the error locator polynomial and terminating the iterative updating in response to a determination that the current degree of the error locator polynomial exceeds a threshold value.

Abstract: An encoder provides (2t?1) redundant symbols in a sequence of n coded symbols, and a decoder corrects up to t erroneous symbols in the sequence of n coded symbols corrupted by a plurality of symbol errors. The decoder uses an improved decoding method, the method solving a plurality of matrix equations, each matrix equation associated with a hypothetical location of error. By monitoring a plurality of solutions associated with hypothetical locations of error, a processor determines the actual number of errors, the locations of the erroneous symbols in the sequence of n symbols, and the erroneous symbol value at each error location. The improved decoder includes erasure processing and a correct symbol determination method similar to erasure processing.

Abstract: According to one embodiment, an error detecting device includes a syndrome processor, an error locator polynomial generator, and a search processor. The syndrome processor is configured to generate syndrome values based on received data. The error locator polynomial generator is configured to generate coefficients for an error locator polynomial based on the syndrome values. The search processor configured to detect an error location by calculating a root of the error locator polynomial. The search processor has a clock controller, a buffer, a polynomial generator, and a first judging module. The clock controller is configured to output or stop a clock signal according to at least one of the coefficients. The buffer is configured to drive the clock signal outputted form the clock controller. The polynomial generator is configured to calculate a part of the error locator polynomial in synchronization with the clock signal driven by the buffer.

Abstract: Integrated circuits with a memory array may include error checking circuitry for detecting, locating, and correcting soft errors in the memory array. The error checking circuitry may include row cyclic-redundancy-check (CRC) circuits each of which is operable to receive bits from respective groups of memory elements in the array and may also include an array CRC circuit. In one embodiment, the row CRC circuits compute CRC values based on bits stored in each of the memory elements in the respective groups of memory without the use of the array CRC circuit. After all of the columns have been read out, the array CRC circuit may be used to combine the CRC values from the different row CRC circuits. In another embodiment, the array CRC circuit may update the array CRC value each time the row CRC circuits update their CRC values in response to selecting a new column for readout.

Abstract: A method, a codebook, and a Base Station (BS) for precoding are provided. The precoding method includes: obtaining a total uplink power of a User Equipment (UE); if the total uplink power is greater than ¾ of a rated total transmit power of antennas, selecting a codeword from a first codebook with imbalanced power between layers; otherwise, selecting a codeword from the first codebook and a second codebook with balanced power between layers, so as for precoding data to be transmitted according to the selected codeword.

Abstract: Systems and methods are provided for recovering data stored in memory. A group of data is encoded using a first layer of code to form a first encoded group of data. Individual portions of the first encoded group of data are then encoded using a second layer of code to form a second encoded group of data. A processor may request access to an individual portion of the group of data. The encoded version of the requested individual portion is retrieved from memory and decoded using the second layer of code to recover the requested individual portion. If the recovery of the requested individual portion fails, the remaining encoded portions of the group are retrieved from memory and decoded using the first layer of code to recover the requested individual portion.

Abstract: A coding device includes: an inspection matrix generating module that generates a block inspection matrix; and a coding module that generates and outputs a code word from an input message by the inspection matrix. The inspection matrix generating module includes: a degree-allocation unit that prescribes function values of the block inspection matrix by the coefficients of a self-reciprocal polynomial expression; a weight distribution determination unit that prescribes the number of components that are non-zero matrices among the components of each block of the block inspection matrix using a mask pattern; a first degree-altering unit that considers the sum of the components of the k_r-th row block of the block inspection matrix as a cyclic permutation matrix; and a second degree-altering unit that prescribes the row-block number of components that are non-zero matrices among the components of each row block excluding said k_r-th row block of the clock inspection matrix.

Abstract: In an arrangement of the disclosed systems, devices, and methods, a matrix representation of a block code comprising m bit-planes is obtained, a generator matrix corresponding to each of the m bit-planes from the matrix representation is extracted, a transformed generator matrix and a transformed data symbol vector for the first bit-plane of the block code are determined, a reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are determined, and instructions for the encoder architecture based on the transformed generator matrix for the first bit-plane and the reverse-mapped transformed generator matrix for each of the second bit-plane through the mth bit-plane of the block code are generated.

Abstract: The present disclosure relates to methods, systems, and computer-readable media for varying a memory size in a data stream processing while improving a connection degree sketch. Embodiments of the present disclosure may encode an input data by using an error coding technique to produce an encoded data, wherein the encoded data results in a modified memory size; generate a host connectivity using a set of parameters and applying a reverse sketching technique over the encoded data in order to obtain estimated encoded data; and decode the encoded data after the host connectivity is established using a decoding technique and obtaining an output data. The memory size of the output data may be proportional to the memory size of the input data.

Abstract: Error protection based on a nonlinear code set may be used in a multiple input multiple output (MIMO) radio communications system. A decoder decodes received MIMO data streams and generates an automatic repeat request (ARQ) message for data units received for the MIMO data streams for each transmission time interval. An encoder codes the ARQ message using a code word from a nonlinear code set. At the data transmitter, which transmits one or more data units in transmission time intervals from two or more MIMO data streams, the ARQ message associated with the transmitted data units is decoded using a code word from the nonlinear code set.

Abstract: In one embodiment, a Chien search circuit includes a plurality of evaluation circuits, each configured to sequentially evaluate possible roots ?i in a respective subset of possible roots of an error location polynomial (?(x)). Each evaluation circuit includes a respective sub-circuit for each of a plurality of coefficients ?i (0?i?T) of the error location polynomial ?(x) having T+1 coefficients. Each sub-circuit is configured to calculate one term of the error location polynomial for each possible root ?i in the respective subset of possible roots. Each evaluation circuit is configured to evaluate the error location polynomial for each possible root in the respective subset of possible roots, as a sum of the terms calculated by the plurality of sub-circuits.

Abstract: A device includes a controller configured to provide a data word and check bits for the data word to decoding logic, the decoding logic configured to generate a decoding of the data word and check bits for the data word in conformance with an H-matrix having the following properties: (a) no all 0 columns; (b) all columns are distinct; (c) no linear dependency involving three or less columns; (d) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where j=i+1 and m=k+1; and (e) no linear dependency involving columns Ci, Cj, Ck, Cm, where m>k>j>i, where (j=i+1 and m?k=q) or (k=j+1 and m?i=q) or (m=k+1 and j?i=q) for all integer values of q such that q>1 and q<=d, where d>=2 and d<=n?1 where n?k is a number of the check bits.

Abstract: A method for encoding includes receiving input data symbols to be encoded with an Error Correction Code (ECC) so as to produce a code word of the ECC including redundancy symbols. The input data symbols are applied first and second processing stages, such that the first processing stage performs a first polynomial division by a fixed-coefficient polynomial with a first degree of parallelism, and the second processing stage performs a second polynomial division by a configurable-coefficient polynomial with a second degree of parallelism that is smaller than the first degree of parallelism, so as to jointly produce the redundancy symbols.

Abstract: A circuit enabling generating a product in a decoder circuit is disclosed. The circuit comprises a first memory element coupled to receive a first error value and a first portion of a second error value; a second memory element coupled to receive the first error value and a second portion of the second error value; and an adder circuit coupled to add an output of the first memory element and an output of the second memory element. The output of the first memory element is generated in response to an address based on the first error value and the first portion of the second error value, and the output of the second memory element is generated in response to an address based on the first error value and the second portion of the second error value. A method for generating a product in a decoder circuit is also disclosed.

Abstract: In one embodiment, an encoder circuit is provided. The encoder includes an input circuit having a plurality of finite field subtraction circuits, each configured to receive a respective one of the sequence of symbols and subtract the symbol from a respective symbol of an intermediate polynomial to produce a respective feedback symbol. For each coefficient of a code generation polynomial, a first circuit is configured to multiply each feedback symbol by a respective constant corresponding to the coefficient to produce a first set of intermediate results. Each first set of intermediate results is summed to produce a second intermediate result. A buffer circuit of the encoder is configured and arranged to store the second intermediate results produced by the first circuit as the intermediate polynomial.

Abstract: A random number generator circuit includes: an element generating and outputting physical random numbers; a digitizing circuit digitizing the physical random numbers to output a random number sequence tested by a testing circuit; and an error correcting code circuit including a shift register having the random number sequence input thereto, a multiplier multiplying the stored random number sequence by an error-correcting-code generating matrix, and a selector switch outputting one of an output of the shift register and an output of the multiplier in accordance with a test result obtained by the testing circuit. The error correcting code circuit outputs the output of the multiplier as a corrected random number sequence from the selector switch when the result of a test conducted by the testing circuit indicates a rejection. The testing circuit tests the corrected random number sequence when the result of the test indicates a rejection.

Abstract: A wireless device comprises a code-assignment module configured for assigning Golay codes to be used for spreading, a spreading module configured for spreading data with the Golay codes to produce a signal, wherein the Golay codes are randomly used to spread the data, and a transmitter configured for transmitting the signal. The wireless device may transmit a first beacon signal via a set of quasi-omni beam patterns, and a second beacon signal via a set directional beam patterns. The first beacon signal has a first transmission rate that is higher than the second beacon signal's transmission rate. Extended Golay codes having zero periodic cross-correlation may be generated from a Golay code and a set of short sequences. A data block transmitted by the wireless device may comprise Golay codes and data portions, wherein every data portion is between two Golay codes and every Golay code is between two data portions.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: Various embodiments of the present invention provide systems and methods for a symbol flipping data processor. For example, a symbol flipping data processor is disclosed that includes a data decoder in the symbol flipping data processor operable to perform error checking calculations, and a data detector in the symbol flipping data processor operable to perform symbol flipping in the data detector based at least in part on the error checking calculations, wherein the output of the data processor is generated at least in part based on the symbol flipping in the data detector.

Abstract: A system and method for using a cyclic redundancy check (CRC) to evaluate error corrections. A set of data and initial CRC values associated therewith may be received. The set of data by changing a sub-set of the data may be corrected. Intermediate CRC values may be computed for the entire uncorrected set of data in parallel with said correcting. Supplemental CRC values may be computed for only the sub-set of changed data after said correcting. The intermediate and supplemental CRC values may be combined to generate CRC values for the entire corrected set of data. The validity of the corrected set of data may be evaluated by comparing the combined CRC values with the initial CRC values.

Abstract: A system and method for transmitting and receiving acknowledgement information are provided. A method for communications device operations includes determining a hybrid automatic repeat request (HARQ) response for each component carrier (CC) in a set of CCs configured by higher layer signaling, thereby producing a set of HARQ responses; generating an information vector from the set of HARQ responses, encoding the information vector; and transmitting the encoded information vector. The information vector comprises one or more bits respectively corresponding to a CC in the set of CCs. A bit is assigned a fixed value if HARQ response of a corresponding CC is set to DTX in response to no transmission detected over the CC.

Abstract: A decoder, an encoder, a decoding method and an encoding method are provided. The encoding method includes receiving data; generating a set of first codewords by applying a first encoding process on the received data; and performing a second encoding process on a folded version of each first codeword to provide a set of second codewords, wherein a folded version of a first codeword is representative of a storage of the first codeword in a two dimensional memory space, wherein the second codeword comprises redundancy bits.

Abstract: A data reading method is provided. The data reading method includes: utilizing a first sense voltage to read a data unit from a flash memory block; performing an error detection operation on the data unit and calculating an error polynomial according to a detection result; and determining whether the error polynomial conforms to a predetermined condition and deciding whether to perform read retry on the data unit according to a determining result.

Abstract: The invention discloses a method and an apparatus for data check processing, the method comprises: acquiring data to be checked; acquiring a first polynomial matrix F according to a generator polynomial; acquiring a second generator polynomial matrix Fi according to Fi=Fi, wherein i is the digit of the data; generating a CRC code of the data from the second generator polynomial matrix Fi, initial CRC register value X(0) and the data; and sending the data and the CRC code to a receiver for being checked by the receiver.

Abstract: A cyclic code encoding device or encoder that contains word registers rather than single bit registers, and can process input bits and parity bits as input words and parity words. The cyclic code encoder can add input words to output register words, generating a feedback word, which can be supplied through a feedback loop that selectively transmits feedback words through weight arrays and intra-register adders, to the input of word registers. A controller can operate the cyclic code encoder in either an input mode or an output mode during which feedback words can be sequentially transmitted on the feedback loop and the states of the word registers can be updated and the final states of the word registers can be sequentially shifted out of the output word register as parity words.

Abstract: Methods and apparatus create codewords of n-state symbols having one of 3 or more states with n-state check symbols. Check symbols are created from independent expressions. Codewords are associated with a matrix for detection of one or more symbols in error and the location of such symbols in error. Symbols in error are reconstructed from symbols not in error, error syndromes and check symbols not in error. Deliberately created errors that can be corrected are used as nuisance errors.

Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

Abstract: An encoder and decoder using LDPC-CC are provided, which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an associated encoding method is provided. A termination sequence length determining unit determines the sequence length of a transmitted termination sequence added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.

Abstract: In staircase forward error correction coding, a stream of data symbols are mapped to data symbol positions in a sequence of two-dimensional symbol blocks Bi, i a positive integer. Each of the symbol blocks has data symbol positions and coding symbol positions. Coding symbols for the coding symbol positions in each symbol block Bi in the sequence are computed. The coding symbols are computed such that, for each symbol block Bi that has a preceding symbol block Bi?1 and a subsequent symbol block Bi+1 in the sequence, symbols at symbol positions along one dimension of the preceding symbol block Bi?1, concatenated with the data symbols and the coding symbols along the other dimension in the symbol block Bi, form a codeword of a FEC component code, and symbols at symbol positions along the one dimension of the symbol block Bi, concatenated with the data symbols and the coding symbols along the other dimension in the subsequent symbol block Bi+1, form a codeword of the FEC component code.

Abstract: A method for channel-coding information bits using a code generation matrix including 32 rows and A columns corresponding to length of the information bits includes, channel-coding the information bits having “A” length using basis sequences having 32-bit length corresponding to columns of the code generation matrix, and outputting the channel-coded result as an output sequence. If “A” is higher than 10, the code generation matrix is generated when (A-10) additional basis sequences were added as column-directional sequences to a first or second matrix. The first matrix is a TFCI code generation matrix composed of 32 rows and 10 columns used for TFCI coding. The second matrix is made when at least one of an inter-row location or an inter-column location of the first matrix was changed. The additional basis sequences satisfy a value 10 of a minimum Hamming distance.

Abstract: Disclosed herein is a coding apparatus, including: a calculation section adapted to calculate, based on information of a transmission object, a linear code to be used for error detection of the information; a production section adapted to produce coded data including a plurality of sets of the information and the linear code calculated by the calculation section; and a transmission section adapted to transmit the coded data to a reception apparatus.

Abstract: A method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. In one embodiment of the invention, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction.

Abstract: Subject matter disclosed herein relates to error protection of data stored in and/or read from a memory device.

Abstract: A method begins by a dispersed storage (DS) processing module receiving a zero information gain (ZIG) encoded data slice and a subset of encoded data slices of a set of encoded data slices. The method continues with the DS processing module generating a set of ZIG encoded data slices using a ZIG function and corresponding ones of the subset of encoded data slices, wherein the set of ZIG encoded data slices represents additional components of recovery information of a first encoded data slice. The method continues with the DS processing module recreating the first encoded data slice from the ZIG encoded data slice and the set of ZIG encoded data slices. The method continues with the DS processing module decoding the subset of encoded data slices and the first encoded data slice using a dispersed storage error coding function to reproduce data.

Abstract: Methods of correcting data in a memory, and memories adapted to correct data, include prioritizing error correction of the read data in response to locations and likely states of known bad or questionable data positions of a segment of a memory array selected for reading.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: An apparatus generally having a plurality of first circuits and a second circuit is disclosed. The first circuits may be configured to (i) generate a plurality of intermediate bits by dividing a plurality data bits by a plurality of minimal polynomials of an encoding along a first path and (ii) generate a plurality of parity bits by multiplying the intermediate bits by the minimal polynomials along a second path. A number of the parity bits may be variable based on a configuration signal. The second circuit may be configured to (i) delay the data bits and (ii) generate a plurality of code bits by appending the parity bits to a last of the data bits.

Abstract: Various embodiments of the present invention provide systems and methods for a data processing system with failure recovery. For example, a data processing system is disclosed that includes a data processing circuit operable to process a block of data from an input and to yield a plurality of possible results based on the block of data, and an error detection circuit operable to test the plurality of possible results for errors and to report to the data processing circuit whether the plurality of possible results contain errors. The data processing system is operable to output any of the possible results in which the error detection circuit found no errors.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: A method of data validation is provided. In one implementation, the method includes performing a cyclic redundancy check (CRC) on data transmitted over a channel having L lanes. In one implementation, the performing includes performing the CRC using n CRC bits and a CRC polynomial, where n is an integer equal to or greater than one and where L is an integer equal to or greater than one and represents the number of lanes in the channel. Further, in one implementation, the CRC polynomial is selected based on L. In one implementation, the method includes: performing a CRC on data, where the performing includes performing the CRC using n CRC bits, where n is an integer equal to or greater than one; and performing a checksum on the data, where the performing the checksum includes performing the checksum using m checksum bits, where m is an integer equal to or greater than one, where n plus m bits are allocated for validating the data.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: Systems and methods for error recovery are presented. Data is decoded with an iterative decoding scheme having a first set of parameters. In response to a determination that the iterative decoding scheme has failed, the data is re-read. While the data is being re-read, the iterative decoding scheme is reconfigured with a second set of parameters, and the data is decoded with the reconfigured iterative decoding scheme. In response to determination that the reconfigured iterative decoding scheme has failed, an error type associated with the data is determined. An error recovery scheme is selected from a plurality of error recovery schemes for the data based on the determined error type.

Abstract: Methods and a system for operating a programmable device are disclosed. In one embodiment, a method includes accessing a master summary data and loading an original configuration data to configuration registers of the programmable device. The method further includes generating a current summary data by performing a summary operation of a current configuration data of the configuration registers of the programmable device, comparing the current summary data with the master summary data, and performing an exception action if the current summary data does not match with the master summary data.