Abstract: A query controller accesses a cache comprising information related to data that is newly added to a database, responsive to detecting a data extraction application is ready to query the database for at least one data extraction rule. The information is added to the cache for each new data event received by a data processing application, prior to the data processing application adding the data parsed from each new data event to the database. The query controller evaluates each data extraction rule against the information in the cache to determine whether the information is relevant to at least one data extraction rule.

Abstract: A chip includes a dielectric layer and a fill structure in the dielectric layer, wherein the fill structure extends along a dicing edge of the chip, with the fill structure abutting the dicing edge.

Abstract: In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

Abstract: A computer system identifies active nets in a netlist of a circuit design by performing simulation of the netlist. Active nets are interconnections between circuit components showing a level of activity during the simulation. The computer system extracts, from a layout of the circuit design, a parasitic netlist of a part of the circuit design, where the part determined by the active nets. The parasitic netlist is a list of parasitic nets, or unwanted circuit interconnections that are unavoidable adjuncts of the active nets. The computer system performs simulation of the circuit design including the netlist of a circuit design and the parasitic netlist of the part of the circuit design.

Abstract: A method, a system and a computer program product for reducing coupling noise in low loss on-module wires used for connecting module components in electrical circuits/devices. During the design stage, an Enhanced Crosstalk Reduction (ECR) utility identifies interconnect wires as driven/aggressor traces or receiver traces. The ECR utility substantially avoids forward crosstalk in a victim trace by specially arranging driver traces adjacent to the receiver victim trace in order to provide a lower level and saturated level of backward crosstalk. In particular, the ECR utility provided a configuration of wire/trace layers based on one or more of: (a) the crosstalk impact of a trace when positioned in a particular location; (b) the crosstalk impact of the trace upon remaining components based on placement in the particular location; and (c) system component specifications.

Abstract: The function of logic cells may be changed by altering their metal routing. Logic cells altered in this manner may be used to correct, substitute, or otherwise alter the operation of logic blocks or scan paths without completely re-working an integrated circuit. The process may be referred to as an engineering change order (ECO) process. According to an exemplary process a buffer may be reconfigured to operate as a NAND gate, a NOR gate, or an INVERTER, for example, and may be configured to operate in a circuit in need of such a logic function.

Abstract: A designing device for a semiconductor integrated circuit of an embodiment includes a low-order hierarchy wiring design portion configured to design a first wiring; and a high-order hierarchy wiring design portion configured to design a second wiring. The low-order hierarchy wiring design portion divides the first functional block into a plurality of small regions, calculates a number of wiring layers required for wiring in the functional block for each of the plurality of small regions and sets the number as the number of low-order hierarchy wiring layers, sets wiring layers in the number of the low-order hierarchy wiring layers from the wiring layer located on the lowermost part as a low-order hierarchy wiring region for each of the plurality of small regions, and places the first wiring in the low-order hierarchy wiring region.

Abstract: An integrated circuit device layout is created based on charge carrier mobility characteristics of the device's non-functional cells. The charge carrier mobility of the non-functional cells can alter behavioral characteristics such as the hold time, setup time, or leakage current of nearby functional logic cells. Accordingly, a layout tool creates the layout for the integrated circuit device by selecting and placing non-functional cells having different mobility so as to selectively alter the characteristics of nearby logic cells.

Abstract: Provided are semiconductor device cells, methods for forming the semiconductor device cells and a layout style for the semiconductor device cells. The device cells may be repetitive cells used throughout an integrated circuit. The layout style utilizes an area at the polysilicon level that is void of polysilicon and which can accommodate conductive leads therein or thereover. The conductive leads are formed of material typically used for contacts or vias and are disposed beneath the first metal interconnect level which couples device cells to one another. The subjacent local conductive leads may form subjacent signal lines allowing for additional power mesh lines to be included within the limited number of metal tracks that can be accommodated within a device cell and in accordance with metal track design spacing rules.

Abstract: A design support apparatus that supports designing of a circuit and is connected to a display unit, the design support apparatus includes a storage unit that stores logical connection information of the circuit and cell information of a plurality of cells included in the circuit, a selection unit that selects target cell information of a cell to be placed out of the cell information stored in the storage unit, a placement unit that provisionally places the cell corresponding to the selected target cell information based on inputted positional information, a determination unit that determines whether a wiring mode is set, a wiring unit that provisionally arranges wiring connected to the provisionally placed cell when the determination unit determines that the wiring mode is set, and a finalization unit that finalizes a position of the wiring provisionally arranged based on finalization of a position of the cell provisionally placed.

Abstract: Methods, software, and systems implementing software provide for accepting a user's selection of a database object defining layout being displayed. The database objects can include objects defining paths and path segments. Automatic layout tools may be used in creating at least some of the objects. The user's selection begins a recursive process of automatically selecting additional database objects based on criteria designed to create an uninterrupted spine from database objects on a single interconnect layer, of the same width, and collectively arranged such that the spine has a first end and a second end, and can be traced from the first end to the second end without backtracking.

Abstract: A layout method of a semiconductor integrated circuit includes five steps. The first step is of extracting a wiring crowding place where wiring lines are crowded as compared with a predetermined condition, after carrying out a routing in a region where a placement of circuit elements is carried out. The second step is of generating routing prohibition regions where a routing is prohibited in an area including the wiring crowding place. The third step is of carrying out a routing by bypassing the routing prohibition regions. The fourth step is of deleting the routing prohibition regions. The fifth step is of carrying out a re-routing. The generating step includes: calculating a size and an interval of the routing prohibition regions based on a rate for generating a routing prohibition region in the area in each wiring layer, and generating the routing prohibition regions in the area on the basis of the calculating result.

Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.

Abstract: A logic device includes a low-skew network that feeds a subset of elements on the logic device. The low-skew network includes a selector that can select from a plurality of signal sources which includes a first signal source and a second signal source, wherein the second signal source can reach at least one element outside of the subset.

Abstract: Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.

Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.

Abstract: Setting final dimensions while protecting against the possibility of merging shapes is provided by performing a decomposition of tolerance bands onto a plurality of masks for use in a multi-exposure process. This allows the maximum process latitude between open and short failure mechanisms, while also providing a mechanism to enforce strict CD tolerances in critical regions of a circuit. The decomposition enables co-optimizing various types of shapes placed onto each mask along with the source used to print each mask. Once the tolerance bands are decomposed onto the two or more masks, standard tolerance-band-based data preparation methodologies can be employed to create the final mask shapes.

Abstract: To considerably reduce the cell layout change after timing optimization to reduce the term of layout design by estimating timing and an area after the timing optimization. During the period of initial layout processing using a net list, a timing constraint, a floor plan, a layout library, a timing library, etc., a library for estimating timing/area for estimating the timing and area after the timing optimization is created in advance and whether the timing constraint can be met is estimated. A cell in a path that hardly meets the timing constraint is placed in proximity and conversely, a cell that easily meets the timing constraint is placed at a distance. At this time, an area increase is also estimated so that wiring congestion does not occur.

Abstract: A method of generating optimized input/output (IO) pair and inter-chip connection combinations for two chips is described. In this method, first and second designs for two chips can be specified. Then inter-chip signals based on the first and second designs can be specified. IO pairs for the first and second chips can be determined based on the inter-chip signals. At this point, electrical contacts between micro-bumps (MBs) of the first and second chips can be formed. Inter-chip paths with through-silicon-vias (TSVs) and MBs of the first and second chips can also be formed. At this point, the costs of assigning the IO pairs to the inter-chip paths can be determined. A cost matrix can be built based on these costs. A bipartite matching algorithm can be applied to the cost matrix to determine the optimized IO pair and inter-chip path combinations.

Abstract: This invention concerns an automated method of generating a design for an I/O fabric of a target integrated circuit having a core and pins. A process tool executes algorithms to generate a synthesizable representation of the I/O fabric ring in hardware description language. It imports integrated circuit design data, and from it captures I/O specification data for a circuit core, library of cells, pin, I/O control, BSR and I/O cell chaining, and die. The tool validates the specification data, and generates the I/O fabric design by configuring and inter-connecting a pin multiplexing and control matrix structures according to constraints for signal control, and timing. The structures includes on both the input and output paths of each pin a functional multiplexer matrix structure, a test multiplexer matrix structure, an override matrix structure, a multiplex select and control matrix structure, and an I/O Cell control logic.

Abstract: A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks.

Abstract: Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

Abstract: A hardware circuit component for executing multiple sum-of-products operations is manufactured as follows. A set of multiplexed sum-of-products functions of a plurality of operands (a, b, c, . . . ), any one of which functions can be selected in dependence upon a select value (sel) by multiplex operations, is received. The sum-of-products functions are then rearranged in a particular manner. The rearranged set of sum-of-products functions is merged into a single merged sum-of-products function containing one or more multiplexing operations. From this a layout design can be generated, and a hardware circuit component such as an integrated circuit manufactured from the layout design. The step of re-arranging the multiple sum-of-products functions involves aligning the elements of the set of sum-of-products functions in such a manner that the amount of multiplexing in the single merged sum-of-products function is less than in the input set of sum-of-products functions.

Abstract: Disclosed are systems and methods for electrical verification of integrated circuits. Methodologies are described for verification of the power and ground distribution systems (PDS) for system-on-a-chip (SoC) and the verification of the interaction of the PDS with the behavior of integrated circuits.

Abstract: A computer-implemented method identifies at least one proprietary geometric figure from a plurality of geometric figures within a design data layout format file. The proprietary geometric figure in the design data layout format file may be replaced with a placeholder geometric figure. Cell names and connection names associated with the proprietary geometric figure are renamed from a netlist file that defines electrical connections between the geometric figures with obfuscating names. A modified design data layout format file may be generated that includes the placeholder geometric figure and a modified netlist file including the obfuscating names. The modified file enables IC designers to complete their design and checking activities, but inhibits reverse-engineering of the proprietary geometric & netlist data.

Abstract: The Intelligent Graphics Plug Map System automatically converts plug maps into Intelligent Graphics with intelligent behaviors. The electronic trouble shooting system enables users to easily navigate large quantities of interrelated data and accurately analyze how each plug is used. The system automatically integrates additional information such as the function of each contact, what signals are connected to the contact, and what tools and processes are required to repair or test electrical circuitry. The system provides an Intelligent Plug Map Recognizer that associates a correct contact label for each contact associated with a plug map file defining a plug map; an HTML Generator that generates an HTML file for the plug map; a CGM4 File Builder that generates an intelligent plug map file from the plug map file; and a technical data system application that synchronizes plug map views when a contact associated with the plug map is identified.

Abstract: A method of manufacturing a semiconductor device, including the steps of: acquiring information on a graphic composing a physical layout of a semiconductor integrated circuit; carrying out calculation for a transferred image in the physical layout; carrying out calculation for a signal delay based on the physical layout, and obtaining a wiring not meeting a specification having the signal delay previously set therein; and setting a portion into which a repeater is to be inserted based on at least one result of results obtained from the information on the graphic and calculation for the transferred image, respectively, with respect to the wiring not meeting the specification.

Abstract: A system and method of designing the physical layout of an SoC incorporating row-based placement of analog standard cells whose heights are constrained to a predetermined row height or integer multiple thereof. A library of analog standard cells may be utilized by an ECAD tool to map, place, and route analog and mixed signal circuits in a manner similar to how such ECAD tool may utilize a library of digital standard cells to map, place, and route digital circuits. Mapping, placing, and routing of digital, analog, and mixed signal circuits may proceed within a unified ECAD SoC physical design flow. Finally, a general type analog standard cell is taught to further increase the speed and efficiency of analog and mixed-signal SoC layout.

Abstract: A large block synthesis (LBS) process pre-optimizes selected submacros by synthesizing the submacros using timing assertions and placement abstracts, removing placement information, and assigning weights to the internal nets of the submacros that are much higher than weights used for external (e.g., top-level) nets. The timing assertions include an input arrival time, a required output arrival time, and an output pin capacitance loading for the logic block, and the placement abstract is generated by condensing input and output pins of the logic block at a center of gravity of the logic block. The submacros to be pre-optimized can automatically be identified using an attribute to indicate pre-optimization, or by determining that the submacro is one of many instances in the design. The higher weights for the submacro nets define soft-bounds for the logic which still allow relocation of submacro components. The pre-optimization results in significantly reduced synthesis runtime.

Abstract: An aspect of the present invention is a method for laying out a power wiring of a semiconductor device. The method includes: modeling the power wiring as an analysis model including a plurality of nodes and a plurality of element resistors provided between the plurality of nodes neighboring each other; obtaining voltage values of the plurality of nodes by a circuit simulation; searching a path of a current flowing into a node of the plurality of nodes when an IR drop violation exists in the voltage values, the node having a maximum value of the IR drop violation; selecting a bottleneck element resistor from among the plurality of element resistors included in the path; and changing a resistance value of the bottleneck element resistor.

Abstract: A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

Abstract: Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.

Abstract: A method for providing an alternative power source for a graphics card are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of laying a set of gold fingers on a printed circuit board according to an industrial standard bus interface, positioning a wire in a middle layer of the printed circuit board, attaching a first end of the wire to a specific gold finger, and attaching the alternative power source to a second end of the wire, wherein the second end of the wire is an electroplated contact protruded external to the printed circuit board.

Abstract: A circuit design device decides placement of elements and interconnections included in a circuit, on the basis of connection information of the circuit. The circuit design device includes an equivalent fault class extracting unit, a weighting unit, and a placement deciding unit. The equivalent fault class extracting unit extracts one or more classes (hereinbelow referred to as “equivalent fault classes”) having, as members, interconnections (hereinbelow referred to as “equivalent fault interconnections”) which mutually cause an equivalent fault in the circuit. The weighting unit gives a greater weight to the equivalent fault class or the equivalent fault interconnections included in the equivalent fault class, as the number of the members in the equivalent fault class (hereinbelow referred to as the “number of equivalent fault interconnections”) increases.

Abstract: An integrated circuit design apparatus includes a macro signal terminal position determination unit that determines temporary arrangement positions of a scan-in terminal and a scan-out terminal of each of a number of macros. The unit updates layout information of an integrated circuit based on the temporary arrangement positions. The apparatus includes an initial scan path route determination unit that updates scan path connection information, such that one of the macros arranged in a closest distance is connected in turn starting with a scan-in external terminal, with reference to the updated layout information and the scan path connection information. The apparatus include a scan path re-routing unit that determines a scan path connection order, such that a scan path total wiring length becomes shortest, with reference to the updated layout information and the updated scan path connection information. This unit updates the scan path connection information based on this determined order.

Abstract: A semiconductor device, includes a first wiring pattern in a first region, a second wiring pattern in a second region, and at least one first dummy pattern formed in the first region and at least one second dummy pattern formed in the second region. A total area of the at least one first dummy pattern is the same as a total area of the at least one second dummy pattern and a total length of pattern periphery of the at least one second dummy pattern is longer than a total length of pattern periphery of the at least one first dummy pattern. The first region and the second region have same area.

Abstract: Techniques are described for increasing the density of structures in a layout circuit design, while reducing undesired total interconnect capacitance that might otherwise be created by the increase in structure density. Data representing a pattern of fill structures is added to the fill regions of the design for one of the layers. Data representing a pattern of fill structures then is added to the fill regions of the design for another of the layers adjacent to the first layer. In the design for the second conductive layer, however, the pattern of fill structures is offset from the pattern of fill structures added to the design for the first layer in a direction substantially parallel to the layers. The offset may be selected to minimize or otherwise reduce the amount of overlap between the fill structures along a direction substantially perpendicular to the layers, thereby reducing the total interconnect capacitance associated with the layers.

Abstract: An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Abstract: The invention concerns a method and devices for analyzing the feasibility of a computer system composed of subsystems, each having functions. After having determined the functional architecture of the computer system comprising at least one subsystem and at least one function, the characteristics of the functions implemented are imported from a database. The user determines the number of subsystems and the number of connectors per subsystem. He then distributes the functions to the subsystems and enters the characteristics of the connectors and the characteristics of the subsystems. The computer system is analyzed in light of the information provided by the user and the characteristics of the functions implemented in order to determine the feasibility of the computer system.

Abstract: An integrated circuit device includes a dynamic array section that includes a gate electrode level region that has linear conductive features defined in accordance with a gate level virtual grate. Each of at least three consecutively positioned virtual lines of the gate level virtual grate has at least one linear conductive feature defined thereon. A first virtual line of the at least three virtual lines has two linear conductive segments defined thereon and separated by a first end-to-end spacing. A second virtual line of the at least three virtual lines has another two linear conductive segments defined thereon and separated by a second end-to-end spacing. A size of the first end-to-end spacing as measured along the first virtual line is substantially equal to a size of the second end-to-end spacing as measured along the second virtual line.

Abstract: A semiconductor memory chip that has word lines driven by respective word line drivers and bit lines to carry signals to respective bit line amplifiers/drivers with memory cells at intersections of the word lines and bit lines memory cells. The semiconductor memory chip including various memory cell types, the type of memory cell at an intersection based on a position of the intersection among the word lines and bit lines.

Abstract: CMOS pixel sensors with multiple pixel sizes and methods of manufacturing the CMOS pixel sensors with implant dose control are provided. The method includes forming a plurality of pixel sensors in a same substrate and forming a masking pattern over at least one of the plurality of pixel sensors that has a pixel size larger than a non-masked pixel sensor of the plurality of pixel sensors. The method further includes providing a single dosage implant to the plurality of pixel sensors. The at least one of the plurality of pixel sensors with the masking pattern receives a lower dosage than the non-masked pixel sensor.

Abstract: An automated method for estimating layout-induced variations in threshold voltage in an integrated circuit layout. The method begins with the steps of selecting a diffusion area within the layout for analysis. Then, the system identifies Si/STI edges on the selected area as well as channel areas and their associated gate/Si edges. Next, the threshold voltage variations in each identified channel area are identified, which requires further steps of calculating threshold voltage variations due to effects in a longitudinal direction; calculating threshold voltage variations due to effects in a transverse direction; and combining the longitudinal and transverse variations to provide an overall variation. Finally, a total variation is determined by combining variations from individual channel variations.

Abstract: A circuit design assist system that receives a user instruction for registering an interface section of at least two circuits as a template, and generates a plurality of circuit patterns of the interface section, each pattern having a different combination of electrical properties of at least one device included in the interface section for evaluation. When an evaluation result indicates that the interface section operates normally for each of the circuit patterns, the circuit design assist system registers the interface section as the template.

Abstract: Combined memories in integrated circuits are described, including determining a first requirement for logic blocks, determining a second requirement for memory blocks including a vertical configuration for the memory bocks, and compiling a design for the integrated circuit using the first requirement and the second requirement. The memory blocks may include non-volatile two-terminal cross-point memory arrays. The non-volatile two-terminal cross-point memory arrays can be formed on top of a logic plane. The logic plane can be fabricated in a substrate. The non-volatile two-terminal cross-point memory arrays may be vertically stacked upon one another to form a plurality of memory planes. The memory planes can be portioned into sub-planes. One or more different memory types such as Flash, SRAM, DRAM, and ROM can be emulated by the plurality of memory planes and/or sub-planes. The non-volatile two-terminal cross-point memory arrays can include a plurality of two-terminal memory elements.

Abstract: Disclosed is a computer implemented method, data processing system, and computer program product to optimize, incrementally, a circuit design. An Electronic Design Automation (EDA) system receives a plurality of nets wherein each net is comprised of at least one pin. Each pin is linked to a net to form a path of at least a first pin and a second pin, wherein the first pin is a member of a first net. The second pin can be a member of a second net, and the path is associated with a slack. The EDA system determines whether the path is a critical path based on the slack. The EDA system reduces at least one wire length of the path, responsive to a determination that the path is a critical path. The EDA system moves a non-critical component in order to reduce at least one wire length of the nets that include pins of a non-critical component, responsive to reducing at least one wire length of the path, wherein the non-critical component lacks pins on a critical path.

Abstract: A package includes a die and at least one further die. The die has an interface configured to receive a transaction request from the further die via an interconnect and to transmit a response to the transaction request to said further die via the interconnect. The die also has mapping circuitry which is configured to allocate to the received transaction a local source identity information as source identity information, the local source identity information comprising one of a set of reusable local source identity information. This ensures the order of transactions tagged with a same original source identity and target and allows transactions tagged with different source identifiers to be processed out of order.

Abstract: Disclose are embodiments of an integrated circuit design method based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage. Design-for manufacturability (DFM) modifications to the layout of an integrated circuit can be made in light of test coverage. Alternatively, test coverage of an integrated circuit can be established in light of DFM modifications. Alternatively, an iterative process can be performed, where DFM modifications to the layout of an integrated circuit are made in light of test coverage and then test coverage is altered in light of the DFM modifications. Alternatively, DFM modifications to the layout of an integrated circuit can be made in light of test coverage and also diagnostic coverage. In any case, after making DFM modifications and establishing test coverage, any unmodified and untested nodes (and, optionally, any unmodified and undiagnosable tested nodes) in the integrated circuit can be identified and tagged for subsequent in-line inspection.

Abstract: A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

Abstract: A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures.