Abstract: The invention relates to a method for influencing the selection of a type and form of a circuit implementation in at least one layer in a given integration task for at least one integrated circuit in a wafer composite, a module on a 2-dimensional carrier substrate, or a compact module. In one embodiment, a plurality of electric or electronic components are spatially arranged and to be electrically connected. Completed solutions x are stored in a database, and each of the completed solutions includes properties for the given integration task. The completed solutions define a destination space from which a solution is selectable by operating elements and determines a type and form of circuit implementation as a result of the given integration task, and aggregates the plurality of electric and electronic components in one of a plurality of integration technologies.

Abstract: Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.

Abstract: A method of generating a layout of an integrated circuit is disclosed, the layout incorporating both standard cells and at least one memory instance generated by a memory compiler to define a memory device of the integrated circuit. Input data is received specifying one or more properties of a desired memory instance. The memory compiler generates the desired memory instance based on the input data and using the specified memory architecture. A standard cell library is provided. The memory compiler references at least one property of the standard cell library in order to generate the desired memory instance. The layout is then generated by populating standard cell rows with standard cells selected from the standard cell library in order to provide the functional components required by the integrated circuit, and integrating into the layout the desired memory instance provided by the memory compiler.

Abstract: Embodiments relate to a method of decomposing a layout of a semiconductor device. The method may include generating a pattern layout including first patterns and second patterns, generating an interference map for the pattern layout, the interference map including optical interference information regarding the first and second patterns, and decomposing the pattern layout into a first decomposition pattern layout including the first patterns, and a second decomposition pattern layout including the second patterns, based on the interference map. In the interference map, an influence of constructive interference on the first patterns may be greater than an influence of constructive interference on the second patterns.

Abstract: A circuit and a method of layout-designing a circuit based on circuit information. The method includes generating layout information including a core region based on the circuit information, laying out an I/O circuit in a region other than the core region on the layout information based on the circuit information, determining a layout-permitted region of pads, which is included in regions other than the core region and a layout region of said I/O circuit, based on circuit information, and laying out the pads in the layout-permitted region.

Abstract: Disclosed is a method and system for visualizing pin access locations on an integrated circuit design. Visual feedback is provided to a user that is attempting to connect a wire or a via to a pin structure polygon on the integrated circuit design. The visual feedback comprises any visual cue that provides an indication of a legal location to access the pin.

Abstract: A method for the creation of rectilinear Steiner minimum trees includes determining a set of candidate connections from a terminal node to a different terminal node or to a graph edge. The length of each candidate connection may be used to determine the set of candidate connections that span the graph with a minimum total length.

Abstract: Circuits, architectures, a system and methods for providing multiple power rails to a plurality of standard cells in a region of an integrated circuit. The circuitry generally includes a plurality of cells configured for connection to a first or second power rail, the first power rail providing a first voltage to at least one of the plurality of cells, and the second power rail providing a second voltage (which may be independent from the first voltage) to remaining cells in the plurality of cells. The method generally includes routing, in an IC layout, a first power rail providing a first voltage and a second power rail providing a second voltage, placing the plurality of cells, and selectively connecting first and second subsets of the plurality of cells to the first and second power rails, respectively. The present invention further advantageously minimizes regional layout design considerations and time delays.

Abstract: A device, and method of fabricating and/or designing such a device, including a first gate structure having a width (W) and a length (L) and a second gate structure separated from the first gate structure by a distance greater than: (?{square root over (W*W+L*L)})/10. The second gate structure is a next adjacent gate structure to the first gate structure. A method and apparatus for designing an integrated circuit including implementing a design rule defining the separation of gate structures is also described. In embodiments, the distance of separation is implemented for gate structures that are larger relative to other gate structures on the substrate (e.g., greater than 3 ?m2).

Abstract: A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device.

Abstract: Self-aligned via interconnects using relaxed patterning exposure. In accordance with a first method embodiment, a method for controlling a computer-aided design (CAD) system for designing physical features of an integrated circuit includes accessing a first pattern for first metal traces on a first metal layer, accessing a second pattern for second metal traces on a second metal layer, vertically adjacent to the first metal layer and accessing a precise pattern of intended interconnections between the first and second metal traces. The precise pattern of intended interconnections is operated on to form an imprecise via pattern that indicates a plurality of general areas in which vias are allowed. The imprecise via pattern is for use in an integrated circuit manufacturing process to form, in conjunction with operations to form the first and second metal layers, a plurality of self-aligned vias for interconnecting the intended interconnections.

Abstract: Systems, methodologies and technologies for the analysis and transformation of integrated circuit layouts using situations are disclosed. A method for transforming an integrated circuit (IC) layout includes recognizing shapes within the IC layout, identifying features for each of the shapes and extracting situations for the respective features. Extracted situations can be used to improve optical proximity correction (OPC) of the IC layout. This improved OPC includes extracting the situations, simulating the situations to determine a set of the situations identified for modification based on failing to satisfy a desired OPC tolerance level, modifying the set of situations to improve satisfaction of the desired OPC tolerance level, and reintegrating the modified set of situations into the IC layout. Extracted situations can also be used to improve aerial image simulation of the IC layout.

Abstract: Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

Abstract: A cell-based architecture for an integrated circuit that uses at least two categories of cells: cut-gate cells and breaker cells. Cut-gate cells have gates that extend from one boundary of the cell to an opposite boundary of the cell. Cut gate features are located along the boundaries of the cell to indicate locations for cutting the gates during fabrication. Instances of the cut-gate cells are arranged in abutting rows that result in the formation of continuous gate strips during the fabrication process, which are then cut into individual gates with a cut-gate mechanism. Breaker cells have gates that do not extend to the boundaries of the breaker cell. To prevent the continuous gate strips from exceeding design rule requirements, instances of breaker cells are placed at intervals between the rows of cut-gate cell instances to restrict the size of the gate strips.

Abstract: A system and method for designing integrated circuits is disclosed. An embodiment comprises placing a standard cell with a first cell height into a cell row with a different height. The standard cell may have a height smaller than the cell row or else may have a height that is larger than the cell row. Vertical fillers and horizontal fillers are utilized to extend and connect the standard cell to adjacent cells without having to redesign the entire cell row.

Abstract: A method and a system for generating a placement layout is disclosed. The method includes receiving one or more user provided schematic with circuit data, placement parameters of circuit elements, default values, and user specified function calls and variables for calculating placement parameters; evaluating variables and function calls to discrete placement parameters; evaluating justification values and adjusting relative parameter values; calculating absolute placement coordinates for all cells from relative placement parameters for each instance; adjusting placement coordinates for alignment options; and generating a layout/hierarchical layout with placement circuit elements based on the calculated absolute placement coordinates.

Abstract: A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to unfold the entire design hierarchy, only the specific instances of shapes falling within the geometric bounds of shapes identified as being part of a net needs to be unfolded to perform the search. When composing the list of nets for a hierarchical design, the unfolded shapes at other hierarchical levels of the design can be derived based upon virtual terminal structures that implicitly references nets and objects at other levels.

Abstract: In an example embodiment, an EDA application creates a physical PCell from a CAD database that relates the physical PCell to a collection of expected mask layers. The EDA application auto-places an identifying text label with the physical and converts the physical PCell and the text label to a format that represents the physical PCell and the text label as sequence of drawn layers. The EDA application generates an equation that performs transformational operations on the drawn layers to create a sequence of derived layers, where the sequence of derived layers defines a collection of logical mask layers. The EDA application executes the equation and compares a derived layer to the expected mask layers, if the derived layer interacts with the derived layer for the text label. If the compared derived layer varies from the expected mask layers, the EDA application reports a variance based on the text label.

Abstract: A semiconductor device includes a first wafer having i) a plurality of semiconductor dies, ii) a plurality of scribe lines adjacent one or more of the semiconductor dies, iii) a test access interface positioned in one or more of the scribe lines, wherein the test access interface has a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the through-substrate conductors and at least one of the semiconductor dies. Methods, apparatus and systems for testing this and other types of semiconductor devices are also disclosed.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: A method comprising placing elements in a layout, performing clock tree synthesis, and performing routing. The method further comprising, in parallel with one of the clock tree synthesis or the routing, performing a footprint based optimization, substituting a footprint equivalent element in a path based on a timing slack of the path.

Abstract: A method includes extracting a first netlist from a first layout of a semiconductor circuit and estimating layout-dependent effect data based on the first netlist. A first simulation of the semiconductor circuit is performed based on the first netlist using an electronic design automation tool, and a second simulation of the semiconductor circuit is performed based on a circuit schematic using the electronic design automation tool. A weight and a sensitivity of the at least one layout-dependent effect are calculated, and the first layout of the semiconductor circuit is adjusted based on the weight and the sensitivity to provide a second layout of the semiconductor circuit. The second layout is stored in a non-transient storage medium.

Abstract: Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement.

Abstract: A method and circuit for implementing field effect transistors (FETs) having a gate within a gate utilizing a replacement metal gate process (RMGP), and a design structure on which the subject circuit resides are provided. A field effect transistor utilizing a RMGP includes a sacrificial gate in a generally central metal gate region on a dielectric layer on a substrate, a source and drain formed in the substrate, a pair of dielectric spacers, a first metal gate and a second metal gate replacing the sacrificial gate inside the central metal gate region, and a second gate dielectric layer separating the first metal gate and the second metal gate. A respective electrical contact is formed on opposite sides of the central metal gate region for respectively electrically connecting the first metal gate and the second metal gate to a respective voltage.

Abstract: Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

Abstract: A finFET block architecture uses end-to-end finFET blocks. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. An inter-block isolation structure separates the semiconductor fins in the first and second sets. The ends of the fins in the first set are proximal to a first side of the inter-block isolation structure and ends of the fins in the second set are proximal to a second side of the inter-block isolation structure. A patterned gate conductor layer includes a first gate conductor extending across at least one fin in the first set of semiconductor fins, and a second gate conductor extending across at least one fin in the second set of semiconductor fins. The first and second gate conductors are connected by an inter-block conductor.

Abstract: A method for selecting and placing of an IP block in a SOC design based on a topology and/or a density of the SOC design is disclosed. Embodiments include: displaying a user interface; causing, at least in part, a presentation in the user interface of a topology and density view of a SOC design that includes an IP block; and modifying, prior to a tape-out of the SOC design, topology and/or density transition for the IP block in the SOC design based on the presentation.

Abstract: An analog design-rule-check tool analyzes a microdevice design, such as an integrated circuit design, to identify occurrences of geometric elements that share a specified relationship. When the tool identifies such an occurrence of these geometric elements, it will associate or “cluster” these geometric elements together into an identifiable unit. For specified “clusters” of geometric elements, the analog design-rule-check tool will then determine the value of a measurement or measurements required by a user. Once the analog design-rule-check tool has determined the necessary measurement values, it will use those values to evaluate the function describing a model.

Abstract: Methods, systems, computer program products for editing electrical circuits that facilitate and speed the layout of electrical circuits. Embodiments provide high-altitude editing capabilities to the user that enable the user to more easily select circuit items in congested layouts and schematic diagrams, and modify and arrange circuit items with respect to one another in congested layouts and schematic diagrams. Additional embodiments are directed to enabling EDA commands and the like to have context sensitivity, neighborhood awareness, and/or an ability to anticipate intentions of the user.

Abstract: Cells designed to accommodate metal routing tracks having a pitch that is an odd multiple of a manufacturing grid. The cells includes cell pins that are located within the cell based on the offsets of the routing tracks relative to the cell boundaries. The cell pins are wider than wires that are routed along the metal routing tracks. The standard cell may be placed in a layout in either a normal orientation or in a flipped orientation. In both orientations, the cell pins are aligned with the wires that are routed along the metal routing tracks.

Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.

Abstract: An integrated circuit (IC) chip having repeaters for propagating signals along relatively long wires that extend between and among lower-level physical blocks of the IC chip, wherein the repeaters are implemented as clocked flip-flops (or “repeater flops”). A method for automatically inserting and allocating such repeater flops during the logical and physical design of the IC chip is also provided.

Abstract: A method of designing an integrated circuit includes deploying an active area in a first standard cell. At least one gate electrode is routed, overlapping the active area in the first standard cell. At least one metallic line structure is routed, overlapping the active area in the first standard cell. The at least one metallic line structure is substantially parallel to the gate electrode. A first power rail is routed substantially orthogonal to the at least one metallic line structure in the first standard cell. The first power rail overlaps the at least one metallic line structure. The first power rail has a flat edge that is adjacent to the at least one metallic line structure. A first connection plug is deployed at a region where the first power rail overlaps the at least one metallic line structure in the first standard cell.

Abstract: A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.

Abstract: Aspects of the present disclosure relate to determining the location and/or density of vias that form part of an RF isolation structure of a packaged module and the resulting RF isolation structures. From electromagnetic interference (EMI) data, locations of where via density can be increased and/or decreased without significantly degrading the EMI performance of the RF isolation structure can be identified. In certain embodiments, one or more vias can be added and/or removed from a selected area of the packaged module based on the EMI data.

Abstract: An improved approach for automatically generating physical layout constraints and topology that are visually in-sync with the logic schematic created for simulation is described. The present approach is also directed to an automatic method for transferring topology from logic design to layout.

Abstract: A method of generating a photo mask layout includes providing a first photo mask layout including main patterns and sub-resolution assist features (SRAF) patterns, defining a plurality of mesh cells by dividing the first photo mask layout into regions, generating a rule based table including correction information for correcting defects in the SRAF patterns for at least one of the plurality of mesh cells, and correcting the SRAF patterns by applying values of the correction information to the SRAF patterns corresponding to each mesh cell.

Abstract: A computer-implemented method for processing an electronic circuit design, a method of placing vias within an electronic circuit, and an electronic circuit produced utilizing such method(s) are disclosed. A method embodiment for processing an electronic circuit design comprises accessing, utilizing a computer, data which represents an electronic circuit design, identifying a via metallization feature associated with at least one interconnect metallization feature of the electronic circuit design utilizing data which represents the electronic circuit design. The described method embodiment further comprises evaluating a spacing design rule check on the via metallization feature of the electronic circuit design utilizing an area occupied by the at least one interconnect metallization feature.

Abstract: A global placement phase of physical design of an integrated circuit includes iteratively spreading a plurality of modules comprising the integrated circuit within a die area based on density of the plurality of modules and optimizing module placement by preserving global module density while improving a local objective, such as local wirelength and/or local density, in individual subareas among a plurality of subareas of the die area. After global placement, detailed placement of modules in the plurality of subareas is performed.

Abstract: An integrated circuit includes an active layer including an active pattern diffusion region. The integrated circuit further includes at least one guard band conforming to a shape of the active layer, the at least one guard band comprising a dummy diffusion layer, wherein the guard bans is spaced from the active layer at a first constant spacing in an X-axis direction and a second constant spacing in a Y-axis direction, which is perpendicular to the X-axis direction. The integrated circuit further includes a plurality of dummy diffusion patterns outside the at least one guard band.

Abstract: This invention provides a method of fabricating transduction devices on flexible electronics that allows a complete mechatronic system to be incorporated into one system. The method uses the interconnects and pads in flexible electronics substrates to make coils, windings and electrodes for electromagnetic and electrostatic transduction. By building these systems directly into the substrate it is possible to make a complete sensing and actuating system that can be fitted onto machinery that requires power and control. The end result is a flexible, 3-dimensional structure that contains transduction, power, and control interconnections, and is customized for complex mechatronic structures and applications. This gives designers of electromechanical control systems the ability to produce a complete feedback system with sensors, actuators, connectors and electronics; all made out of one component.

Abstract: The present invention discloses methods and apparatuses to design an integrated circuit. According to one aspect, the present invention circuit design discloses an iterative process of synthesis and placement where each iteration provides incremental changes on the design of the integrated circuit. The synthesis transform is then made with accurate timing information from the placement, and the process is incrementally iterative toward the final timing enclosure of the design. The incrementally iterative approach of the present invention provides a continuous advancement from synthesis to placement and vice versa, with the incremental improvements on synthesis made with knowledge of current instance placement, and the incremental improvements on placement made with knowledge of current circuit logic.

Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Abstract: To include a first semiconductor chip including driver circuits, a second semiconductor chip including receiver circuits, and through silicon vias provided in the second semiconductor chip. The first semiconductor chip includes an output switching circuit that exclusively connects an output terminal of an i-th driver circuit (where i is an integer among 1 to n) to one through silicon via among an i-th through silicon via to an (i+m)-th through silicon via. The second semiconductor chip includes an input switching circuit that exclusively connects an input terminal of an i-th receiver circuit (where i is an integer among 1 to n) to one through silicon via among the i-th through silicon via to the (i+m)-th through silicon via. With this configuration, because a difference in wiring lengths does not occur between signal paths before and after replacement of through silicon vias, the signal quality can be enhanced.

Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.

Abstract: Systems and methods receive a design of a circuit layout. The circuit layout has some available spaces. Such systems and methods automatically insert capacitor arrays in the specified spaces. Each of the capacitor arrays has capacitor cells, and each of the capacitor cells has capacitor structures and a buried implant. The process of inserting the capacitor arrays comprises a process of forming the capacitor arrays to either: grow the capacitor arrays to the size of the specified spaces; grow the capacitor arrays to a specified capacitance value within the restriction of the length dimension or the width dimension of the specified spaces; or grow the capacitor arrays to a specified capacitance value, irrespective of dimensional length dimension or width dimension limitations (where the only limitations are the dimensions of the specified space).

Abstract: A multi-step density gradient smoothing layout style is disclosed in which a plurality of unit cells are arranged into an array with a feature density. One or more edges of the array is bordered by a first edge sub-array which has a feature density that is less than the feature density of the array. The first edge sub-array is bordered by second edge sub-array which has a feature density that is less than the feature density of the first edge sub-array, and is approaching that of the background circuitry.

Abstract: A method is provided that includes performing a free placement of a system design comprising a plurality of power domains, wherein the power domains are not constrained to physical regions, assigning a physical region to each of the power domains based on the free placement of cells in the power domains, performing a soft cluster placement of the system design with each power domain and corresponding physical region defined as a soft cluster, refining at least one physical region based on the soft cluster placement, redefining cells in at least one power domain based on the soft cluster placement of the cells and the corresponding physical region, and performing a hard cluster placement of the system design with each power domain and corresponding physical region defined as a hard cluster to generate final power domains.

Abstract: Disclosed are method, system, and computer program product for a method and system for a fast and stable placement/floorplanning method that gives consistent and good quality results. Various embodiments of the present invention provide a method and system for approximate placement of various standard cells, macro-blocks, and I/O pads for the design of integrated circuits by approximating the final shapes of the objects of interest by one or more probability distribution functions over the areas for the objects of interest with improved runtime and very good stability. These probability distributions are gradually localized to final shapes satisfying the placement constraints and optimizing an objective function.