Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.

Abstract: Disclosed is an IC layout design method capable of improving a result of an integrated circuit (IC) layout design process including a front-end process and a back-end process. The IC layout design method includes the following steps: executing the front-end process according to an initial clock latency setting and thereby generating an initial netlist; executing at least a part of the back-end process according to the initial netlist and thereby obtaining an updated clock latency setting; executing at least a part of the front-end process according to the updated clock latency setting and thereby generating an updated netlist; and executing the back-end process according to the updated netlist and thereby obtaining the result of the IC layout design process.

Abstract: Disclosed systems and methods may support fabric-independent multi-patterning. A system may include a coloring constraint access engine and a fabric-independent multi-patterning engine. The coloring constraint access engine may be configured to access a set of coloring constraints to apply to geometric elements of a circuit design without accessing a fabric layer that defines a layout of the geometric elements of the circuit design, the set of coloring constraints applicable to multi-patterning the geometric elements of the circuit design to support manufacture of circuit layers using multiple manufacturing steps (e.g., via complementary lithographic masks). The fabric-independent multi-patterning engine may be configured to perform, independent of the fabric layer, a pattern coloring process according to the set of coloring constraints to determine a color assignment for the geometric elements, respectively.

Abstract: A method (of generating a layout diagram) includes: generating a cell (which represents a circuit) including first and second side boundaries which are substantially parallel and extend in a first direction, a first wiring pattern which is an intra-cell wiring pattern that extends in a second direction (substantially perpendicular to the first direction) and represents a conductor of a first signal which is internal to the circuit, and a second wiring pattern which extends in the first direction and represents a conductor of a second signal of the circuit; configuring the intra-cell wiring pattern so that a first end is located substantially a minimum boundary offset interior to the first side boundary; and configuring the second wiring pattern so that a portion thereof has a first end which extends exterior to the first side boundary by a protrusion length which is substantially greater than the minimum boundary offset.

Abstract: In some embodiments, the present disclosure relates to a method that includes receiving an initial layout design for a circuit schematic. The initial layout design includes a first gate electrode, a second gate electrode, and a third gate electrode arranged over a continuous fin. A first source/drain region is arranged between the first gate electrode and dummy gate electrode, and a second source/drain region is arranged between the second gate electrode and the dummy gate electrode. The method further includes determining if at least one of the first or second source/drain regions corresponds to a drain in the circuit schematic, and modifying the initial layout design to increase a dummy threshold voltage associated with the dummy gate electrode when the at least one of the first or second source/drain regions corresponds to the drain in the circuit schematic to provide a modified layout design.

Abstract: Various examples of integrated circuit layouts with line-end extensions are disclosed herein. In an example, a method includes receiving an integrated circuit layout that contains: a first and second set of shapes extending in parallel in a first direction, wherein a pitch of the first set of shapes is different from a pitch of the second set of shapes. A cross-member shape is inserted into the integrated circuit layout that extends in a second direction perpendicular to the first direction, and a set of line-end extensions is inserted into the integrated circuit layout that extend from each shape of the first set of shapes and the second set of shapes to the cross-member shape. The integrated circuit layout containing the first set of shapes, the second set of shapes, the cross-member shape, and the set of line-end extensions is provided for fabricating an integrated circuit.

Abstract: According to one embodiment, there is provided an integrated circuit including a circuit provided with terminals, a plurality of circuit blocks provided with terminals, and a plurality of wirings that run in parallel from the terminals of the circuit toward the circuit blocks and each turns in mid-course toward a position at which a terminal of a corresponding circuit block exists to connect to the terminal of the corresponding circuit block, any adjacent wirings at the terminals of the circuit being connected to different circuit blocks.

Abstract: A system and method of performing model-based refinement of a placement of components in integrated circuit generation select one of the components as a candidate component and postulate a move of the candidate component from an original position to a new position. The method includes defining nets associated with the candidate component. An initial perimeter and a new perimeter associated with each of the one or more nets are defined. The initial perimeter includes the candidate component at its original position and the new perimeter includes the candidate component at its new position. The method includes quantifying a change from the initial perimeter and the new perimeter and the original position and the new position, and obtaining a model of wires interconnecting the candidate component to the components of each of the nets. A result of the placement is provided for manufacture of the integrated circuit.

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

Abstract: Aspects of the present disclosure address improved systems and methods for generating a clock tree based on route-driven placement of fan-out clock drivers. Consistent with some embodiments, a method may include constructing a spanning tree comprising one or more paths that interconnect a set of clock sinks of a clock net of an integrated circuit device design. The method further includes calculating a center of the set of the clock sinks based on clock sink locations in the integrated circuit device design and identifying a point on the spanning tree nearest to the center of the set of clock sinks. The method further includes generating a clock tree by placing a clock driver at the point on the spanning tree that is nearest to the center of the set of clock sinks.

Abstract: A method for fabricating a semiconductor chip includes placing, at a processor, a target cell to be used for a design of the semiconductor chip depending on a first placement, changing, at the processor, the first placement to a second placement, based on a result of comparing a cost function value of the target cell in the first placement with a reference value, and fabricating the semiconductor chip based on one of the first placement and the second placement.

Abstract: Aspects include performing integrated circuit design. A processor identifies a child block of an integrated circuit for placement of a buffer-bay to insert a buffer in a portion of the integrated circuit reserved for the child block. The buffer-bay is divided into a plurality of buffer-bay segments. Parent-level routing information and one or more boundary conditions are analyzed to determine a plurality of placement options for the buffer-bay segments. A best possible placement is selected from the plurality of placement options for the buffer-bay segments as a planned buffer-bay layout. A routing of the integrated circuit is performed based on the planned buffer-bay layout.

Abstract: A technique relates to structuring a semiconductor device. First empty cells are placed against hierarchical boundaries of a macro block. Functional cells are added in the macro block. Remaining areas are filled with second empty cells in the macro block. Shape requirements are determined for the first empty cells and the second empty cells. The first and second empty cells are replaced with determined shape requirements.

Abstract: A computer-implemented method includes receiving a text description of a logic circuit design, reading a plurality of circuit priority indicator values, synthesizing a logic circuit design based, at least in part, on those circuit priority indicator values, and fabricating logic circuits using the synthesized logic circuit design. A corresponding computer program product and computer system are also disclosed herein.

Abstract: Provided is an integrated circuit. The integrated circuit includes: a first standard cell comprising a P-type Fin Field Effect Transistor (FinFET) region and an N-type FinFET region; and a filler cell adjacent to the first standard cell in a first direction and including a first region and a second region arranged in a second direction perpendicular to the first direction, wherein the first region includes a plurality of first insulating structures spaced apart from each other in the first direction, and the second region includes a second insulating structure having a width greater than that of at least one of the plurality of first insulating structures in the first direction, and one of the first region and the second region is arranged adjacent to the P-type FinFET region in the first direction and the other is arranged adjacent to the N-type FinFET region in the first direction.

Abstract: A computer-implemented method includes placing standard cells based on design data defining an integrated circuit. A layout of the integrated circuit is generated by performing colorless routing. First, second, third and fourth patterns included in a quadruple patterning lithography (QPL) layer are arranged, based on space constraints, on the placed standard cells. The generated layout is stored to a computer-readable storage medium. The space constraints define minimum spaces between the first, second, third and fourth patterns. The method includes assigning first, second, third and fourth colors to the first, second, third and fourth patterns, respectively. Masks are generated based on the layout. A semiconductor device is manufactured by using the generated masks. A space between two patterns of the first, second, third and fourth patterns smaller than a corresponding space constraint of the space constraints indicates a color violation.

Abstract: A method for generating physical design layout patterns includes the step of selecting one or more physical design layouts, a given physical design layout comprising a set of physical design layout patterns for features in at least one layer of a given patterned structure. The method also includes the step of converting the physical design layout patterns into coordinate arrays, a given coordinate array comprising feature center coordinates for the features in a given one of the physical design layout patterns. The method further includes the step of training, utilizing the coordinate arrays, a generative adversarial network (GAN) comprising discriminator and generator neural networks. The method further includes the step of generating one or more synthetic coordinate arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic coordinate arrays comprising feature center coordinates of features for a new physical design layout pattern.

Abstract: In a method, system, apparatus, and computer-readable device having instructions for collaboration within a visualization application, a visualization application is used to display a visualization for at least a portion of an object, wherein the object comprises a plurality of parts, a request is received to display collaboration data for a part of the object using the input device, information is received about a part, wherein the information comprises details about the part, an association between collaboration data and visualization data for a part of an object is retrieved and the collaboration data comprises data input by one or more to be associated with the part of the object, and information is displayed about a part and collaboration data associated with the visualization for the part of the object.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include providing an electronic design having a plurality of geometric elements and generating a non-design element. Embodiments may further include associating the non-design element with one of the plurality of geometric elements and storing the non-design element with the one of the plurality of geometric elements. Embodiments may also include displaying, at a graphical user interface, the non-design element upon selection of the geometric element.

Abstract: A circuit configuration optimization apparatus includes a machine learning device that learns a circuit configuration of a FPGA device. The machine learning device observes circuit configuration data of the FPGA device and FPGA error occurrence state data indicating an error occurrence state of the FPGA device as state variables that express a current state of an environment. In addition, the machine learning device acquires determination data indicating propriety determination results of an operating state of the FPGA device. Then, the machine learning device learns the circuit configuration of the FPGA device in association with the FPGA error occurrence state data, using the state variables and the determination data.

Abstract: Generating a routing between pins of a semiconductor device may include selecting one or more of candidate pins of the semiconductor device, generating a net list associated with the selected pins generating an interface script to execute the net list in a library-based disposition and wiring tool that is driven in a computer system, and executing the interface script through the library-based disposition. Pins may be selected from the candidate pins based on at least one of density, shapes, intervals, and sizes among the candidate pins. The net list may define a set of electrical connections between the selected pins.

Abstract: A method of forming an integrated circuit includes generating, by a processor, a layout design of the integrated circuit based on a set of design rules and manufacturing the integrated circuit based on the layout design. The integrated circuit has a first gate. Generating the layout design includes generating a set of gate layout patterns, generating a cut feature layout pattern and generating a first via layout pattern. The cut feature layout pattern extends in a first direction, is located on the first layout level and overlaps at least a first gate layout pattern. The set of gate layout patterns extends in a second direction and is located on a first layout level. The first via layout pattern is over the first gate layout pattern, and is separated in the second direction from the cut feature layout pattern by a first distance. The first distance satisfies a first design rule.

Abstract: The present embodiments relate to implementing an integrated circuit design where a layout of circuit cells on a semiconductor chip is based on positions of the circuit cells on a schematic. According to some aspects, embodiments relate to a method for identifying a plurality of sub-regions on a semiconductor chip layout where each sub-region has a placement constraint. The method further includes assigning circuit cells to sub-regions based on the constraints. The method also includes clustering the circuit cells into clusters based on their positions on the schematic. Circuit cells from each cluster are placed in one or more of the sub-regions based on the proximity of the centers of the clusters to the centers of the sub-regions.

Abstract: A computing device translates each of a group of structured language graphical process flow element representations, that each represents within a structured language one node of a captured graphical process flow diagram of a first business process, into one of a group of numerical strings that each represents within a set of data fields the respective node and connections to and from the respective node. The group of numerical strings is sequenced in accordance with values of the respective data fields within each numerical string that represents the respective node and the connections to and from each represented node of the captured graphical process flow diagram of the first business process.

Abstract: Disclosed are techniques for implementing routing aware placement for an electronic design. These techniques identify a block having one or more first pins or interconnects to be inserted into a first layer corresponding to a first set of tracks and identify a second set of tracks on a second layer adjacent to the first layer. One or more candidate locations may be generated on the first layer for the block based in part or in whole upon the first set of tracks. The block may be inserted into a candidate location on the first layer based in part or in whole upon respective costs or routability of the one or more candidate locations with respect to the second set of tracks.

Abstract: The inspection support device is provided with a camera provided on a moving body so as to be capable of imaging a circuit board, and an imaging control section configured to control imaging processing of the camera and acquire image data of an inspection component, which is a component that is a target for inspection among electronic components mounted by the component mounter, when the inspection component is mounted on the circuit board. The imaging control section optimizes the performance sequence of multiple of the mounting operations and multiple of the imaging operations based on a moving distance of the moving body during the performance sequence or based on a time required for the mounting operation and the imaging operation during the performance sequence.

Abstract: Methods and apparatus are disclosed for symbolic methods using algebraic geometry (e.g., based on a Gröbner basis of tangent space polynomials of parametric curves). For example, the design, optimization and verification of silicon photonic wave guides using parametric polynomials and/or Gröbner basis functions can be used to perform envelope generation, rectification, manufacturability checking, singularity detection, reticle and etch processing model generation, tapering loss minimization, and bend loss minimization. In one example, a method of analyzing a layout to be manufactured using a photolithographic process includes producing an envelope of a curve representing a layout object based at least in part on a Gröbner basis and performing one or more analysis operations for the envelope to perform verification and manufacturability checks.

Abstract: Always-on (AO) tie cells, whose power supply has to remain on when the primary supply to the power domain is off, are used to implement logic constants. In accordance with embodiments of the present disclosure, insulated and non-insulated AO tie cells improve the QoR of the layout design and lower the power consumption.

Abstract: An image editing method comprises: a step of acquiring identification information on each of a plurality of operation instruction units for instructing editing of an image, a step of automatically selecting one or more images for editing from a group of images to classify the one or more images into a group of usable images based on the identification information, a step of determining a right to edit reaching contents of processing which each operation instruction unit is authorized to perform against each image in the group of usable images, and a step of performing editing processing on an image to be edited in the group of usable images based upon the determined right to edit according to an editing instruction supplied from each operation instruction unit.

Abstract: A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.

Abstract: This application discloses a computing system to parse a product model definition that includes a layout design of a printed circuit board assembly, which identifies physical design characteristics of the layout design of the printed circuit board assembly. The computing system can identify one or more manufacturing processes capable of manufacturing at least a portion of the printed circuit board assembly having the identified physical design characteristics. The computing system can include a map or correlation between the manufacturing processes and manufacturing-related design constraints. The computing system can select one or more manufacturing checks that define manufacturing-related design constraints correlated to the identified manufacturing processes.

Abstract: A method for determining system reliability of a logic circuit, wherein a functional component model for design/simulation of a circuit model of the logic circuit is created, where functional components model are expanded by adding an associated power model, a temperature model, and a reliability, where the logic circuit is constructed with expanded model components and, based on simulation of the logic circuit aided by the constructed circuit model, a functional, a power-dependent, and a temperature-dependent behavior and a temperature-dependent failure rate are derived for each component in a component specific manner for a specified application case, and where in addition to the functional behavior, a power and temperature behavior and a total failure rate can be determined simply and dynamically, based on the derived data and dependent on temperature and simulation time for the logic circuit for the specified application case.

Abstract: A method, system, and computer program product for performing incremental common path pessimism analysis in integrated circuit design includes performing common path pessimism removal (CPPR) analysis to provide timing credit for one or more paths that are subject to common path pessimism. The method also includes identifying one or more post-CPPR critical paths based on the CPPR analysis, setting flags for critical nodes of the one or more post-CPPR critical paths, performing a design fix to address the one or more post-CPPR critical paths, and applying a set of rules based on the design fix and the flags to identify seed points among the critical nodes of the one or more post-CPPR critical paths. Invalidating and re-performing the CPPR analysis is done only for paths associated with the seed points.

Abstract: A circuit including an SRAM cell with a set of vertical nanowire transistor columns is provided. Each member of the set includes a vertical nanowire transistor and at least one member of the set is a vertical nanowire transistor column including two vertical nanowire transistors in series. The set can consist of four vertical nanowire transistor columns, a first column including two n-type vertical nanowire transistors, a second column including two n-type vertical nanowire transistors, a third column including one p-type vertical nanowire transistor and a fourth column including one p-type vertical nanowire transistor. EDA tools for such circuits are also provided.

Abstract: A method for designing an integrated circuit die, the method including generating a first layout for the die which includes at least one decap; and performing a post-processing decap insertion operation to add at least one additional decap in excess of the at least one decap, the operation including: for at least a portion of the first layout, identifying at least some of whichever locations in at least the portion have positive slack, as “candidate” locations; and inserting at least one additional decap at at least one respective location from among the “candidate” locations.

Abstract: A layout design system, semiconductor device using the layout design system, and fabricating method thereof are provided.

Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a memory cell array; a standard cell region in which first type standard cells implemented to perform a first operation for accessing the memory cell array and second type standard cells performing the first operation and having performance characteristics different from performance characteristics of the first type standard cells are arranged; and a ROM including a program that performs place and route for the standard cells arranged in the standard cell region.

Abstract: Disclosed are techniques for implementing three-dimensional or multi-layer integrated circuit designs. These techniques identify an electronic design and a plurality of inputs for implementing connectivity for the electronic design. Net distribution results may be generated at least by performing one or more net distribution analyzes. A bump in a bump array may then be assigned to a net that connects a first layer and a second layer in the electronic design based in part or in whole upon the net distribution analysis results.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method comprises forming active patterns on a substrate that includes first and second logic cell regions adjacent to each other in a first direction, and forming on the substrate a device isolation layer exposing upper portions of the active patterns. The forming the active patterns comprises forming first line mask patterns extending parallel to each other in the first direction and running across the first and second logic cell regions, forming on the first line mask patterns an upper separation mask pattern including a first opening overlapping at least two of the first line mask patterns, forming first hardmask patterns from the at least two first line mask patterns, and etching the substrate to form trenches defining the active patterns.

Abstract: There is provided a method of verifying a Fin-based integrated circuit layout in a layout verifying system. The method includes receiving a layout corresponding to a specific integrated circuit unit, extracting one or more device codes from the layout, and synthesizing a code stream using the one or more extracted device codes according to a gate line sequence. Each device code is based on a corresponding gate line unit in the layout that includes an active region, gate lines, and a number of intersecting points with silicon fins of the layout.

Abstract: According to embodiments of the present invention are systems and methods for using scan chains for the creation of unique physically uncloneable function (PUF). In particular, the present invention uses existing circuitry on an integrated circuit and the internal-scan or boundary-scan register to create a unique identifier for each integrated chip. The unique nature of the scan chains results from the inherent variability of the manufacturing process.

Abstract: A method of designing a layout of a semiconductor device includes receiving information on a size of a target chip and a unit placement width for forming a gate line through a self-align double patterning process by a layout design system. The method also includes allocating an input and output area, a hard macro area, and a standard cell area at the target chip, and adjusting a width of the standard cell area by applying a gate generation rule for setting a width of at least one cell row located in the standard cell area to an odd number multiple of the unit placement width. The unit placement width corresponds to a width between centers of a pair of gate lines in the self-align double patterning process.

Abstract: A standard cell for use within an integrated circuit can be partially personalized by local wiring. The standard cell can include a set of transistors, each having a fixed size and position within an established standard cell perimeter. The set of transistors can be partially interconnected to a set of local nodes by local wiring. Customization ports can be arranged on a global wiring layer and electrically connected to the set of local nodes. A set of blockage in shapes can be arranged to identify, on a global wiring layer, areas reserved for personalization wiring. Personalization wiring can be configured to complete the personalization of the standard cell by electrically interconnecting, on the global wiring layer, some of the set of customization ports.

Abstract: The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.

Abstract: A MOS IC may include a first contact interconnect in a first standard cell that extends in a first direction and contacts a first MOS transistor source and a voltage source. Still further, the MOS IC may include a first double diffusion break extending along a first boundary in the first direction of the first standard cell and a second standard cell. The MOS IC may also include a second contact interconnect extending over a portion of the first double diffusion break. In an aspect, the second contact interconnect may be within both the first standard cell and the second standard cell and coupled to the voltage source. Additionally, the MOS IC may include a third contact interconnect extending in a second direction orthogonal to the first direction and couples the first contact interconnect and the second contact interconnect together.

Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.

Abstract: A computer-implemented method for designing an integrated circuit includes: performing a simulation on input data or an initial layout to determine whether or not a design constraint has been violated. Upon determining that the design constraint has been violated, a redesign layout is created by adding a cutting area without changing a size of the integrated circuit. The adding a cutting area separates at least one of an active region and a gate line. At least one of the initial layout and the redesign layout is stored in a non-transitory computer readable storage medium.

Abstract: A method for fabricating an interposer wafer includes providing at least one mask having printing regions for forming a plurality of interposer designs; selecting an interposer design; and forming the interposer design on a substrate using a plurality of lithographic imaging steps. For each lithographic imaging step, at least one portion of the interposer design is printed by exposing at least one of the printing regions while blocking at least one other of the printing regions.

Abstract: Embodiments include a computer implemented method comprising: while designing a chip, identifying a plurality of partitions in the chip, for a first partition of the plurality of partitions in the chip, identifying a plurality of pins configured to interconnect the first partition with one or more other partitions of the plurality of partitions of the chip, assigning a name to each of the plurality of pins associated with the first partition of the plurality of partitions, based on the names assigned to each of the plurality of pins, forming a plurality of groups such that each group of the plurality of groups is associated with a corresponding one or more pins of the plurality of pins, and based on forming the plurality of groups, designing a first subset of the plurality of pins to be located at close proximity in the chip.

Abstract: A method of designing an integrated circuit is described. The integrated circuit comprises a plurality of circuit components, including one or more functional components and one or more tile shapes. A pcell instance may be defined to specify a functional component along with one or more tile shapes. The tile shapes are thus associated with the functional component. A netlist may be arranged to specify interconnections between the functional components of the integrated circuit as well as electrical interactions between the tile shapes and functional components. A computer program product for carrying out the method is also described.