Abstract: A design support method executed by a computer includes: detecting a layout position of a first terminal in a cell as a first layout position from layout data including a cell of a macro which is arranged at a plurality of orientations, the first terminal being arranged at a first orientation; calculating a second layout position of a first terminal which is arranged at a second orientation which is different from the first orientation based on a variation from the first orientation to the second orientation and the first layout position; associating the second layout position with the first layout position and the layout data; and outputting an association result.

Abstract: Techniques for determining resistances of analog routes in electronic designs are described herein. In an example embodiment, a computer system receives first user input that indicates, in a user interface, a first component in an electronic design. The electronic design has been placed and routed for a programmable target device. The computer system receives second user input that selects, in the user interface, a particular component from one or more second components of the electronic design, where the one or more second components have analog connectivity to the first component. The computer system determines a resistance value of an analog route between the first component and the particular component, and displays the resistance value in association with the analog route in the user interface.

Abstract: A structure includes a substrate having a plurality of balls, a semiconductor chip, and an interposer electrically connecting the substrate and the semiconductor chip. The interposer includes a first side, a second side opposite the first side, at least one first exclusion zone extending through the interposer above each ball of the plurality of balls, at least one active through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one active through via is formed outside the at least one first exclusion zone and wherein no active through vias are formed within the at least one first exclusion zone, and at least one dummy through via extending from the first side of the interposer to the second side of the interposer, wherein the at least one dummy through via is formed within the at least one first exclusion zone.

Abstract: Based upon a layout of a semiconductor wafer comprising a plurality of integrated circuits at pre-defined locations, each integrated circuit comprising a set of electrical connection pads, a probe chip contactor is established, having a unit standard cell on the probe side of the probe chip to correspond to each of the arranged integrated circuits. The unit standard cell is stepped and repeated for the probe side of the probe chip contactor, to establish a wafer scale standard cell layout. The opposite contact side of the probe chip contactor is connectable to a central structure, e.g. a Z-block or PC board, typically comprising a fixed array of vias with fixed X, Y, and Z locations. The routing of contact side of the probe chip contactor is preferably routed automatically, such as implemented on one or more computers, to provide electrical connections between the substrate through vias and the Z-block through vias.

Abstract: Disclosed herein are rouging methods and devices for a flip-chip package. The flip chip includes several outer pads and several inner pads. The routing method includes: setting an outer sequence based on the arrangement order of the outer pads; setting several inner sequences based on the connection relationships between inner pads and the outer pads; calculating the longest common subsequence of each inner sequence and the outer sequence, defining the connection relationships between the inner pads and the outer pads corresponding to the longest common subsequence as direct connections, and defining the connection relationships between the inner pads and the outer pads that do not correspond to the longest common subsequence as detour connections; establishing the routing scheme of the flip chip based on the connection relationships between the inner pads and the outer pads.

Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Abstract: A method may include receiving circuit information from a backend circuit test system and grouping components in the circuit information into collections by types, the types including segments, equipment, ports, and connections. The method may further include positioning, based on the grouping by types, the components from the circuit information for presentation of a circuit design on a display, and performing path rendering for the circuit design based on the positioning of the components. The method may also include sending an output file with the path rendering to a web browser.

Abstract: A method is provided for optimized buffer placement based on timing and capacitance assertions in a functional chip unit including a single source and multiple macros, each having a sink. Placement of the source and macros with the sinks is pre-designed and buffers are placed in branches connecting the source with the multiple sinks. The method includes: calculating an estimated slack for each branch based on cycle reach, calculating a minimum slack for each branch, arranging branches according to the calculated slack to evaluate at least one most critical branch, inserting decoupling buffers in all branches except the most critical branch(es) and placing decoupling buffers close to the source, globally routing the most critical branch(es) and fixing slew conditions within this branch, globally routing at least one subsequent branch as arranged according to the calculated slack and fixing slew conditions within this branch(es), and routing all remaining branches.

Abstract: A computer identifies a metal layer, in a design, which contains routing track segregated by blockages. The sections of segregated routing track are removed and new routing track are added along the periphery of the blockage. It is determined if contact can be created between the component and the new routing track with the addition of a vertical interconnect access (VIA) structure. If contact can be created, then the VIA structures are added to create contact. If no contact can be created then another new routing track is added with (VIA) structures such that contact is created. Further routing track and VIA structures are added to higher metal layers to form a connection between a routing terminus located on a top metal layer and the new routing track and component.

Abstract: In a particular embodiment, a method is disclosed that includes automatically adding a first power line in a channel between at least two macros when less than two system power supply lines with opposite polarities are detected within the channel.

Abstract: A semiconductor integrated circuit includes: a semiconductor chip; a through-chip via passing through a conductive pattern disposed in the semiconductor chip and cutting the conductive pattern; and an insulation pattern disposed on an outer circumference surface of the through-chip via to insulate the conductive pattern from the through-chip via.

Abstract: A finFET block architecture includes a first set of semiconductor fins having a first conductivity type, and a second set of semiconductor fins having a second conductivity type. An inter-block insulator is placed between outer fins of the first and second sets. A patterned gate conductor layer includes a first plurality of gate traces extending across the set of fins in the first block without crossing the inter-block insulator, and a second plurality of gate traces extending across the set of fins in the second block without crossing the inter-block insulator. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and include an inter-block connector arranged to connect gate traces in the first and second blocks.

Abstract: An object is to provide a semiconductor device in which it is possible to determine whether or not a minute delay time given by a delay circuit is within a specified value or not, and a method of testing the semiconductor device. In response to a data strobe signal TDQS for testing, the delay circuits DC0 and DC1 produce delay data strobe signals IDQS0 and IDQS1 delayed by delay times DT0 and DT1. Outputted as a reverse signal from the inverter INV0, is a reverse data strobe signal RIDQS0 in response to the delay data strobe signal IDQS0, and delayed by an allowable delay time IT. Inputted into the NAND gate ND0, are the reverse data strobe signal RIDQS0 and the delay data strobe signal IDQS1. When, in comparison with the phase of the delay data strobe signal IDQS0, the phase of the delay data strobe signal IDQS1 is delayed by the allowable delay time IT or more, a pulse signal PL0 is not outputted from the NAND gate ND0.

Abstract: Multiple level spine routing is disclosed. In some embodiments, in response to receiving a specification of a plurality of nets and a specification of a set of routing tracks available for main spines, a main spine routing track is assigned to each of the plurality of nets based at least in part on a cost function and main spine wires are generated on the assigned main spine routing tracks for each of the plurality of nets.

Abstract: Disclosed are a method, apparatus, and computer program product to implement routing for double patterning lithography. A three-phase routing scheme is employed, comprising a global router, a C-router, and a detail router. The C-router provides double patterning color seeding for shapes on routing tracks in the electronic design. The detail router employs space-tiles to perform double-patterning based routing for wires in the electronic design.

Abstract: A method for designing an electronic circuit including determining at least one hold violation in a net routing; inserting a routing blockage associated with each at least one hold violation; de-routing the determined net-routing and re-routing the determined net-routing dependent on at least the routing blockage.

Abstract: During a calculation technique, contributions to reflected light from multiple discrete cells in a model of a multilayer stack in a reflective photo-mask may be determined based on angles of incidence of light in a light pattern to the multilayer stack, a polarization of the light in the light pattern, and a varying intensity of the light in the light pattern through the multilayer stack. Then, phase values of the contributions to the reflected light from the multiple discrete cells are adjusted, thereby specifying optical path differences between the multiple discrete cells in the multilayer stack that are associated with the defect. Moreover, the contributions to the reflected light from multiple discrete cells are combined to determine the reflected light from the multilayer stack. Next, k-space representations of the contributions to the reflected light from the multiple discrete cells are selectively shifted based on the angles of incidence.

Abstract: An automatic wiring method includes calculating a metal area within an integrated circuit, and determining whether the metal area calculated at the calculating is smaller than a minimum metal area as a predetermined threshold value.

Abstract: According to an embodiment an improved Application Specific Integrated Circuit (ASIC) isolation method and system for assigning signal pins in an ASIC package having a plurality of signal pins is disclosed. The method and system comprise identifying an isolation requirement of the ASIC and determining an optimized pattern for substantially diagonal pairing of signal pins in relation to the isolation requirement. The method includes pairing signal pairs substantially diagonally in accordance with the pattern.

Abstract: Systems and methods for wire routing using virtual landing pads (VLPs) are described. In an embodiment, a method includes routing a wiring path between an output of a first circuit component and a VLP that represents an input of a second circuit component. For example, the VLP may have an area larger than the area of a physical pin of the second circuit component. The method may also include identifying a connection point on the VLP that is separated from an actual terminal of the second circuit, and completing the path between the connection point and the actual terminal. In some embodiments, the output of the first circuit component may also be represented by its own VLP. As such, systems and methods described herein may allow a circuit designer to perform routing procedures in a complex, highly integrated circuit, while reducing the circuit's overall capacitance and associated power consumption.

Abstract: An integrated circuit structure includes a chip including a substrate and a power distribution network. The power distribution network includes a plurality of power through-silicon vias (TSVs) penetrating the substrate, wherein the plurality of power TSVs forms a grid; and a plurality of metal lines in a bottom metallization layer (M1), wherein the plurality of metal lines couples the plurality of power TSVs to integrated circuit devices on the substrate.

Abstract: Methods and/or associated devices and/or systems for creating integrated circuits (IC's) that have multiple connected I/O regions that can be designed and implemented using commonly available standard I/O libraries in conjunction with standard IC design flows and tools and in combination with one or more novel standardized I/O region interconnect cells for interconnecting between or through otherwise separated I/O regions. Specific embodiments support a wide variety of IC's that can be developed using standard libraries and design flows including: application specific integrated circuits (ASIC's), programmable logic devices (PLDs), custom IC's, analog IC's, CPU's, GPU's, and other IC's that require large numbers of input/ouput (IO) circuits while having relatively small core circuitry areas. Specific embodiments may involve innovative I/O cell functions, innovative IC topologies, and innovative IC packaging solutions for single die packages and multiple die packages.

Abstract: In one embodiment of the invention, an object oriented autorouter is disclosed for routing nets in a circuit. The object oriented autorouter includes a routing data model (RDM); at least one routing engine, such as a single connection router (SCR), a topographical (TOPO) transformation engine, and a detail geometric (DETAIL) engine, and a command and control module (CCM) coupled together. The RDM reads and write data with a design database as well as reading one or more object oriented design constraints. Each of the routing engines have at least one action to operate on the design database to improve compliance of the circuit to a constraint. The CCM controls the overall routing process of the nets in the circuit and includes at least one director to invoke at least one of the routing engines to achieve compliance with one or more constraints.

Abstract: Disclosed is a method, apparatus, and program product for routing an electronic design using sidewall image transfer that is correct by construction. The layout is routed by construction to allow successful manufacturing with sidewall image transfer, since the router will not allow a routing configuration in the layout that cannot be successfully manufactured with a two-mask sidewall image transfer. A layout is produced that can be manufactured by a two-mask sidewall image transfer method. In one approach, interconnections can be in arbitrary directions. In another approach, interconnections follow grid lines in x and y-directions.

Abstract: An assignment method of terminals of a semiconductor package executed by an assignment supporting apparatus includes: deciding a maximum allowable distance to be a constraint condition regarding a relative distance between each of the pads and a terminal to be assigned to the pad, and extracting one or a plurality of assigned terminal candidates for each of the pads so that the relative distance between each of the pads and a terminal selected for the pad falls within a range of the maximum allowable distance; and deciding one of the terminals as a assigned terminal based on the assigned terminal candidates and assigning the one of the terminals to one of the pads. The process is a process to assign one of the terminals with priority to a pad having a smallest number of assigned terminal candidates in a not-assigned condition based on the assigned terminal candidates.

Abstract: Generating a physical circuit board design. The physical circuit board is designed based on a design data set containing multiple electronic components. In a first step, the electronic components are classified by assigning them either to a group of so-called Core Components or to a group of Application Specific Components. Subsequently, a circuit board layer structure is generated. The layer structure includes a Core Layer Structure located in the center of this layer structure. The components are placed onto the board's layer structure in such a way that the Core Components are placed onto the Core Layer Structure. Finally, a design macro of the resulting physical design is generated and the circuit board is assembled.

Abstract: The present disclosure is directed to a method for extracting information for a circuit design. The method may utilize an incremental extraction process for extracting information for a portion of the circuit design. Extracted results of this portion may be merged with a previously extracted result to obtain an integrated result that is equivalent to that of extracting the entire circuit design. The incremental extraction process may identify a set of changed shapes, a set of affected shapes, and a set of involved shapes for extraction. The method may also divide the circuit design into a plurality of regions, wherein two or more regions may be processed in parallel.

Abstract: A method for designing a system on a target device includes identifying candidate portions in the system to preserve based on similarities between the system and another system. Preservation criteria are applied on the candidate portions in the system to preserve to identify portions of the system to preserve. Design results from the another system are reused for portions in the system that are preserved.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: A computer-readable recording medium stores a program that causes a computer to execute a circuit design process. The process includes selecting component data in first board data from among the first board data including first connector component data and second board data including second connector component data that is associated with the first connector component data; setting a connection destination net name of the selected component data to a first vacant terminal of the first connector component data; and setting the connection destination net name of the component data to a second vacant terminal of the second connector component data that corresponds to the first vacant terminal of the first connector data when the component data is moved from the first board data to the second board data.

Abstract: A macro layout verification apparatus for verifying a layout of a macro to be placed as a functional block on a semiconductor device. The apparatus includes: a unit, which assumes as a virtual wiring line, a wiring line that uses an unused intra-macro channel located adjacent to an intra-macro wiring line; a unit which calculates a parallel wiring length along which the virtual wiring line and the intra-macro wiring line run; and a unit which outputs information concerning the virtual wiring line when the parallel wiring length exceeds a reference value defined as a design rule.

Abstract: A vertically stackable die having a chip identifier structure is disclosed. In a particular embodiment, a semiconductor device is disclosed that includes a die comprising a first through silicon via to communicate a chip identifier and other data. The semiconductor device also includes a chip identifier structure that comprises at least two through silicon vias that are each hard wired to an external electrical contact.

Abstract: A method is provided for testing a circuit design in a programmable IC. The circuit design and a sampling circuit are implemented in the programmable IC. A first routing circuit is implemented in the programmable IC to route signals from the designated locations of a first subset of a set of test nodes of the circuit design to a set of input nodes of the sampling circuit. Signals are sampled from the first subset of test nodes using the sampling circuit. The programmable IC is partially reconfigured to implement a second routing circuit that replaces the first routing circuit. The second routing circuit is configured to route signals from a second subset of the set of test nodes to the set of input nodes of the sampling circuit. Signals from the second subset of test nodes are sampled using the sampling circuit.

Abstract: A printed circuit board includes a group of pads suitable to be soldered to a respective group of solder-balls of a device. Each pad of the group has a crack initiation point on its perimeter at a location where cracks in a solder-ball are anticipated to start after that solder-ball is soldered to that pad. For a pad of that group having a microvia located therein, a center of that microvia is located farther than a center of that pad from its crack initiation point. For a pad of that group having a trace merging along a portion of its perimeter, that portion does not include a vicinity of that crack initiation point.

Abstract: Embodiments of the present invention provide a method and system for clock-gating a circuit. During operation, the system receives a description of a circuit that includes clocked memory elements, some of which are clock-gated. Next, the system identifies a sender memory element by identifying a sender path from an output of the sender memory element to a data input for a seed memory element. Then, the system identifies an enable-generating memory element by identifying an enable-signal path from an output of the enable-generating memory element to an enable signal which is used to gate a clock signal input for the seed memory element. Next, the system provides clock-gating for the sender memory element by generating an enable signal using a data input for the enable-generating memory element. Finally, the system gates a clock signal for the sender memory element using this generated enable signal.

Abstract: A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Abstract: Some embodiments of the present invention provide systems for generating and using a route fix guidance for fixing design rule violations. A route fix guidance includes information that enables a router to locally modify a routing solution to fix one or more design rule violations. A route fix guidance can include a set of two or more metal avoidance areas, wherein avoiding any one of the set of two or more metal avoidance areas during routing fixes the design rule violation. Additionally, a route fix guidance can specify a set of rectangles to remove from a routing solution, and a set of rectangles to insert into or add to a routing solution. Further, the route fix guidance can include information for moving one or more vias to new locations in the routing solution. The route fix guidance can specify a sequence in which the local modifications are to be made.

Abstract: A method of connecting an interface to a fabric of an electronic device, the interface having a plurality of nets to be connected to corresponding connectors in the fabric includes associating with each of the connectors in the fabric a first variable indicating that the connector belongs to the interface; associating with each of the connectors in the fabric a second variable indicating a number of higher numbered adjacent connectors for the connector in the interface; connecting each of the nets in the interface to a corresponding one of the connectors in the fabric such that the second variable has a non-zero value at exactly one of the corresponding connectors in the interface.

Abstract: By carrying out circuit simulations, paretos that are non-dominated solutions in a solution specification space for respective items in the requirement specification are obtained for all of circuit configurations having possibility that requirement specification is satisfied, and a provisional optimal solution, which is on a pareto curved surface identified by the obtained paretos and whose distance with the requirement specification is shortest, is identified. Furthermore, a circuit configuration corresponding to the provisional optimal solution is identified and the provisional optimal solution is mapped to values of circuit parameters. Then, the pertinent circuit configuration and values of the circuit parameters, which are obtained by the mapping, are outputted.

Abstract: A method of generating resistance-capacitance (RC) technology files is disclosed. The method comprises receiving a plurality of metal schemes from an IC foundry and dividing the plurality of metal schemes into one or more modular RC groups. The method further comprises identifying a modular RC structure; calculating capacitance values of the modular RC structure by means of a field solver; calculating an equivalent dielectric constant and an equivalent height of the RC structure based upon a variety of interconnect layers not having interconnects; calculating an equivalent dielectric constant and an equivalent height for each of the plurality of metal schemes; and deriving capacitance values of each of the plurality of metal schemes from the capacitance values of the modular RC structure.

Abstract: Approaches for placement and routing of a circuit design are disclosed. Two or more modules of a circuit design are assigned to respective regions of a programmable integrated circuit. Placement and routing constraints are created for non-global resources of two or more modules of the circuit design. The placement and routing constraints restrict placement and routing of non-global resources of each of the two or more modules to respective regions of a programmable IC. Each non-global resource is used by at most one of the two or more modules. The two or more modules are placed. In response to the one of the placed circuit elements not being placed within the assigned region, the routing constraint on the one of the circuit elements is removed. The circuit design is routed.

Abstract: The exemplary embodiments provide a program binder for a resilient integrated circuit. An exemplary IC comprises a plurality of composite circuit elements, a state machine element (SME), and a plurality of communication elements. Each composite circuit element comprises an element interface and a selected circuit element which may vary by element type, and which may be configurable. An exemplary program binding method includes assigning a first action to a first computational element having a first type; assigning a second action to a second computational element having a second type; and establishing a first data routing, through a selected communication element, between the first computational element and the second computational element. In the event of detection of a fault with a composite circuit element or a communication element, the various actions may be re-assigned and new data routings established.

Abstract: A cell-based architecture for an integrated circuit. A row of cell instances borders a first adjacent row of cell instances along a first boundary and a second adjacent row of cell instances along a second boundary. A first power rail (e.g., carrying an auxiliary voltage) extends along the first boundary. A second power rail (e.g., VSS) extends along the second boundary. The second power rail is wider than the first power rail. Additionally, a third power rail (e.g., VDD) extends across the interior of the second row of cells.

Abstract: A system and method are provided for reducing signal skew. The method includes receiving a netlist having components and connections among the components. Each connection has at least one signal wire. A plurality of net groups is identified, each net group including at least some of the connections and for which equivalent routing is desired. For each net group, the method includes systematically routing connection paths between the components for the connections, each connection path extending between an output of one of the components and an input to at least one other of the components and including at least one path fragment. Routing includes, for at least one of the connections of the net group, routing at least one grounded shielding wire in a routing channel adjacent and parallel to at least one of the path fragments of the connection path.

Abstract: A design rule check system includes: a design rule check unit that performs a design rule checks on wiring information which indicates a wiring pattern of a net on the basis of a design rule which includes a constraint condition of a wiring pattern; and a screening processing unit which generates information about an error for each clock frequency of each net based on a result of the design rule check and outputs the information to an indicating device.

Abstract: A method for designing a system on a target device includes entering the system. The system is synthesized. The system is mapped. The system is placed on the target device. The system is routed. Physical synthesis is performed on the system immediately after more than one of the entering, synthesizing, mapping, placing and routing procedures.

Abstract: Some aspects of this disclosure provide for electronic design automation (EDA) techniques that check whether individual blocks, such as transistors or other semiconductor devices, are connected to their correct power domains during design. In this way, the disclosed EDA techniques can limit or prevent overstress conditions applied to blocks and help to improve reliability of integrated circuits, when manufactured.

Abstract: A method of generating electrical rule file for circuit board by using an electronic device. The electronic device acquires a component file, a wiring file, a wiring group file, a first electrical rule file, and a second electrical rule file from a storage device. The electronic device integrates the component file and the wiring file to be an integrated file according to wire names, acquires group names and inserts the group names into the integrated file according to the wire names, acquires first electrical rules and inserts the first electrical rules into the integrated file according to the group names, acquires second electrical rules and inserts the second electrical rules into the integrated file according to the group names, to complete the integrated file, and saves the completed file to the storage device.

Abstract: Systems and techniques are described for optimizing placement and routing by providing global information during early stages of a computer aided design (CAD) flow to produce better place and route solutions. Moreover, the systems and techniques described herein use natural connectivity information inherently provided in a design hierarchy.

Abstract: A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.