Abstract: A method and system for supporting simultaneous operation of operating systems on a single integrated circuit. The system includes a supervisory operating system (SOS) managing execution of instructions, each instruction being executable under one of the operating systems; registers grouped into multiple sets of registers, each set maintaining an identity of one of the operating systems; and a dispatcher capable of dispatching an instruction and a tag attached to the instruction, the tag identifying one of the operating systems and the instruction to be executed under the identified operating system to access one of the registers. One or more of the registers are utilized when the instruction is executed, and are included in a single set of the multiple sets of registers. The single set maintains the identity of the operating system identified by the tag, and each of the one or more registers includes an identifier matching the tag.

Abstract: There is disclosed a method, apparatus and computer program product for receiving a message, the message being processable by a component on one of a plurality of processing threads. A message is received from a first component on a current thread. The communication style that was used by the first component is determined. Responsive to receipt of the message, the communication style that is desired to be used by a second component is determined. Responsive to determining that the two components are asynchronous, communication takes place with the second component using the current thread.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor having a plurality of thread contexts (TCs), a translation lookaside buffer (TLB) shared by the plurality of TCs, and an instruction scheduler, coupled to the plurality of TCs, configured to dispatch to execution units, in a multithreaded fashion, instructions of threads executing on the plurality of TCs. The system also includes a multiprocessor operating system (OS), configured to schedule execution of the threads on the plurality of TCs, wherein a thread of the threads executing on one of the plurality of TCs is configured to update the shared TLB, and prior to updating the TLB to disable interrupts, to prevent the OS from unscheduling the TLB-updating thread from executing on the plurality of TCs, and disable the instruction scheduler from dispatching instructions from any of the plurality of TCs except from the one of the plurality of TCs on which the TLB-updating thread is executing.

Abstract: A multi-tasking operating system and method updates PCI address values in an extension register to ensure that various threads utilize the correct values when accessing peripheral PCI devices. When application program threads require access to a PCI device, the operating system writes the high order bits of the PCI device address to two places: (1) the extension register of the PCI host bridge to allow immediate addressing of the PCI device, and (2) separate memory locations associated with the threads. When a context switch occurs from a first thread to a second thread, the operating system retrieves the stored value from the memory location associated with the second thread and writes the value to the extension register. In this manner, when the second thread requires access to its PCI device, the proper address value is already located in the extension register.

Abstract: Systems and methods of sharing processing resources in a multi-threading environment are disclosed. An exemplary method may include allocating a lock value for a resource lock, the lock value corresponding to a state of the resource lock. A first thread may yield at least a portion of the processing resources for another thread. The resource lock may be acquired for the first thread if the lock value indicates the resource lock is available.

Abstract: Methods, systems, apparatuses and program products are disclosed for providing for communications within an environment that provides for execution isolation, especially a DXE (Driver Execution Environment) phase of a PC (personal computer) startup process. Provision is made for blocking of server threads awaiting service requests and blocking client thread awaiting server responses, together with marshalling formal parameter descriptions and service request/response arguments across disparate execution contexts that disallow simple data redirection between them.

Abstract: Methods, systems, apparatuses and program products are disclosed for providing execution context isolation during the DXE phase of computer start-up. Provision is made for referencing and dereferencing execution contexts and thereby providing execution isolation across contexts.

Abstract: Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Abstract: An automated technique for switching operating systems, responsive to current context of an executing test scenario. A test designer specifies, in a process control file, a required operating system for appropriate command blocks. A test sequencer packages the required operating system name with each command to be executed, and sends that information to a test listener on a system under test. The test listener remembers the currently-running operating system, and compares that to the required operating system for each command to be executed. If a mismatch occurs, then the correct operating system is not running, and the listener automatically triggers a reboot.

Abstract: A microprocessor executes programs in a pipeline architecture including a task register management unit that, if a switch instruction to a second task is issued when a plurality of units executes a first task, switches a value of a task register to second register information that is used when the second task is executed after the execution of the first task is completed and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.

Abstract: A system to control access to a resource by a group of threads requiring access to the resource provides exclusive access to the resource within a computerized device on behalf of a first thread by allowing the first thread exclusive access of a monitor associated with the resource. An entry list of threads is maintained that are awaiting access to the monitor using block-free list joining mechanisms including a thread chaining technique, a push/pop technique, and a detach, modify, reattach technique to allow threads to join the entry list of threads without blocking operation of the threads. Upon completion of access to the resource by the first thread, the system operates the first thread to manipulate the entry list of threads to identify a successor thread as being a candidate thread to obtain exclusive access of the monitor to gain exclusive access to the resource.

Abstract: In one embodiment, a method includes transitioning control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a VMM timer indicator is set to an enabling value, and identifying a VMM timer value configured by the VMM. The method further includes periodically comparing a current value of a timing source with the VMM timer value, generating an internal event if the current value of the timing source has reached the VMM timer value, and transitioning control to the VMM in response to the internal event without incurring an event handling procedure in any one of the VMM and the VM.

Abstract: The present invention is directed to systems and methods for providing disaster recovery services using virtual machines. The invention provides an inexpensive and minimally intrusive way to provide disaster recovery services including recovery of the state of computer processors and devices. The system includes a production host and a backup host that communicate via a communications link. The state of the processor and devices on the production host are periodically stored onto backup host and can be restored in the event of an emergency. Additionally, the invention includes two business methods for utilizing the system and methods for providing disaster recovery services.

Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.

Abstract: A multiprocessing system is disclosed. The system includes a multithreading microprocessor, including a plurality of thread contexts (TCs), each comprising a first control indicator for controlling whether the TC is exempt from servicing interrupt requests to an exception domain for the plurality of TCs, and a virtual processing element (VPE), comprising the exception domain, configured to receive the interrupt requests, wherein the interrupt requests are non-specific to the plurality of TCs, wherein the VPE is configured to select a non-exempt one of the plurality of TCs to service each of the interrupt requests, the VPE further comprising a second control indicator for controlling whether the VPE is enabled to select one of the plurality of TCs to service the interrupt requests.

Abstract: An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

Abstract: Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.

Abstract: A processor comprises memory circuitry and processing circuitry coupled to the memory circuitry. The processing circuitry is operative to retrieve from the memory circuitry an interrupt polling instruction which causes selection of an active enabled interrupt and generation of an interrupt vector for the selected active enabled interrupt. In conjunction with the selection and generation operations, an execution context of a program thread is stored in the memory circuitry, the stored execution context being utilizable to resume the program thread at an appropriate time subsequent to interruption of that thread.

Abstract: An apparatus and method are disclosed for single-stepping coherence events in a multiprocessor system under software control in order to monitor the behavior of a memory coherence mechanism. Single-stepping coherence events in a multiprocessor system is made possible by adding one or more step registers. By accessing these step registers, one or more coherence requests are processed by the multiprocessor system. The step registers determine if the snoop unit will operate by proceeding in a normal execution mode, or operate in a single-step mode.

Abstract: A mechanism is provided for enabling an auxiliary program to be executed in a computer system, after an operating system has been loaded and executed, without rebooting the computer system. This may be achieved by suspending execution of the operating system, executing the auxiliary program while execution of the operating system is suspended, and then resuming execution of the operating system. In suspending execution of the operating system, state information defining a current state of the computer system is saved. In resuming execution of the operating system, the saved state information is used to restore the computer system to the current state. No state information or data should be lost as a result of suspending and resuming execution of the operating system. From the viewpoint of the operating system and the applications (if any) executing within the environment provided by the operating system, execution of the auxiliary program is transparent.

Abstract: A measurement sampling facility takes snapshots of the central processing unit (CPU) on which it is executing at specified sampling intervals to collect data relating to tasks executing on the CPU. The collected data is stored in a buffer, and at selected times, an interrupt is provided to remove data from the buffer to enable reuse thereof. The interrupt is not taken after each sample, but in sufficient time to remove the data and minimize data loss.

Abstract: The present invention provides a dynamic queue for managing jobs in a threaded computing environment. Jobs may be placed in the queue, which may be maintained within a context of the computing environment, at a given priority level. The priority of jobs within the queue and the receipt time of each job is maintained. A job may also be placed within the queue with triggers that, if met, will result in the priority of the job being changed or will result in the job being removed from the queue entirely. Methods in accordance with the present invention also provide a method for raising an exception should multiple threads seek to access objects within a single context. Methods in accordance with the present invention also provide compatibility with prior computing systems and methodologies by providing for integration of prior static queues with dynamic queues in accordance with the present invention, and by providing methods for a given thread to be pinned to a particular context of a computing environment.

Abstract: Systems and methods are disclosed to support partial physical addressing modes on a virtual machine. An example method disclosed herein identifies a change of a first translation mode to a second translation mode on a host hardware platform, the host hardware platform including a processor, the processor further including region registers; identifies an address as cacheable or non-cacheable; saves contents of the region registers for the first translation mode to processor memory; updates content of the region registers corresponding to the second translation mode; identifies a change of the second translation mode to the first translation mode; and populates the region registers with the contents of the saved region registers corresponding to the first translation mode.

Abstract: A computing environment and techniques are provided for processing work out of order in one or more processing contexts. The processing techniques include: determining, for a processing context having an associated stack of waiting resources, whether a last-in listed resource in the stack of waiting resource is available, and if so, resuming processing of a suspended unit of work requiring the last-in listed resource; and determining, otherwise, whether an out of order execution unit of work is available for processing in the context, and if so, processing the out of order execution unit of work while the suspended unit of work awaits the last-in listed resource. Out of order execution units of work can be processed in order from a regular unit of work queue, or out of order from an out of order unit of work queue of a processing context.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: In process control based on partition setting which is a process corresponding to a plurality of operating systems (OSs), a configuration is implemented in which an interrupt request can be processed efficiently. In process control for switching processes which are based on the plurality of OSs, it is configured to set an interrupt processing partition as an interrupt processing execution period corresponding to an interrupt processing request so as to coincide with a pre-set partition switching timing. Further, a processing schedule is set, taking a maximum allowable delay time, a minimum allowable delay time into account. As a result of the present configuration, an increment in the number of partition switching processes can be kept to 1, and thus efficient data processing becomes possible.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: According to one embodiment, USB device virtualization can be improved by giving virtual machines (VMs) direct access to USB devices with a combined hardware and software solution. One aspect is directed to including providing a set of PCI configuration registers and operational registers for each VM, providing an interrupt request line for each VM, and using a new schedule traversal algorithm for multiple schedules, including a fairness algorithm that prevents starvation of any VM's bulk traffic.

Abstract: A process scheduling method includes executing a plurality of symmetric schedulers on respective processors of a multiprocessing system. Each scheduler periodically accesses a shared lock to obtain exclusive access to a shared scheduling data structure including (a) process information identifying the processes, and (b) scheduling information reflecting the executability and priorities of the processes. After obtaining the lock, each scheduler performs a scheduling routine including (a) utilizing the scheduling information and a scheduling algorithm to identify a next executable process, and (b) (1) activating the identified process to begin executing on the processor on which the scheduler is executing, and (2) updating the scheduling information to reflect the activation of the identified process. The scheduler then accesses the lock to relinquish exclusive access to the scheduling data structure.

Abstract: In a parallel computing environment comprising a network of SMP nodes each having at least one processor, a parallel-aware co-scheduling method and system for improving the performance and scalability of a dedicated parallel job having synchronizing collective operations. The method and system uses a global co-scheduler and an operating system kernel dispatcher adapted to coordinate interfering system and daemon activities on a node and across nodes to promote intra-node and inter-node overlap of said interfering system and daemon activities as well as intra-node and inter-node overlap of said synchronizing collective operations. In this manner, the impact of random short-lived interruptions, such as timer-decrement processing and periodic daemon activity, on synchronizing collective operations is minimized on large processor-count SPMD bulk-synchronous programming styles.

Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.

Abstract: Context switching between threads belonging to different user-side processes is a time consuming procedure because of the need to move a potentially large number of memory mappings around and the need to flush the data cache on hardware architectures which utilise a virtually tagged data cache. This invention allows the modification of page directory entries and the flushing of the data cache during a context switch to occur with pre-emption enabled; if a third process needs to run during a context switch, and this third process doesn't own or require any user memory modification of the page tables, this is now possible. By means of this invention, switches to kernel threads and threads in fixed user processes can occur much faster; these threads don't belong to processes that own any user memory and are the very ones that need to run with a lower guaranteed latency to ensure real-time performance.

Abstract: A method of deadlock detection is disclosed which adjusts the detection technique based on statistics maintained for tracking the number of actual deadlocks that are detected in a distributed system, and for which types of locks are most frequently involved in deadlocks. When deadlocks occur rarely, the deadlock detection may be tuned down, for example, by reducing a threshold value which determines timeouts for waiting lock requests. When it is determined that actual deadlocks are detected frequently, the processing time for deadlock detection may be reduced, for example, by using parallel forward or backward search operations and/or by according higher priority in deadlock detection processing to locks which are more likely to involve deadlocks.

Abstract: A method for switching between instruction contexts within a time interval in a multi-mode wireless broadband processing system. The method can include executing critical task operations that complete execution within a time interval, a critical task including a plurality of critical task operations, executing non-critical task operations that are able to cross a time interval boundary, a non-critical task including a plurality of non-critical task operations, and entering a sleep mode in which no critical task operations or non-critical task operations are executed, if the critical task operations and the non-critical task operations begun in the time interval have been completed before a following time interval begins.

Abstract: A system for scheduling tasks for execution includes a queue of tasks ordered by scheduled time for execution. A timer thread monitors status of tasks in the queue and selectively dispatches tasks. A guard thread monitors status of tasks in the queue and selectively creates timer threads. The guard thread is responsive to a next task in the queue becoming ready for execution while a first timer thread is still processing a prior task to create a new timer thread to dispatch the next task and mark the first timer thread for closure. Thereafter, the first timer thread closes responsive to the prior task completing.

Abstract: The invention relates to a device to be used with a scheduling method, and to a scheduling method, in particular a context scheduling method, comprising the steps of performing a scheduling for threads to be executed by a multithreaded processor, wherein the scheduling is performed as a function of index variables assigned to the threads. That thread whose index variable has the highest, or—in an alternative—the lowest value may be selected as the respective thread to be executed by the processor.

Abstract: Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.

Abstract: A method and apparatus are provided for thermal management of a multiprocessor computer system. The temperatures of the various processors within a multiprocessor system are monitored. When a processor is identified as overheated, a dummy process will be assigned to it, causing all other processes to be put on hold, thereby reducing the heat output of that processor. When the temperature of the processor lowers below another predetermined value, then the dummy process is terminated.

Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.

Abstract: An embodiment of a method of virtualizing a counter in a computer system comprises a first step and iterative performance of second through fifth steps. In the first step, a virtual machine monitor programs a hardware event counter with an initial count for a profiling event for a virtual machine. In the second step, the virtual machine monitor saves a suspension count and disables the hardware event counter upon suspending operation of the virtual machine. In the third step, the virtual machine monitor programs the hardware event counter with the suspension count upon resuming the operation of the virtual machine. Upon receiving an interrupt from the hardware event counter that provides notification of reaching the initial count, the virtual machine monitor performs the fourth and fifth steps. In the fourth step, the virtual machine monitor saves a sample that comprises an event identifier and a code-in-execution indicator.

Abstract: A method and apparatus are provided for operating a processor. The method comprising the steps of providing a single call stack for execution of a plurality of tasks that operate on the processor, parallelly operating the plurality of tasks and allowing a context switch from a first task to a second task of the plurality of tasks, but only when operation of the first task is blocked.

Abstract: The present invention provides a task selection assistance apparatus, and a task selection assistance method, which enable burdens on a user to be alleviated in selecting a task for solving a problem. A domain candidate determining portion 210 determines domain candidates to be presented to the user from among domains stored in a task model DB 102, and a domain candidate transmitting portion 201 transmits the domain candidates to a portable terminal 101. A user selected domain obtaining portion 203 obtains a domain, which has been selected by the user, from the portable terminal 101, and the task candidate determining portion 211 determines task candidates to be presented to the user from among tasks stored in the task model DB 102 based on the domain selected by the user.

Abstract: Presently disclosed are a method and apparatus for generating graphics in a protected manner by establishing a user graphics partition while in an executive context. Once the user context is established, an operating mode is switched to the user context and then executing a user graphics program while in the user context. The operating mode then reverts to the executive context when the user context expires.

Abstract: A system and method of improved task switching in a data processing system. First, a first-level cache memory casts out an invalidated page table entry and an associated first page directory base address to a second-level cache memory. Then, the second-level cache memory determines if a task switch has occurred. If a task switch has not occurred, first-level cache memory sends the invalidated page table entry to a current running task directory. If a task switch has occurred, first-level cache memory loads from the second-level cache directory a collection of page table entries related to a new task to enable improved task switching without requiring access to a page table stored in main memory to retrieve the collection of page table entries.

Abstract: Process migration method includes copying first process context indicative of first processing, transmitting process context to second computer, causing first computer to start generation of first execution record, causing second computer to receive process context, determining, from first execution record, whether first processing should be migrated, if it is determined that first processing should postpone being migrated, finishing generation of first execution record, starting generation of second execution record, transmitting first execution record to second computer, reproducing process context, and determining, from second execution record, whether first processing should be migrated, after reproducing of process context is finished in the second computer.

Abstract: A system and method for concentration and load-balancing of requests in a distributed computing environment. In accordance with an embodiment, a system and a method for reducing the number of connections in an Internet environment using one or a plurality of connection handlers which handle the connection from the client to the server, and a listener which determines which connection handler to use to handle the connection. Whereas prior solutions required a (n×m) number of connections to handle requests, the invention allows there to be only m connections which significantly reduces resource requirements and allows scalability.

Abstract: A timeout helper main thread is created for an outbound call associated with a container. The main thread creates a timeout helper worker thread. A local timer is started to detect a first timeout condition based on a first timeout interval. The worker thread initiates a client Object Request Broker (ORB) to detect a second timeout condition based on a second timeout interval. If the outbound call completes within the first timeout interval, a result object is returned from the main thread. Otherwise, the main thread throws a timeout exception. If the outbound call has not completed within the second timeout interval, the client ORB throws an exception to the worker thread and one or more resources associated with the outbound call are reclaimed. As an alternative to the client ORB, an HTTP client can detect the second timeout condition.

Abstract: Systems and methods are provided that determine the actual amount of time a processor consumes in executing a code portion. The actual execution time of a code portion may be accurately determined by taking into consideration context switches and/or overhead time corresponding to the code portion. Determining the actual execution time of a code portion may include recording context switches and time values that occur during the execution of the code portion. This information along with overhead measurements may be used to generate the actual execution time of a code portion, as will be described in more detail below. For example, the switched-out intervals resulting from the context switches and the overhead time associated with the time measurements may be subtracted from the elapsed time to produce the actual execution time of a code portion.

Abstract: A method, apparatus and program storage device for managing buffers during online reorganization. An adaptive buffer is provided having a dynamically adjustable boundary, the adaptive buffer processes log records and pointers associated with the log records during online reorganization of a database. Adaptive switching is provided between a first and a second task during the processing of data log records and index log records during the online reorganization of the database.