Abstract: A dispatcher stack is allocated to each of a plurality of processors sharing a run queue. Each processor, in process dispatch processing, saves in a switch-source process stack the context of a switch-source process (the process being run), saves in the dispatcher stack of each of the processors a dispatcher context, inserts the switch-source process into the run queue, removes a switch-destination process from the run queue, and, in addition, restores the context of the switch-destination process from the switch-destination process stack.

Abstract: A mechanism for asynchronous input/output (I/O) using second stack switching in kernel space is disclosed. A method of the invention includes receiving, by a kernel executing in a computing device, an input/output (I/O) request from an application thread executing using a first stack, allocating a second stack in kernel space of the computing device, switching execution of the thread to the second stack, and processing the I/O request synchronously using the second stack.

Abstract: One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that includes at least one set-synchronization instruction and at least one instruction that includes a synchronization command, and determining an active mask that indicates which threads in a plurality of threads are active and which threads in the plurality of threads are disabled. For each instruction included in the plurality of instructions, the instruction is transmitted to each of the active threads included in the plurality of threads. If the instruction is a set-synchronization instruction, then a synchronization token, the active mask and the synchronization point is each pushed onto a stack.

Abstract: A method and apparatus for providing a resource allocation policy in a network are disclosed. For example, the method constructs a queuing model for each application. The method defines a utility function for each application and for each transaction type of each application, and defines an overall utility in a system. The method performs an optimization to identify an optimal configuration that maximizes the overall utility for a given workload, and determines one or more adaptation policies for configuring the system in accordance with the optimal configuration.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: Techniques for managing a plurality of threads on a multi-threading processing core. Embodiments provide an instruction count threshold condition that determines how many countable instructions of a thread the multi-threading processing core will execute before context switching to another one of the plurality of threads. A first plurality of instructions for a first one of the plurality of threads is processed on the multi-threading processing core. Embodiments determine, for each of the first plurality of instructions, whether the instruction is a countable instruction, wherein at least one of the first plurality of instructions is not a countable instruction. A count of the countable instructions is maintained. Upon determining that the instruction count threshold condition is satisfied, based on the maintained count, embodiments context switch the multi-threading processing core to process a second plurality of instructions for a second one of the plurality of threads.

Abstract: Techniques are disclosed to identify concurrently used applications based on application state. Upon determining that usage of a plurality of applications, including a first state of a first application of the plurality of applications, satisfies a criterion for identifying concurrently used applications, the plurality of applications is designated as a first meta-application having a uniquely identifiable set of concurrently used applications. The first meta-application has an associated criterion for launching the first meta-application. Upon determining that the criterion for launching the first meta-application is satisfied, at least one of the plurality of applications is programmatically invoked.

Abstract: A system includes a context file to store multiple contexts corresponding to different power modes of an electronic system, and a domain control device to generate control signals based, at least in part, on a context from the context file. The electronic system is configured to transition to a power mode corresponding to the context responsive to the control signals.

Abstract: The present invention provides an efficient state management system for a complex ASIC, and applications thereof. In an embodiment, a computer-based system executes state-dependent processes. The computer-based system includes a command processor (CP) and a plurality of processing blocks. The CP receives commands in a command stream and manages a global state responsive to global context events in the command stream. The plurality of processing blocks receive the commands in the command stream and manage respective block states responsive to block context events in the command stream. Each respective processing block executes a process on data in a data stream based on the global state and the block state of the respective processing block.

Abstract: Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a Central Processing Unit (CPU) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the CPU effectiveness.

Abstract: In one embodiment, the present invention includes a method for determining a scaling factor between a frequency of a first processor and a frequency of a second processor after a guest software is migrated from first processor to the second processor, and executing the guest software on the second processor using a virtual counter based on a physical counter of the second processor and the scaling factor. Other embodiments are described and claimed.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: A processing resource apparatus comprises a reference processing module comprising a set of reference stateful elements and a target processing module comprising a set of target stateful elements. A scan chain having a first mode for supporting manufacture testing is also provided, the scan chain being arranged to couple the reference processing module to the target processing module. The scan chain also has a second mode capable of synchronizing the set of target stateful elements with the set of reference stateful elements in response to a synchronization signal.

Abstract: Time fidelity may be maintained for an instance of a virtual space placed in a background state. The background state may be a state in which user intervention with the instance of the virtual space is disallowed. In contrast, a foreground state may be a state in which user intervention with the instance of the virtual space is allowed. Individual timers may be associated with corresponding events configured to occur within the virtual space. An elapsed time while the instance of the virtual space is in a background state may be determined. Individual timers may be adjusted based on the elapsed time responsive to the instance of the virtual space resuming from the background state to the foreground state in order to maintain time fidelity.

Abstract: A method and system include a backend mobile development framework. The framework includes a library having a plurality of apps for mobile devices, the apps divided into groups of related apps. A communications module is operable to communicate with multiple mobile devices. A data store provides interconnectivity between apps in each group such that a first app has content information shared with a second app.

Abstract: A method for context switching of multiple offload processors is disclosed. The method can include receiving network packets for processing through a memory bus connected socket, organizing the network packets into multiple sessions for processing, suspending processing of at least one session by reading a cache state of at least one of the offload processor into a context memory by operation of a scheduling circuit, with virtual memory locations and physical cache locations being aligned, and subsequently directing transfer of the cache state to at least one of the offload processors for processing by operation of the scheduling circuit.

Abstract: The method includes identifying a first executing process using a second executing process. The first executing process may include a file descriptor and the first executing process may be independent of the second executing process. The method includes disassociating the file descriptor from a first data stream using the second executing process without involvement of the first executing process. The method includes associating the file descriptor with a second data stream using the second executing process without involvement of the first executing process in response to disassociating the file descriptor from the first data stream.

Abstract: A system and method for efficient automatic scheduling of the execution of work units between multiple heterogeneous processor cores. A processing node includes a first processor core with a general-purpose micro-architecture and a second processor core with a single instruction multiple data micro-architecture. A computer program comprises one or more compute kernels, or function calls. A compiler computes pre-runtime information of the given function call. A runtime scheduler produces one or more work units by matching each of the one or more kernels with an associated record of data. The scheduler assigns work units either to the first or to the second processor core based at least in part on the computed pre-runtime information. In addition, the scheduler is able to change an original assignment for a waiting work unit based on dynamic runtime behavior of other work units corresponding to a same kernel as the waiting work unit.

Abstract: A method dynamically frees computer resources in a multitasking and windowing environment by activating a GUI widget to initiate pausing of an application, pausing CPU processing of the application code, maintaining data of the application in main memory, storing state information for the application code and a process of the application in mass storage, removing the application code from main memory to mass storage, when another application requires additional memory, activating another GUI widget to resume running of the application, restoring the state information for the code and the process to main memory before the application resumes running, and resuming the CPU processing of the application.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.

Abstract: A processor is described having logic circuitry of a general purpose CPU core to save multiple copies of context of a thread of the general purpose CPU core to prepare multiple micro-threads of a multi-threaded accelerator for execution to accelerate operations for the thread through parallel execution of the micro-threads.

Abstract: A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: Systems, apparatus, and method of monitoring synchronization in a distributed cache are described. In an exemplary embodiment, a first and second processing core process a first and second thread respectively. A first and second distributed cache slices store data for either or both of the first and second processing cores. A first and second core interface co-located with the first and second processing cores respectively maintain a finite state machine (FSM) to be executed in response to receiving a request from a thread of its co-located processing core to monitor a cache line in the distributed cache.

Abstract: System and methods providing secure workspace sessions is described. In one embodiment a method for providing multiple workspace sessions for securely running applications comprises steps of: initiating a first workspace session on an existing operating system instance running on the computer system, the first workspace session having a first set of privileges for running applications under that session; while the first workspace session remains active, initiating a second workspace session on the existing operating system instance running on the computer system, the second workspace session having a second set of privileges for running applications under the second workplace session; and securing the second workspace session so that applications running under the second workplace session are protected from applications running outside the second workspace session.

Abstract: Systems and methods are disclosed to schedule jobs in a cloud computing infrastructure by receiving in a first queue jobs with deadlines or constraints specified in a hard service level agreement (SLA); receiving in a second queue jobs with a penalty cost metric specified in a soft SLA; and minimizing both constraint violation count and total penalty cost in the cloud computing infrastructure by identifying jobs with deadlines in the first queue and delaying jobs in the first queue within a predetermined slack range in favor of jobs in the second queue to improve the penalty cost metric.

Abstract: A system and method for providing dynamic device virtualization is herein disclosed. According to one embodiment, the computer-implemented method includes providing a device virtualization via context switching between a guest user process and a host. The guest user process has an address space comprising at least a guest kernel and a host kernel. The guest user process is capable of making a first direct call into the host via the guest kernel of the address space. The host is capable of making a second direct call to the guest user process.

Abstract: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Abstract: Techniques for implicit co scheduling of CPUs to improve corun performance of scheduled contexts are described. One technique minimizes skew by implementing corun migrations, and another technique minimizes skew by implementing a corun bonus mechanism. Skew between schedulable contexts may be calculated based on guest progress, where guest progress represents time spent executing guest operating system and guest application code. A non-linear skew catch-up algorithm is described that adjusts the progress of a context when the progress falls far behind its sibling contexts.

Abstract: Methods, systems, and computer readable storage media embodiments allow for low overhead context switching of threads. In embodiments, applications, such as, but not limited to, iterative data-parallel applications, substantially reduce the overhead of context switching by adding a user or higher-level program configurability of a state to be saved upon preempting of a executing thread. These methods, systems, and computer readable storage media include aspects of running a group of threads on a processor, saving state information by respective threads in the group in response to a signal from a scheduler, and pre-empting running of the group after the saving of the state information.

Abstract: A disclosed parallel computer includes plural nodes, and one node of the plural nodes collects information concerning a state of progress of barrier synchronization from each of the plural nodes, upon detecting that execution of a program for a job is stopped in each of the plural of nodes. And, the one node of the plural nodes in the parallel computer determines a restart position of the program for the job in the one node, based on a stop position of the program for the job in the one node and the information collected from each of the plural nodes.

Abstract: Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation.

Abstract: An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d1) and idle consumed cycles (d3).

Abstract: A method for sharing a common computing system among multiple users is disclosed. A user can perform a login process during which an input data, such as a user name or a password can be entered by the user to access a session. The user name and/or the password are then serialized into an object or a set of objects. If the serialized object or objects are authentic, a session is created and the session properties of the session are defined. Any applications that are subsequently executed during the session remain active after the session is switched out.

Abstract: One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger set of pending threads that is also maintained by the two-leveler scheduler. Pending threads are promoted to strands and strands are demoted to pending threads based on latency characteristics. The two-level scheduler selects strands for execution based on strand state. The longer latency of the pending threads is hidden by selecting strands for execution. When the latency for a pending thread is expired, the pending thread may be promoted to a strand and begin (or resume) execution. When a strand encounters a latency event, the strand may be demoted to a pending thread while the latency is incurred.

Abstract: A processor includes a VM trap logic and a buffering logic. The VM trap logic determines whether or not an instruction acquired from a VM (Virtual Machine) satisfies a predetermined VM trap condition. The buffering logic determines whether or not the instruction acquired from the VM satisfies a predetermined buffering condition.

Abstract: A method for handling a system call in an operating system executed by a processor is disclosed. The message comprises steps of receiving the system call to a called process from a calling process; if the system call is a synchronous system call and if a priority of the calling process is higher than a priority of the called process, increasing the priority of the called process to be at least the priority of the calling process; and switching context to the called process.

Abstract: A data processing system comprising an operating system for supporting processes, such that the process are associated with one or more resources and the operating system being arranged to police the accessing by processes of resources so as to inhibit a process from accessing resources with which it is not associated. Part of this system is an interface for interfacing between each process and the operating system and a memory for storing state information for at least one process. The interface may be arranged to analyze instructions from the processes to the operating system, and upon detecting an instruction to re-initialize a process cause state information corresponding to that pre-existing state information to be stored in the memory as state information for the re-initialized process and to be associated with the resource.

Abstract: For operating two operating systems of a computer without performance loss, the invention proposes a method in which a secondary operating system driver (SOS driver) of the primary operating system is loaded for loading and controlling the secondary operating system and which subsequently loads the secondary operating system. The invention also provides a device with a corresponding secondary operating system driver (SOS driver) of the primary operating system for driving a board support package.

Abstract: A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs.

Abstract: A microprocessor architecture having extendible logic. One or more customized applications are available to the instruction pipeline. The customizable applications may include software, extension logic instruction or register, dynamically configurable hardware logic, or combinations of these. In order to enable the operating system to interface with the customized extension applications, at least one software extension is provided to the operating system. When a specific extension is requested a software exception is generated by the OS. In response to the exception, the least one software extension is called to handle context switch and dynamic configuration of the extendible logic of the microprocessor.

Abstract: An image forming apparatus including a drawing unit which generates pixel data based on print data and an image processing unit which performs image processing for the pixel data, the apparatus comprises: a determination unit configured to determine, while the drawing unit and the image processing unit are performing processing, whether the image processing unit as an output destination of pixel data generated is configured to be stopped when receiving a stop instruction for the processing from a control unit; and a transmission unit configured to transmit pixel data of predetermined color values to the image processing unit for the number of pixels which have not been processed in processing of generating the pixel data when the determination unit determines that the image processing unit is not configured to be stopped, wherein the image processing unit performs image processing by using pixel data of the predetermined color values transmitted.

Abstract: A method for managing data in a collaborative service-oriented workshop, which is adapted to treat objects associated with data representative of real or process data, is provided to share data and resources in an architecture of a workspace. The architecture is adapted to design complex objects and manipulate information technology objects that represent data, which may be representative of a real object or a process based on metadata representing characteristic data. The metadata includes a generic part that is common to all data, a specific part that is inherent to the type of data, and links to other objects. The links make it possible to establish, at a later time, the traceability of the data, or in other words the traceability between the different data produced or used during execution of processes.

Abstract: For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and to enter a mode in which the first processor core is powered off. The second processor core is to save a state of the second processor core and to enter a mode in which the second processor core is powered off. The cache memory is to be powered when the first processor core is powered off. The first processor core is to restore the saved state of the first processor core in response to the first processor core transitioning to a mode in which the first processor core is powered. The second processor core is to restore the saved state of the second processor core in response to the second processor core transitioning to a mode in which the second processor core is powered. Other embodiments are also disclosed.

Abstract: A system and method provides a high level of system functionality in a multimedia console through the use of system applications, while reducing any corresponding lack of control that multimedia applications will have while running on the console. A predetermined amount of hardware resources of the multimedia console is reserved. The system application is executed substantially using the predetermined amount of reserved hardware resources and the multimedia application is executed substantially within the remaining unreserved hardware resources.

Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads is accomplished by creating a first queue node for a first thread, the first queue node representing a request by the first thread to access the critical section; setting at least one pointer within a queue to point to the first queue node, the queue representing at least one thread desiring access to the critical section; waiting until a condition is met, the condition comprising the first queue node having no preceding write requests as indicated by at least one predecessor queue node on the queue; permitting the first thread to enter the critical section in response to the condition being met; and causing the first thread to release a spin lock, the spin lock acquired by a second thread of the plurality of processing threads.

Abstract: An apparatus for dynamically redirecting a file descriptor includes an identification module, a disassociation module, and an association module. The identification module identifies a first executing process using a second executing process. The first executing process may include a file descriptor and the first executing process may be independent of the second executing process. The disassociation module disassociates the file descriptor from a first data stream using the second executing process without involvement of the first executing process. The association module associates the file descriptor with a second data stream using the second executing process without involvement of the first executing process in response to the disassociation module disassociating the file descriptor from the first data stream.

Abstract: A system includes a detection unit configured to detect unauthorized access to one or more information processing apparatuses that are virtually implemented by virtual machines executed by a computer; an authorized network configured to transfer authorized access to the one or more information processing apparatuses from an external network; a honeypot network configured to transfer unauthorized access to the information processing apparatuses from the external network; and a control unit configured to connect the information processing apparatuses for which no unauthorized access has been detected to the authorized network, and connect the information processing apparatuses for which unauthorized access has been detected to the honeypot network; wherein the control unit shifts, in response to detecting unauthorized access by the detection unit, the corresponding information processing apparatus into a decoy mode in which the detected unauthorized access is disconnected from a normal operation.

Abstract: Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached.