Abstract: A processor includes a first translation look-aside buffer to support a guest operating mode. A second translation look-aside buffer supports a root operating mode. Hardware resources support the guest operating mode as controlled by guest mode control registers defining guest context. The guest context is used by the hardware resources to access the first translation look-aside buffer to translate a guest virtual address to a guest physical address. The hardware resources access the second translation look-aside buffer to translate the guest physical address to a physical address.

Abstract: A method and system providing switching between a plurality of installed programs in a computer system. Embodiments include a jump function comprising the steps: (1) determining a jump program that is to be the next program to be run, possibly from a plurality of possible choices; (2) creating input data for the jump program based on data in the current program; (3) storing the program state of the currently running program into a context packet and saving the context packet to memory; (4) releasing temporary memory that is used by the program, so as to allow other programs to use the memory; (5) calling the jump program with the created input data as input and terminating the currently running program.

Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads is accomplished by creating a first queue node for a first thread, the first queue node representing a request by the first thread to access the critical section; setting at least one pointer within a queue to point to the first queue node, the queue representing at least one thread desiring access to the critical section; waiting until a condition is met, the condition comprising the first queue node having no preceding write requests as indicated by at least one predecessor queue node on the queue; permitting the first thread to enter the critical section in response to the condition being met; and causing the first thread to release a spin lock, the spin lock acquired by a second thread of the plurality of processing threads.

Abstract: A network on chip (NOC) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.

Abstract: A virtual core management system including a physical core and a first virtual core including a collection of logical states associated with execution of a first program. The first virtual core is mapped to the physical core. The virtual core management system further includes a second virtual core including a collection of logical states associated with execution of a second program, and a virtual core management component configured to unmap the first virtual core from the physical core and map the second virtual core to the physical core in response to the virtual core management component detecting that the physical core is idle.

Abstract: A method and system for providing access to a shared resource utilizing selective locking are disclosed. According to one embodiment, a method is provided comprising receiving a request to perform a resource access operation on a shared resource, invoking a first routine to perform the resource access operation, detecting a data processing system exception generated in response to invoking the first routine, and invoking a second routine to perform the resource access operation in response to such detecting. In the described embodiment, the first routine comprises a dereference instruction to dereference a pointer to memory associated with the shared resource, the second routine comprises a lock acquisition instruction to acquire a global lock associated with the shared resource prior to a performance of the resource access operation and a lock release instruction to release the global lock once resource access operation has been performed.

Abstract: A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.

Abstract: According to an embodiment, a method of sampling hardware events in a computer system comprises a first step and iterative performance of second and third steps. In the first step, an initiator virtual machine identifies a profiling event and a count to a virtual machine monitor. The virtual machine monitor iteratively performs the second and third steps. In the second step, the virtual machine monitor programs a hardware event counter with the count for the profiling event. In the third step, upon receiving an interrupt from the hardware event counter, the virtual machine monitor saves a sample that comprises a code-in-execution identifier.

Abstract: A process for maintaining synchronization of processors that are executing a same plurality of applications in parallel includes interrupting a current task between processing two successive instructions of an application being processed when an interrupt request occurs to process another application. An intermediate state reached by the current task is saved when the interrupt request occurs, and a counter for each of the processors indicating a number of instructions processed by each of the processors is maintained. A processor is caused to issue a synchronization confirmation in response to a comparison result that the numbers of instructions processed are identical. The processor is caused to enter a wait state when its number of processed-instructions is the largest among the processors or to execute a procedure for processing the instructions until its processed-instruction counter reaches the largest number.

Abstract: An electronic apparatus includes program memory means, application program execution means, and attitude detection means. The program memory means stores a plurality of application programs. The application program execution means executes an application program read out from the program memory means. The attitude detection means detects the attitude of the electronic apparatus. The application program execution means performs an application switching process to execute a second application program when detection data obtained by attitude detection performed by the attitude detection means during execution of a first application program or data obtained by computing the detection data changes across a predetermined threshold.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: In a signal processing system, a programming system and method for a video network are provided. An event may trigger an RDMA controller to execute current instructions in a register update list. The triggering event may be a start-of-field signal from a live source or an end-of-frame signal. The current instructions may be used to modify the mode of operation of at least one of the network elements in the video network. The modification to the mode of operation may depend on whether the current video field is top field originated or bottom field originated. An interrupt may be used to initiate an interrupt handler that generates at least one new instruction and that updates the new instructions in the register update list. When a trigger occurs prior to an update of the register update list, the RDMA controller may execute the current instructions in the register update list.

Abstract: A method, apparatus and program storage device for providing an anchor pointer in an operating system context structure for improving the efficiency of accessing thread specific data is provided. A kernel thread context structure is maintained in memory. A thread accesses a pointer memory in the kernel thread context structure and sets a value within the pointer memory that addresses data specific to the thread.

Abstract: In one embodiment, the present invention includes a method for receiving a signal in a filter register of a performance monitor from an execution unit to enable a field of the filter register associated with a first thread when a filter enable instruction is executed during execution of code of the first thread, receiving a thread identifier and event information in the performance monitor from the execution unit, and determining if the thread that corresponds to the received thread identifier is enabled in the filter register and if so, storing the event information in a first counter of the performance monitor. Other embodiments are described and claimed.

Abstract: A network processor of an embodiment includes a packet classification engine, a processing pipeline, and a controller. The packet classification engine allows for classifying each of a plurality of packets according to packet type. The processing pipeline has a plurality of stages for processing each of the plurality of packets in a pipelined manner, where each stage includes one or more processors. The controller allows for providing the plurality of packets to the processing pipeline in an order that is based at least partially on: (i) packet types of the plurality of packets as classified by the packet classification engine and (ii) estimates of processing times for processing packets of the packet types at each stage of the plurality of stages of the processing pipeline. A method in a network processor allows for prefetching instructions into a cache for processing a packet based on a packet type of the packet.

Abstract: A method to handle peak database workloads is disclosed. In one form of the disclosure, the method can include requesting resources, receiving virtual-machine information in response to requesting, and allocating first and second portions of a workload according to the virtual-machine information. The method can also include processing the first portion on a virtual machine to generate a first result, processing the second portion on a cloned virtual machine to generate a second result, and aggregating the first and the second results to form a response.

Abstract: Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. A set of coscheduled contexts is monitored. If a skew metric associated with a first context of the coscheduled contexts fails to satisfy a condition, then a subset of the coscheduled contexts is descheduled although the first context remains scheduled.

Abstract: A method, apparatus and program storage device for performing a return/rollback process for RCU-protected data structures is provided that includes checking a user-level state of a preempted thread having a RCU read-side critical section, and executing the critical section of the thread after preemption when the user-level state of the thread indicates execution, otherwise returning to a point of preemption, resuming execution of the thread and disabling checking the user-level state when the user-level state of the thread indicates return.

Abstract: Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. A set of coscheduled contexts, including at least a first context and a second context, are monitored. The first and second contexts are alternately scheduled and descheduled so that both the first context and the second context are not concurrently scheduled.

Abstract: A method and system providing switching between a plurality of installed programs in a computer system. Embodiments include a jump function comprising the steps: (1) determining a jump program that is to be the next program to be run, possibly from a plurality of possible choices; (2) creating input data for the jump program based on data in the current program; (3) storing the program state of the currently running program into a context packet and saving the context packet to memory; (4) releasing temporary memory that is used by the program, so as to allow other programs to use the memory; (5) calling the jump program with the created input data as input and terminating the currently running program.

Abstract: A system is provided for disseminating resource allocation information from system resources to state-information observers comprising resource users and typically also at least one system resource manager. Each resource maintains state information about its identity and its allocation to one or more resource users. Each resource provides this information to a state-dissemination arrangement which disseminates it to each state-information observer. Each resource user uses the state information it receives from the state-dissemination arrangement to ascertain the resources allocated to it. Similarly, a system resource manager, when present, uses the state information it receives from the state-dissemination arrangement to ascertain the allocation of those resources that are of interest to the manager. A resource, resource user and resource manager for use in such a system are also provided.

Abstract: Backup systems and methods are disclosed for a virtual computing environment. Certain examples include a system having a backup management server that communicates with a host server having at least one virtual machine. The management server coordinates with the host server to perform backup copies of entire virtual machine disks from outside the guest operating system of the virtual machine. In certain examples, such backup systems further utilize a volume shadow copy service executing on the host server to quiesce virtual machine applications to put data in a consistent state to be backed up. The backup system then utilizes hypervisor snapshot capabilities of the host server to record intended changes to the virtual machine disk files while such files are being copied (e.g., backed up) by the host server. Such recorded changes can be later committed to the virtual machine disk files once the backup operation has completed.

Abstract: A connection management system can achieve scalability for domain computing among a plurality of domains. Each of the plurality of domains comprises a collection of machines and resources that are administrated as a unit. A connection concentrator can connect, and support communication between, a plurality of processes in a first domain and a plurality of processes in a second domain. The connection concentrator uses one connection to communicate with any one of the plurality of processes in the first domain, and can communicate with each one of the plurality of processes in the second domain.

Abstract: An operating system for a computing device includes a scheduler incorporating an algorithm for ordering the running of threads of execution having different priorities. The operating system is also arranged to provide a list of threads which are scheduled to run on the device, ordered by priority. At least one locking mechanism for docking access to a resource of the device from all threads except for a thread that holds the locking mechanism is also provided, and the operating system arranges for a scheduled thread which is docked from running because the resource it requires is locked to cause the thread which holds the locking mechanism to run.

Abstract: An aspect of the present invention improves the accuracy of measuring processor utilization of multi-threaded cores by providing a calibration facility that derives utilization in the context of the overall dynamic operating state of the core by assigning weights to idle threads and assigning weights to run threads, depending on the status of the core. From previous chip designs it has been established in a Simultaneous Multi Thread (SMT) core that not all idle cycles in a hardware thread can be equally converted into useful work. Competition for core resources reduces the conversion efficiency of one thread's idle cycles when any other thread is running on the same core.

Abstract: In one embodiment, a load balancing system may include a first physical device that provides a resource. The first physical device may have a first virtual device running actively thereon. The first virtual device may have the resource allocated to it on the physical device. The first physical device may also have a virtual server load balancer running actively thereon. The server load balancer may be adapted to balance a workload associated with the resource between the first virtual device and a second virtual device. The second virtual device may be running in active mode on a second physical device, and in standby mode on the first physical device. The first virtual device may be in standby mode on the second physical device.

Abstract: A computer implemented method, apparatus, and computer program product for dynamically loading a module into an application address space. In response to receiving a checkpoint signal by a plurality of threads associated with an application running in a software partition, the plurality of threads rendezvous to a point outside an application text associated with the application. Rendezvousing the plurality of threads suspends execution of application text by the plurality of threads. The application text is moved out of an application address space for the application to form an available application address space. The available application address space is an address space that was occupied by the application text. A software module is moved into the available application address space.

Abstract: Guiding OS thread scheduling in multi-core and/or multi-threaded microprocessors by: determining, for each thread among the active threads, the power consumed by each instruction type associated with an instruction executed by the thread during the last context switch interval; determining for each thread among the active threads, the power consumption expected for each instruction type associated with an instruction scheduled by said thread during the next context switch interval; generating at least one combination of N threads among the active threads (M), and for each generated combination determining if the combination of N threads satisfies a main condition related to the power consumption per instruction type expected for each thread of the thread combination during the next context switch interval and to the thread power consumption per instruction type determined for each thread of the thread combination during the last context switch interval; and selecting a combination of N threads.

Abstract: A method for designing a time-sliced and multi-threaded architecture comprises the steps of conducting a thorough analysis of a range of applications and building a specific processor to accommodate the range of applications. In one embodiment, the thorough analysis includes extracting real time aspects from each application, determining optimal granularity in the architecture based on the real time aspects of each application, and adjusting the optimal granularity based on acceptable context switching overhead.

Abstract: A method and an apparatus for storing a copy of memory-mapped I/O (MMIO) register are provided for enhancing data processing efficiency. In a structure in which data processing is executed by associating a plurality of logical processors with a physical processor by timing sharing, a host OS stores copy information, namely, shadow, of the MMIO register corresponding to a logical processor in memory both in an active state where a physical processor is allocated to a logical processor corresponding to a guest OS and in an inactive state where no physical processor is allocated to a logical processor. This structure enables a guest OS to gain faster access to the MMIO register through the shadow by memory access, instead of a direct access to the MMIO register, so as to achieve efficient data processing.

Abstract: Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding performance (e.g., execution performance and/or power consumption performance) of a plurality of processor cores of a processor is stored (and tracked) in counters and/or tables. Logic in the processor determines which processor core should execute an application based on the stored information. Other embodiments are also claimed and disclosed.

Abstract: One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger set of pending threads that is also maintained by the two-leveler scheduler. Pending threads are promoted to strands and strands are demoted to pending threads based on latency characteristics. The two-level scheduler selects strands for execution based on strand state. The longer latency of the pending threads is hidden by selecting strands for execution. When the latency for a pending thread is expired, the pending thread may be promoted to a strand and begin (or resume) execution. When a strand encounters a latency event, the strand may be demoted to a pending thread while the latency is incurred.

Abstract: A scalable locking system is described herein that allows processors to access shared data with reduced cache contention to increase parallelism and scalability. The system provides a reader/writer lock implementation that uses randomization and spends extra space to spread possible contention over multiple cache lines. The system avoids updates to a single shared location in acquiring/releasing a read lock by spreading the lock count over multiple sub-counts in multiple cache lines, and hashing thread identifiers to those cache lines. Carefully crafted invariants allow the use of partially lock-free code in the common path of acquisition and release of a read lock. A careful protocol allows the system to reuse space allocated for a read lock for subsequent locking to avoid frequent reallocating of read lock data structures. The system also provides fairness for write-locking threads and uses object pooling techniques to make reduce costs associated with the lock data structures.

Abstract: To avoid extensive time during which servicing of clients' requests is stopped for updating a piece of software or a data structure, various embodiments of the invention update an instance of the piece of software or an instance of the data structure instead of updating the original piece of software or the data structure. This allows the original piece of software or the data structure to service clients' requests without interruption. The updated instance begins to service clients' requests without losing context while the original piece of software or the data structure is terminated from further operation.

Abstract: A information processing apparatus having a processor is controlled to execute a procedure of reading from the memory attribute information indicating a usage frequency of a register used by a process to be executed as a next process by the processor when the processor switches a process currently being executed, saving a value of the register used by the next process to be executed by the processor to the memory when the usage frequency of the register indicated by the attribute information is larger than a certain frequency, reading from the memory owner information indicating a process using the register to be used by the next process when the usage frequency of the register indicated by the attribute information is larger than the certain frequency, and restoring a register value saved in the memory to the register when the owner information indicates a process other than the next process.

Abstract: A system, method and medium for reducing the number of system calls from an application program to an operating system kernel. In an embodiment, a method includes the steps of creating a list of requests issued by an application program, associating an indicia with the list indicating whether the list contains a request, querying the indicia to determine if the list contains a request, and adding a new application program request to the list when the indicia indicates that the list includes a request.

Abstract: A dynamic scheduling system is provided that comprises a processor, a polling task, a work task, and a scheduler assistant task. The polling task is configured for execution by the processor, wherein the polling task executes during a first CPU time window and sleeps during a second CPU time window. The work task is configured for an execution during the second CPU time window. The scheduler assistant (SA) task has an execution state to indicate to the polling task a status of the execution of the work task to the polling task. The SA task is configured to run if the work task runs to completion within the second CPU time window.

Abstract: An apparatus initiates, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be prefetched on behalf of that thread so that when execution of the thread is resumed, more of the working state for the thread is likely to be cached, or at least in the process of being retrieved into cache memory, thus reducing cache-related performance penalties associated with context switching.

Abstract: A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.

Abstract: A sleep function capable of putting a fixed high-priority thread to sleep within a time-window is disclosed. After a sleep request has been made by a fixed high-priority thread via the sleep function, a determination is made whether or not the fixed high-priority thread is awoken before a requested sleep duration under the sleep request. If the fixed high-priority thread is awoken before the requested sleep duration, the number of tasks for the fixed high-priority thread to perform is increased in order to delay the start sleep time of the fixed high-priority thread from a point within a first time-window in which the sleep request was made to an end boundary of the first time-window.

Abstract: A mobile telecommunication handset capable of implementing multitasking and a method for implementing multitasking in a mobile telecommunication are provided that makes it possible to implement multitasking even if sufficient memory and resources are not available. The mobile telecommunication handset includes a keypad having multitasking-specific function keys, a memory storing a task to run in a multitasking mode and task information related to the multitasking mode, a control unit controlling functions to implement a current task based on the task information, and a display unit displaying on-screen information related to multitasking in a multi tasking mode.

Abstract: Embodiments of the invention provide techniques for performing timeout waits of process threads. Generally, a thread requesting access to locked resource sends a timeout request to a timeout handler process, and then goes to sleep. The timeout request is received by a receiving thread of the timeout handler process. The receiving thread may insert the timeout request into a minimum heap of timeout requests, and may determine whether the inserted request is due earlier than any of the existing timeout requests. If so, the receiving thread may interrupt a timing thread of the timeout handler process. The timing thread may then wait until reaching the requested timeout, and then send a wakeup message to the sleeping thread.

Abstract: A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.

Abstract: A system to increase the security of the state of interrupted applications may include a computer processor to process software running in a plurality of runtime environments. The system may also include an interrupt stack per runtime environment to assist in how the computer processor switches from one subroutine to another in the same environment and from one runtime environment to any of the other runtime environments. The system may further include a plurality of hardware-managed areas to store processor state information and to assist in how the computer processor switches from one runtime environment to any of the other runtime environments.

Abstract: Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. A set of coscheduled contexts is monitored. If a skew metric associated with any one of the coscheduled contexts fails to satisfy a condition, then all coscheduled contexts in the set of coscheduled contexts not already descheduled are descheduled. After the contexts are descheduled, a subset of the set of coscheduled contexts is scheduled before the remainder of the set of coscheduled contexts.

Abstract: Disclosed are a method, information processing system, and computer readable medium for resource recovery. The method comprises associating at least one bit with at least one block of memory. The bit denotes a borrow status for the block of memory. The bit is set for resource recovery. A resource recovery event is detected and in response to the bit being enabled for resource recovery, the block of memory is borrowed for a given duration of time. The block is borrowed to temporarily store information associated with the resource recovery there into until the information is written to persistent storage.

Abstract: A microcomputer system includes a CPU, a memory, and a runaway detector. The CPU includes a controller for outputting a task information signal. The task information signal is activated, if the CPU performs the most important task at the present time. A program for the most important task is stored in the memory. The runaway detector includes an address register and a program area checker. The address register stores start and end addresses of the program area. The program area checker determines whether an execution address of the CPU is within the program area by comparing the execution address with each of the start and end addresses. The runaway detector detects a task runaway in the event of conflict between the task information signal and a result of a determination of the program area checker.

Abstract: Implementing fair scalable reader writer mutual exclusion for access to a critical section by a plurality of processing threads in a processing system is accomplished by creating a first queue node for a first thread on the first thread's stack, the queue node representing a request by the first thread to access the critical section; adding the first queue node to a queue pointed to by a single word reader writer mutex for the critical section, the queue representing a list of threads desiring access to the critical section, each queue node in the queue being on a stack of a thread of the plurality of processing threads; waiting until the first queue node has no preceding write requests as indicated by predecessor queue nodes on the queue; entering the critical section by the first thread; exiting the critical section by the first thread; and removing the first queue node from the queue.

Abstract: The disclosure relates generally to techniques, methods and apparatus for controlling context switching at a central processing unit. Alternatively, methods and apparatus are provided for providing security to memory blocks. Alternatively, methods and apparatus are provided for enabling transactional processing using a multi-core device.

Abstract: Apparatus, system, and method including a local resource to transfer information between a first processing unit and a second processing unit; and a global resource to transfer information between said first processing unit and said second processing unit, and to transfer information between said first processing unit and a third processing unit if said local resource is full are described.