Abstract: A method for tagging cache entries to support context switching for virtual machines and for operating systems. The method includes, storing a plurality of entries within a cache of a CPU of a computer system, wherein each of the entries includes a context ID, handling a first portion of the entries as local entries when the respective context IDs indicate a local status, and handling a second portion of the entries as global entries when the respective context IDs indicate a global status.

Abstract: According to an embodiment, a computer program product includes a computer-readable medium including program, when executed by a computer, to have a plurality of modules run by the computer. The computer includes a memory having a shared area, which is an area accessible to only those modules which run cooperatively and storing therein execution module identifiers. Each of the modules includes a first operation configured to store, just prior to a switchover of operations to an other module that runs cooperatively, an identifier of the other module as the execution module identifier in the shared area; and a second operation configured to execute, when the execution module identifier stored in the shared area matches with an identifier of own module immediately after a switchover of operations from the other module, a function inside the own module.

Abstract: An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.

Abstract: A method is described that comprises suspending a currently executing thread at a periodic time interval, calculating a next time slot during which the currently executing thread is to resume execution, appending the suspended thread to a queue of threads scheduled for execution at the calculated time slot, and updating an index value of a pointer index to a next sequential non-empty time slot, where the pointer index references time slots within an array of time slots, and where each of the plurality of time slots corresponds to a timeslice during which CPU resources are allocated to a particular thread. The method further comprises removing any contents of the indexed non-empty time slot and appending the removed contents to an array of threads requesting immediate CPU resource allocation and activating the thread at the top of the array of threads requesting immediate CPU resource allocation as a currently running thread.

Abstract: The interrupt level storing unit (16) stores one or more interrupt levels indicating the priority of a generated interrupt and stores the interrupt level having the highest priority among the stored interrupt levels as a second interrupt mask level. The second interrupt type determination unit (13) sets an interrupt level corresponding to the interrupt type of a newly generated interrupt. The priority determination unit (14) notifies the interrupt to the virtual machine control unit (20) when the interrupt level of the newly generated interrupt is higher than the stored second interrupt mask level. As a result, the priority of the virtual machine can be determined according to the task priority and the switching of virtual machines can be adequately controlled even if the virtual machines cannot notify the task priority.

Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

Abstract: A microprocessor executes programs in a pipeline architecture that includes a task register management unit that switches a value of a task register to second register information that is used when a second task is executed after the execution of a first task is completed, if a switch instruction to the second task is issued when a plurality of units executes the first task, and a task manager that switches a value of a task identification information register to a second task identifier after the value is switched to the second register information, and grants each of the plurality of units permission to execute the second task.

Abstract: A multiprocessing transaction recovery manager, operable with a transactional application manager and a resource manager, comprises a threadsafety indicator for receiving and storing positive and non-positive threadsafety data of at least one transactional component managed by one of the transactional application manager and the resource manager; a commit protocol component for performing commit processing for the at least one transactional component; and a thread selector responsive to positive threadsafety data for selecting a single thread for the commit processing to be performed by the commit protocol component. The thread selector is further operable to select plural threads for the commit processing to be performed by the commit protocol component responsive to non-positive threadsafety data.

Abstract: Techniques are described for managing distributed execution of programs. In at least some situations, the techniques include decomposing or otherwise separating the execution of a program into multiple distinct execution jobs that may each be executed on a distinct computing node, such as in a parallel manner with each execution job using a distinct subset of input data for the program. In addition, the techniques may include temporarily terminating and later resuming execution of at least some execution jobs, such as by persistently storing an intermediate state of the partial execution of an execution job, and later retrieving and using the stored intermediate state to resume execution of the execution job from the intermediate state. Furthermore, the techniques may be used in conjunction with a distributed program execution service that executes multiple programs on behalf of multiple customers or other users of the service.

Abstract: Input/output (I/O) operation requests from pageable storage mode guests are interpreted without host intervention. In a pageable mode virtual environment, requests issued by pageable storage mode guests are processed by one or more processors of the environment absent intervention from one or more hosts of the environment. Processing of the requests includes manipulating, by at least one processor on behalf of the guests, buffer state information stored in host storage. The manipulating is performed via instructions initiated by the guests and processed by one or more of the processors.

Abstract: A para-virtualization method is provided. The method comprises implementing a virtual machine (VM) for guest software running on first host software. In response to a privileged instruction, the guest software causes a first VM exit. If the first host software is not running directly on hardware, the privileged instruction is managed without causing a second VM exit. Otherwise, the privileged instruction is managed normally.

Abstract: When a process sleep event, a process wake-up event, a process save event, and a process resume event occur in an IT system having a multiprocessor configuration, a tracer respectively generates sleep event data, wake-up event data, save event data, and resume event data and records them as trace data in a trace buffer. The analysis unit generates an analysis result by referring to the trace data to accumulate a number of times of execution of the process wake-up process and a first time as a time from the process save event to the process wake-up event or to the process resume event with respect to a plurality of processes to be executed. When a contention for a shared resource occurs, the process wake-up process is repeatedly executed among relevant processes. For this reason, based on the analysis result, a possibility can be presented that the shared resource contention occurs in the IT system.

Abstract: During runtime of a binary program file, streams of instructions are executed and memory references, generated by instrumentation applied to given ones of the instructions that refer to memory locations, are collected. A transformation is performed, based on the executed streams of instructions and the collected memory references, to obtain a table. The table lists memory events of interest for active data structures for each function in the program file. The transformation is performed to translate memory addresses for given ones of the instructions and given ones of the data structures into locations and variable names in a source file corresponding to the binary file. At least the memory events of interest are displayed, and the display is organized so as to correlate the memory events of interest with corresponding ones of the data structures.

Abstract: Methods, apparatus, and products are disclosed for thread selection during context switching on a plurality of compute nodes that includes: executing, by a compute node, an application using a plurality of threads of execution, including executing one or more of the threads of execution; selecting, by the compute node from a plurality of available threads of execution for the application, a next thread of execution in dependence upon power characteristics for each of the available threads; determining, by the compute node, whether criteria for a thread context switch are satisfied; and performing, by the compute node, the thread context switch if the criteria for a thread context switch are satisfied, including executing the next thread of execution.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: A method for preventing priority inversion in a processor system having an operating system operable in a plurality of contexts is provided. The method comprises: providing a plurality of context control registers with each context control register being associated with a corresponding one context for controlling execution of the context; providing a plurality of sets of hardware registers, each set corresponding to one context of the plurality of contexts; and utilizing the plurality of context control registers and said plurality of sets of hardware registers to prevent priority inversion.

Abstract: A method and a system execute operations, called jobs, via an APM model, in a MES system. The job execution is requested in an application defining an abstract Job class. The abstract Job class includes: an abstract method for job execution, called Execute, wherein a set of jobs to be executed is implemented, at engineering time, within the Execute method, when implementing a set of classes derived from the abstract Job class; a method for executing the job in asynchronous mode, called ExecuteAsync, the ExecuteAsync method runs the Execute method by following APM rules; and a method for executing the job in synchronous mode, called WaitForExecution, the WaitForExecution method runs the ExecuteAsync method waiting for its completion. At run time, by the application, requests the job execution in asynchronous mode by invoking directly the ExecuteAsync method or in synchronous mode by invoking the WaitForExecution method.

Abstract: Embodiments for performing cooperative user mode scheduling between user mode schedulable (UMS) threads and primary threads are disclosed. In accordance with one embodiment, an asynchronous procedure call (APC) is received on a kernel portion of a user mode schedulable (UMS) thread. The status of the UMS thread as it is being processed in a multi-processor environment is determined. Based on the determined status, the APC is processed on the UMS thread.

Abstract: In a data processing system including multiple logical partitions (LPARs), an application executes on a first logical partition (LPAR) of the multiple LPARs, where the application uses a first operation system stored in a first memory partition of a shared pool memory of the data processing system. A virtualization management component (a) initiates an update process that quiesces operations of the first LPAR, (b) pages in, via a virtual input/output server coupled to a first paging device, a first image of a second operating system from the first paging device to the shared pool memory; (c) changes one or more pointers associated with the application to point to one or more portions of the second operating system, such that the application uses the second operating system, when resumed; and (b) resumes execution the application.

Abstract: A computer-implemented method for a computerized system having at least a first processor and a second processor, where each of the processors are operatively interconnected to a memory storing a set of data to be processed by a processor. The method includes monitoring data accessed by the first processor while executing, and if the second processor is at a shorter distance than the first processor from the monitored data, instructing to interrupt execution at the first processor and resume the execution at the second processor.

Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

Abstract: A computer-implemented method for lock-free use of a non-preemptive system resource by a preemptive thread, which may be interrupted. The method comprises registering a non-preemptive system resource and a first level reclaim handler for the non-preemptive system resource with the kernel of an operating system, registering a second level reclaim handler with the kernel, wherein the second level reclaim handler is included in an application program, and running the application program as a preemptive thread using the non-preemptive system resource. The first level reclaim handler is code that is a part of the implementation of the non-preemptive system resource in the kernel. The second level reclaim handler is code that is part of the application and is registered with the kernel before the application uses the non-preemptive system resource. The method enables a preemptive thread using a non-preemptive system resource to be preempted without crashing.

Abstract: In one embodiment, the instant invention includes a method of executing computer instructions having steps of: a) receiving, by a first computer, an instruction to perform a task b) executing each thread of a process, corresponding to the task, to time stop point when each thread requires data from a second computer system; maintaining a data structure that identifies a state information of each thread at the time stop point, and ii) whenever each thread reaches its own stop point, each thread gives up its execution in favor of an execution of another thread; c) requesting, from the second computer system, the data needed to continue the execution of the process; d) receiving, from the second computer system, the requested data; and e) resuming the execution of the process based on the state information for each thread stored in the data structure at the time stop point.

Abstract: Application states may be stored and retrieved using policies that define various contexts in which the application is used. The application states may define configurations or uses of the application, including connections to and interactions with other applications. Applications that are virtualized may have state that is defined within a usage context and multiple states or configurations may be stored and recalled based on the usage context. Policies may define the context and what parameters are to be saved, and may be applied when applications are operated in a virtualized manner.

Abstract: An approach that uses a handler to detect asynchronous lock line reservation lost events, and switching tasks based upon whether a condition is true or a mutex lock is acquired is presented. A synergistic processing unit (SPU) invokes a first thread and, during execution, the first thread requests external data that is shared with other threads or processors in the system. This shared data may be protected with a mutex lock or other shared memory synchronization constructs. When requested data is not available, the SPU switches to a second thread and monitors lock line reservation lost events in order to check when the data is available. When the data is available, the SPU switches back to the first thread and processes the first thread's request.

Abstract: Methods, apparatus, and products are disclosed for thread selection during context switching on a plurality of compute nodes that includes: executing, by a compute node, an application using a plurality of threads of execution, including executing one or more of the threads of execution; selecting, by the compute node from a plurality of available threads of execution for the application, a next thread of execution in dependence upon power characteristics for each of the available threads; determining, by the compute node, whether criteria for a thread context switch are satisfied; and performing, by the compute node, the thread context switch if the criteria for a thread context switch are satisfied, including executing the next thread of execution.

Abstract: A computer implemented method for handling events in a multi-core processing environment is provided. The method comprises handling an event by a second application running on a second core, in response to determining that the event is initiated by a first application running on a first core; and running a third application on the first core, while the first application is waiting for the event to be handled by the second application.

Abstract: A method, apparatus, and computer readable article of manufacture for executing a transaction by a processor apparatus that includes a plurality of hardware threads. The method includes the steps of: creating a main software thread for executing the transaction; creating a helper software thread for executing a barrier function; executing the main software thread and the helper software thread using the plurality of hardware threads; deciding whether the execution of the barrier function is required; executing the barrier function by the helper software thread; and returning to the main software thread. The step of executing the barrier function includes: stalling the main software thread; activating the helper software thread; and exiting the helper software thread in response to completion of the execution.

Abstract: One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

Abstract: A turn-oriented thread and/or process synchronization facility obtains a ticket value from a monotonically increasing ticket counter and waits until a memory location contains a value equal to the ticket value, yielding the processor between polls of the memory location only if a difference between the ticket value and the contents of the memory location exceeds a threshold value. Machine-readable media containing instructions to implement similar methods, and systems that can use the methods, are also described and claimed.

Abstract: An apparatus, system, and method for clipping graphics primitives are described. In one embodiment, a graphics processing apparatus includes a clipping unit that is configured to produce and issue ni initial outputs based on execution of a set of clipping operations, wherein ni represents the number of the initial outputs that are issued by the clipping unit prior to context switching, and the initial outputs partially define a clipped graphics primitive. The graphics processing apparatus also includes a control unit connected to the clipping unit. The control unit is configured to preserve an initial execution state of the clipping unit in response to an initial command for context switching, wherein the initial execution state is preserved based on ni.

Abstract: Techniques for allocating computing resources to tasks include receiving first data and second data. The first data indicates a limit for unblocked execution by a processor of a set of at least one task that includes instructions for the processor. The second data indicates a maximum use of the processor by the set. It is determined whether a particular set of at least one task has exceeded the limit for unblocked execution based on the first data. If it is determined that the particular set has exceeded the limit, then execution of the particular set by the processor is blocked for a yield time interval based on the second data. These techniques can guarantee that no time-critical tasks of an embedded system on a specific-purpose device are starved for processor time by tasks of foreign applications also executed by the processor.

Abstract: Provided is a virtual machine including a first virtualization module operating on a physical CPU, for providing a first CPU, and a second virtualization module operating on the first CPU, for providing second CPU. The second virtualization module includes first processor control information holding a state of the first CPU obtained at a time of execution of the user program. The first virtualization module includes second processor control information containing a state of the physical CPU obtained at the time of the execution of the second virtualization module, third processor control information containing a state of the physical CPU obtained at the time of the execution of the user program, and prefetch entry information in which information to be prefetched from the third processor control information is set, and, upon detection of a event, the information set in the prefetch entry information is reflected to the first processor control information.

Abstract: According to an aspect of the disclosure, a printing system is provided comprising a plurality of resources including idle and non-idle resources having a at least one image marking engine. The plurality of resources includes a page parallel RIP system wherein the RIP system supports configurable sized print chunks. The RIP system adaptively adjusts the size of the chunks according to the busyness of receiving RIP nodes.

Abstract: Provided is a method and apparatus for measuring a progress or a performance of an application program in a computing environment using a micro-architecture. An apparatus for thread progress tracking may select a thread included in an application program, may determine, based on a predetermined criterion, whether an execution scheme for at least one instruction included in the thread corresponds to an effective execution scheme in which an execution time is uniform or a non-effective execution scheme in which a delayed cycle is included and the execution time is non-uniform, and may generate an effective progress index (EPI) by accumulating an execution time of an instruction executed by the effective execution scheme other than an instruction executed by the non-effective execution scheme.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: Methods and systems are disclosed that relate to handling interrupts across multiple software instances. An exemplary method includes receiving an interrupt at a current CPU. An instance includes a set of independent threads of execution each with its own code context, interrupt service routines, drivers, and operating system services. The method further includes storing context information relating to the first instance, identifying the second instance associated with the interrupt, running at least one interrupt service routine, and restoring the context information relating to the first instance.

Abstract: A system and method employing the system for pushing work request associated contexts into a computer device includes issuing a request to a device in a computer system. Context data is fetched from a data storage device for the device. Context is determined for specified data requests, and context misses in the device are predicted. The system and method then initiates a context push and pushes the context into the device using a controller when a context miss is detected. Thereby, reducing the context miss latency time or delay in retrieving context data.

Abstract: Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first critical region with an interrupt routine. The thread may be set to restart at a beginning of the first critical region in response to an indication that the thread is working in a critical region. Other embodiments are also claimed and disclosed.

Abstract: Mechanisms for executing a transaction in the data processing system are provided. A transaction checkpoint data structure is generated in internal registers of a processor. The transaction checkpoint data structure stores transaction checkpoint data representing a state of program registers at a time prior to execution of a corresponding transaction. The transaction, which comprises a first portion of code that is to be executed by the processor, is executed. An interrupt of the transaction is received while executing the transaction and, as a result, the transaction checkpoint data is stored to a data structure in a memory of the data processing system. A second portion of code is then executed. A state of the program registers is restored using the data structure in the memory of the data processing system in response to an event occurring causing a switch of execution of the processor back to execution of the transaction.

Abstract: A method for context switching on a video processor having a scalar execution unit and a vector execution unit. The method includes executing a first task and a second task on a vector execution unit. The first task in the second task can be from different respective contexts. The first task and the second task are each allocated to the vector execution unit from a scalar execution unit. The first task and the second task each comprise a plurality of work packages. In response to a switch notification, a work package boundary of the first task is designated. A context switch from the first task to the second task is then executed on the work package boundary.

Abstract: Disclosed is a system with multiple virtual machines passing I/O requests via a shared memory space. A flag in shared memory is set to a first state in response to a first hypervisor I/O interrupt to indicate that an I/O processing routine is active (running). I/O requests are retrieved from an I/O queue in the shared memory by the I/O processing routine. Based on an indicator that there are no I/O requests remaining in said I/O queue, the shared flag is set to a second state to indicate that the I/O processing routine is deactivated (sleeping). In response to said shared flag being in the second state, when new I/O requests are going to be made, a second hypervisor I/O interrupt is generated. In response to said shared flag being in said first state, I/O requests are inserted into the I/O queue without generating a second hypervisor I/O interrupt.

Abstract: A user interface can be maintained in a responsive state on a user interface thread while synchronous application logic is running on a background thread. The application logic can access an object on the background thread, and the user interface can access the same object on the user interface thread. Additionally, a request for work to be done on an object can be received. If the request is to be dispatched to a background thread, then the work can be dispatched to the background thread without blocking the user interface thread. However, if the request is to be dispatched to the user interface thread, then the work can be dispatched to the user interface thread, and the background thread can be blocked.

Abstract: Provided is a program control device which switches, per timeslot, between threads to be executed. The program control device includes: a first interrupt creation unit which creates a first interrupt signal which designates a timeslot as a destination; and a first receiving unit which [i] does not receive the first interrupt signal if the timeslot as the destination is not a current timeslot, and [ii] receives the first interrupt signal if the timeslot as the destination is the current timeslot.

Abstract: Methods of multi-threading, and systems thereof, are described. A first thread is executed. Context for the executing thread is maintained in a working register. Execution of the first thread is halted and execution of a second thread is begun by performing a rollback operation. The rollback operation causes context for the second thread to be copied from a first register into the working register.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: A method of optimizing multi-set context switch for embedded processors includes the steps of partitioning a plurality of registers into a plurality of register sets based on a live-range-sensitive context-switch procedure that is associated with a usage frequency of each of the registers, storing contents of first target registers according to live set information of a current task, wherein the first target registers are selected from the register sets, determining a next task by an operating system and updating the live set information according to the next task, and restoring contents of second target registers according to the updated live set information, wherein the second target registers are selected from the register sets.

Abstract: A system and method are disclosed for recreating graphics processing unit (GPU) state information associated with a migrated virtual machine (VM). A VM running on a first VM host coupled to a first graphics device, comprising a first GPU, is migrated to a second VM host coupled to a second graphics device, in turn comprising a second GPU. A context module coupled to the first GPU reads its GPU state information in its native GPU state representation format and then converts the GPU state information into an intermediary GPU state representation format. The GPU state information is conveyed in the intermediary GPU state representation format to the second VM host, where it is received by a context module coupled to the second GPU. The context module converts the GPU state information related to the first GPU from the intermediary GPU state representation format to the native GPU state representation format of the second GPU.

Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.

Abstract: A method for operating a sensor based application includes receiving a context hierarchy for the sensor based application, the context hierarchy comprising a plurality of contexts, wherein each of the contexts is assigned a level of interest and a priority, reading the context hierarchy and discovering at least one sensor associated with each of the plurality of contexts, and reading at least one value of each of the sensors, and applying the values.