Abstract: Transactional Lock Elision (TLE) may allow threads in a multi-threaded system to concurrently execute critical sections as speculative transactions. Such speculative transactions may abort due to contention among threads. Systems and methods for managing contention among threads may increase overall performance by considering both local and global execution data in reducing, resolving, and/or mitigating such contention. Global data may include aggregated and/or derived data representing thread-local data of remote thread(s), including transactional abort history, abort causal history, resource consumption history, performance history, synchronization history, and/or transactional delay history. Local and/or global data may be used in determining the mode by which critical sections are executed, including TLE and mutual exclusion, and/or to inform concurrency throttling mechanisms. Local and/or global data may also be used in determining concurrency throttling parameters (e.g.

Abstract: A method to handle peak database workloads may include requesting resources, receiving virtual-machine information in response to the requesting, allocating first and second portions of a workload according to the virtual-machine information, processing the first portion on a virtual machine to generate a first result, creating a cloned virtual machine with a virtualization layer, and cloning with the virtualization layer a storage allocated to the virtual machine to create a cloned storage.

Abstract: A method and system are provided that determine a likelihood that at least one special purpose register (SPR) will be required during execution of a thread; after determining that the SPR is not likely required during execution of the thread, set a flag for the thread to indicate that the SPR is not required; and after determining that the SPR is likely required during execution of the thread, set the flag to indicate that the SPR is required.

Abstract: An information processing device for causing a processor to execute a plurality of threads by switching between them. Each thread performs a process in correspondence with an obtainment of an event. The information processing device, when causing a second thread to transit from a non-execution state to an execution state to replace a first thread, detects whether or not, in the first thread having transited to the non-execution state, a next start position of a process belongs to an already processed part, detects whether or not a start position of a process in the second thread in the execution state belongs to the processed part; and determines whether or not to set a context for execution of the second thread into the processor in accordance with detection results of the first and second detection units, and performs processing in accordance with the determination.

Abstract: Logic (also called “synchronizing logic”) in a co-processor (that provides an interface to memory) receives a signal (called a “declaration”) from each of a number of tasks, based on an initial determination of one or more paths (also called “code paths”) in an instruction stream (e.g. originating from a high-level software program or from low-level microcode) that a task is likely to follow. Once a task (also called “disabled” task) declares its lack of a future need to access a shared data, the synchronizing logic allows that shared data to be accessed by other tasks (also called “needy” tasks) that have indicated their need to access the same. Moreover, the synchronizing logic also allows the shared data to be accessed by the other needy tasks on completion of access of the shared data by a current task (assuming the current task was also a needy task).

Abstract: Non-intrusive techniques have been developed to dynamically and selectively alter address translations performed by, or for, a processor. For example, in some embodiments, a memory management unit is configured to map from effective addresses in respective effective (or virtual) address spaces to physical addresses in the memory, wherein the mappings performed by the memory management unit are based on address translation entries of an address translation table. For a subset of less than all processes, entry selection logic selects from amongst plural alternative mappings coded in respective ones of the address translation entries. For at least some effective addresses mapped for a particular process of the subset, selection of a particular address translation entry is based on an externally sourced value. In some embodiments, only a subset of effective addresses mapped for the particular process are subject to dynamic runtime alteration of the address translation entry selection.

Abstract: A system and method are presented for converting a multi-boot computer to a virtual machine. Existing boot images on a multi-boot computer are identified and converted into virtual machine instances. Each virtual machine instance represents an operating system and is capable of running at the same time. Finally, a new hosting operating system is installed. The new hosting operating system launches and manages the converted virtual machine instances.

Abstract: Disclosed is an information processing device and a task switching method that can reduce the time required for switching of tasks in a plurality of coprocessors. The information processing device includes a processor core; coprocessors including operation units that perform operation in response to a request from the processor core and operation storage units that store the contents of operation of the operation units, save storage units that store the saved contents of operation, a task switching control unit that outputs a save/restore request signal when switching a task on which operation is performed by the coprocessors-, and save/restore units that perform at least one of saving of the contents of operation in the operation storage units to the save storage units and restoration of the contents of operation in the save storage units to the operation storage units in response to the save/restore request signal.

Abstract: A task execution method for executing a plurality of tasks while switching the tasks from one to another by time-sharing, wherein an allocated time is allocated for each of the plurality of tasks, and the plurality of tasks includes a plurality of first-type tasks and a single second-type task, and the task execution method includes a task selection step which selects a task from among the plurality of tasks according to a predetermined sequence, a correction step which corrects an allocated time for the second-type task so that execution of the plurality of tasks completes within the cycle time, when the task selected is a second-type task, which is the total allocated time for the plurality of tasks, and a task execution control step which causes the selected task to be executed so that the execution of the selected task completes within the allocated time or the corrected allocated time.

Abstract: A profiler may analyze processes being run by a processor. The profiler may include logic to periodically sample a value of an instruction pointer that indicates an instruction in the first process that is currently being executed by the processor and logic to update profile data based on the sampled value. The profiler may additionally include logic to determine, in response to a context switch that includes the operating system switching the active process from the first process to another of the plurality of processes, whether the first process executes for greater than a first length of time; logic to stop operation of the profiler when the first process executes for greater than the first length of time; and logic to clear the profile data when the first process fails to execute for greater than the first length of time.

Abstract: The present disclosure is directed to a method and system for task switching with inline execution. In accordance with a particular embodiment of the present disclosure, a first state and a second state are identified for a function executing in the first state. A switch routine is invoked at a particular execution point in the function. A work element is generated in the switch routine. The work element includes status information for the function. The work element is transmitted to at least one alternate state task. The first state is altered to the second state according to the work element. Execution of the function in the second state is resumed at the particular execution point.

Abstract: Logical processors/hardware contexts are assigned to different jobs/threads in a multithreaded/multicore environment. There are provided a number of different sorting algorithms, from which one is periodically selected on the basis of whether the present algorithm is giving satisfactory results or not. The period is preferably a super-context interval. The different sorting algorithms preferably include a software/OS priority. A second sorting algorithm may include sorting according to hardware performance measurements. The judgement of satisfactory performance is preferably based on the difference between a desired number of time quantum attributed per super-context switch interval to each job/thread and a real number of time quantum attributed per super-context switch interval to each job/thread.

Abstract: A membership interface provides procedure headings to add and remove elements of a data collection, without specifying the organizational structure of the data collection. A membership implementation associated with the membership interface provides thread-safe operations to implement the interface procedures. A blocking-bounding wrapper on the membership implementation provides blocking and bounding support separately from the thread-safety mechanism.

Abstract: The invention relates to a method for preventing industrial automation system from avalanche, in which the industrial automation system comprising a storage unit for storing time stream data to be processed and a CPU for processing the time stream data in the storage unit, the method comprises the following items: 1) establishing a data processing task priority level; 2) scheduling the data processing task of the CPU; 3) using method of the storage unit. Under a given CPU processing ability, the time stream data to be processed is set with different priority levels, the CPU firstly processes the to-be-processed data processing task with the highest priority level and then processes those with the next priority level. And the storage unit is also set with the corresponding sub-storage units with different priority levels in accordance with the priority levels of the to-be-processed data processing task.

Abstract: Systems and methods for efficient thread arbitration in a processor. A processor comprises a multi-threaded resource. The resource may include an array of entries which may be allocated by threads. A thread arbitration table corresponding to a given thread stores a high and a low threshold value in each table entry. A thread history shift register (HSR) indexes the table, wherein each bit of the HSR indicates whether the given thread is a thread hog. When the given thread has more allocated entries in the array than the high threshold of the table entry, the given thread is stalled from further allocating array entries. Similarly, when the given thread has fewer allocated entries in the array than the low threshold of the selected table entry, the given thread is permitted to allocate entries. In this manner, threads that hog dynamic resources can be mitigated such that more resources are available to other threads that are not thread hogs.

Abstract: Provided are a method, system, and program for executing multiple threads in a processor. Credits are set for a plurality of threads executed by the processor. The processor alternates among executing the threads having available credit. The processor decrements the credit for one of the threads in response to executing the thread and initiates an operation to reassign credits to the threads in response to depleting all the thread credits.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. A task control circuit is provided with a task selection circuit and state storage units associated with respective tasks. When executing a predetermined system call instruction, the CPU notifies the task control circuit accordingly. When informed of the execution of a system call instruction, the task control circuit selects a task to be subsequently executed in accordance with an output from the selection circuit. When an interrupt circuit receives a high-speed interrupt request signal, the task switching circuit controls the state transition of a task by executing an interrupt handling instruction designated by the interrupt circuit.

Abstract: Backup systems and methods are disclosed for a virtual computing environment. Certain examples include a system having a backup management server that communicates with a host server having at least one virtual machine. The management server coordinates with the host server to perform backup copies of entire virtual machine disks from outside the guest operating system of the virtual machine. In certain examples, such backup systems further utilize a volume shadow copy service executing on the host server to quiesce virtual machine applications to put data in a consistent state to be backed up. The backup system then utilizes hypervisor snapshot capabilities of the host server to record intended changes to the virtual machine disk files while such files are being copied (e.g., backed up) by the host server. Such recorded changes can be later committed to the virtual machine disk files once the backup operation has completed.

Abstract: Systems and methods for optimizing the task scheduling efficiency of firmware and/or software associated with optoelectronic transceiver devices. In one example, a scheduling module executes microcode that schedules tasks based on the operational parameters. The scheduling module compares operational parameters with their last known values and then flags necessary tasks to be initiated. The scheduling module flags only those tasks that rely on a particular operational parameter and only if the operational parameter has changed in value since the most recent time that it has been measured. Specifically, the scheduling module identifies leading tasks and dependent tasks and flags tasks only if data that relies on the operating parameter has changed since a previous task scheduling determination.

Abstract: A task migration system is provided which transmits a migration request signal for a plurality of first tasks to a migration manager using a resource manager, transmits information used in response to the migration request signal from a migration initiation handler to the migration manager when a first task, of which a migration point is in a capture ready state, among the plurality of first tasks is received from a processor, and captures, using the migration manager, the migration point of the first task in the capture ready state, in response to a migration request signal for the first task in the capture ready state, so that the first task with the captured migration point migrates to a second task.

Abstract: A task processor includes a CPU, a save circuit, and a task control circuit. The CPU is provided with a processing register and an execution control circuit operative to load data from a memory into a processing register and execute a task in accordance with the data in the processing register. The task control circuit is provided with a task selecting circuit and state storage units respectively associated with tasks. In executing a predetermined system call, the execution control circuit notifies the task control circuit as such. Upon being notified of the execution of the system call instruction, the task control circuit switches a task to be executed next in accordance with an output from the task selecting circuit. The task selecting circuit selects a task in accordance with an output from the state registers.

Abstract: Techniques for providing access to physical resources in a virtual machine environment are provided. A virtual machine may access physical resources using device drivers that have been divided. After monitoring a performance of device drivers operating in a virtual machine, the device drivers that are underperforming or that experience a high rate of context switches are identified. These device drivers are adapted dynamically into portions that execute in an untrusted domain and in a trusted domain. Running a portion of the device driver in the trusted domain eliminates context switches and improves performance of the virtual machine.

Abstract: Performing directed switches between user mode schedulable (UMS) threads and primary threads enable proper execution of the UMS threads. A primary thread user portion is switched to a UMS thread user portion so that the UMS thread user portion is executed in user mode via the primary thread user portion. The primary thread is then transferred into kernel mode via an implicit switch. A kernel portion of the UMS thread is then executed in kernel mode using the context information of a primary thread kernel portion.

Abstract: Methods, systems, apparatuses and program products are disclosed for providing timer use and timer based execution parallelism during the DXE phase of computer start-up. Provision is made for loading a microkernel (or other kernel program) which presents itself as though it were a DXE Driver and changes a single threaded environment into a multithreaded environment.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, processing a computational load by a first core of a multi-core processor, and dynamically distributing at least a portion of the computational load to a second core of the multi-core processor to reduce a power density of the multi-core processor for the processing of the computational load.

Abstract: The present disclosure provides methods and apparatus for fast context switching in a virtualized system. In the disclosed system, a globally unique application-space identifier is associated with each guest application. No two applications share the same application-space identifier, even if the two applications reside in different virtual machines. Domain identifiers are used to ensure that a guest's mappings are only active when that guest is executing. A unique domain identifier is associated with each virtual machine, and all translation lookaside buffer entries thereby mapping the guest's kernel pages with that domain value. All other mappings are tagged with a predefined domain such as zero. In addition, a virtual memory management unit may be configured to support two virtual page table pointers and a configurable boundary between a virtual user page table and a virtual kernel page table.

Abstract: Embodiments of apparatuses and methods for guest processes to access registers are disclosed. In one embodiment, an apparatus includes an interface to a first register, shadow logic, evaluation logic, and exit logic. The shadow logic is to, in response to a guest attempt to write data to the first register, cause the data to be written to a second register. The evaluation logic is to determine, based on the value of the data, whether to transfer control to a host in response to the guest attempt. The exit logic is to transfer control to the host after the data is written to the second register if the evaluation logic determines to transfer control.

Abstract: Provided is a method and an apparatus for selectively returning parameters from an invoked object. Specifically, a requestor can invoke an object by transmitting a message. The message can include specified return parameters from an interface, such as an interface definition language (IDL). Alternatively, an object stub locally accessible by the requester can be invoked. The object stub, similar to the IDL, can specify the parameters to return. After the execution of a method in the invoked object, the requestor receives the return parameters or a subset of the return parameters previously selected.

Abstract: A packet processing system includes multiple processors and a set of code partitions that implement a feature set for packet processing. Each of the processors is capable of loading and executing one or more of the code partitions. A context manager enables packet processing operations to migrate between code partitions executing on one or more of the processors.

Abstract: A virtual machine system includes a first operating system for operating a virtual machine, a first manager for controlling to divide a physical resource into a plurality of virtual resources and assign at least one of the plurality of virtual resources as a unit to the virtual machine, the physical resource including at least a central processing unit and a memory, and a second operating system for controlling the first operating system, the second operating system being connected to a storage unit.

Abstract: A method and system for software emulation of hardware support for multi-threaded processing using virtual hardware threads is provided. A software threading system executes on a node that has one or more processors, each with one or more hardware threads. The node has access to local memory and access to remote memory. The software threading system manages the execution of tasks of a user program. The software threading system switches between the virtual hardware threads representing the tasks as the tasks issue remote memory access requests while in user privilege mode. Thus, the software threading system emulates more hardware threads than the underlying hardware supports and switches the virtual hardware threads without the overhead of a context switch to the operating system or change in privilege mode.

Abstract: In a method for switching to a spare processor during runtime, a processing system determines that execution should be migrated off of an active processor. An operating system (OS) scheduler and at least one device are then paused, and the active processor is put into an idle state. State data from writable and substantial non-writable stores in the active processor is loaded into the spare processor. Interrupt routing table logic for the processing system is dynamically reprogrammed to direct external interrupts to the spare processor. The active processor may then be off-lined, and the device and OS scheduler may be unpaused or resumed. Threads may then be dispatched to the spare processor for execution. Other embodiments are described and claimed.

Abstract: Management of contexts that execute on a computer system is described. More specifically, context scheduling in a virtual machine environment is described. Times at which a context transitions from a scheduled state to a descheduled state and times at which the context transitions from a descheduled state to a scheduled state are recorded for each context. Skew is detected using the recorded times. The amount of skew can be quantified, and a corrective action is triggered if the amount of skew fails to satisfy a threshold value.

Abstract: Various operations are disclosed for improving the operational efficiency of register handling in a virtualized environment. Some infrequently accessed software managed registers are managed lazily when switching contexts between virtual processors. The states of those registers are not saved on exit from a guest or restored on entry to the guest. Rather, guest accesses to those registers are intercepted. For some frequently accessed registers, register states are saved or restored only upon exit from a hypervisor to a different guest that that from which the hypervisor was entered. For enable-flag-gated registers, updates to a physical register value are not made unless the register is enabled. A shadow register cache may be used to speed accesses to some registers. When a shadowed register is modified, the new value is cached as a shadow copy in RAM and subsequent reads of the register are taken from the shadow copy.

Abstract: Computer implemented methods, computer program products and computer systems synchronize copies of a virtual disk. A record of blocks that are modified during an access session of a copy of the virtual disk is maintained. For each partition of the virtual disk, a file system level indication of currently relevant blocks is obtained. Only those blocks that were modified during the access session and are currently relevant are copied to at least one additional copy of the virtual disk.

Abstract: An interruptible thread synchronization method and apparatus are provided. The interruptible thread synchronization method includes controlling mutually exclusive access to an object by one or more threads using a monitor, and interrupting a first thread that is on standby for the monitor. The interruptible thread synchronization method and apparatus allows for access and control of an object by one or more threads.

Abstract: Exemplary embodiments include a system and storage medium for managing computer processing functions in a multi-processor computer environment. The system includes a physical processor, a standard logical processor, an assist logical processor sharing a same logical partition as the standard logical processor, and a single operating system instance associated with the logical partition, the single operating system instance including a switch-to service and a switch-from service. The system also includes a dispatch component managed by the single operating system instance. Upon invoking the switch-to service by standard code, the switch-to service checks to see if an assist logical processor is online and, if so, it updates an integrated assist field of a work element block associated with the task for indicating the task is eligible to be executed on the assist logical processor. The switch-to service also assigns a work queue to the work element block.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: Data transfer during processor context switching is reduced, particularly in relation to a time-sharing microtasking programming model. Prior to switching context of a processor having local memory from a first to a second process, a portion of the local memory that does not require transfer to system memory for proper saving of data associated with the first process is determined. The context of the processor is then switched from the first to the second process, including transferring all of the local memory as the data associated with the first process, to system memory—except for the portion of the local memory that has been determined as not requiring saving to the system memory for proper saving of the data associated with the first process. Therefore, switching the context from the first to the second process results in a reduction of data transferred from the local memory to the system memory.

Abstract: The computer program includes a virtualization software that is executable on the new processor in the legacy mode. The new processor includes a legacy instruction set for a legacy operating mode and a new instruction set for a new operation mode. The switching includes switching from the new instruction set to the legacy instruction set and switching paging tables. Each of the new operating mode and the legacy operating mode has separate paging tables. The switch routine is incorporated in a switch page that is locked in physical memory. The switch page has a first section to store a part of switching instructions conforming to the new instruction set and a second section to store another part of the switching instructions conforming to the legacy instruction set.

Abstract: Attempts are made to reduce the system overhead generated at the time of context save/restore processing to perform process switching in a virtual machine system. In a CPU occupancy mode that a physical CPU is exclusively allocated to virtual machines, a logical CPU process running on the physical CPU is static, so that it is not necessary to save/restore the context every time the processes are switched. When a switching source process is a logical CPU process in a CPU occupancy mode, a context save is temporarily suspended. When switching to the same logical CPU process is made again continuously, save/restore is skipped. When the logical CPU process of a VMM control VM runs in that period, the logical CPU process whose save is delayed is recorded and saved late.

Abstract: Various technologies and techniques are disclosed that provide fast context switching. One embodiment provides a method for a context switch comprising preloading a host virtual machine context in a first portion of a processor, operating a guest virtual machine in a second portion of the processor, writing parameters of the host virtual machine context to a memory location shared by the host virtual machine and the guest virtual machine, and operating the host virtual machine in the processor. In this manner, a fast context switch may be accomplished by preloading the new context in a virtual processor, thus reducing the delay to switch to the new context.

Abstract: A mechanism for controlling instruction fetch and dispatch thread priority settings in a thread switch control register for reducing the occurrence of balance flushes and dispatch flushes for increased power performance of a simultaneous multi-threading data processing system. To achieve a target power efficiency mode of a processor, the illustrative embodiments receive an instruction or command from a higher-level system control to set a current power consumption of the processor. The illustrative embodiments determine a target power efficiency mode for the processor. Once the target power mode is determined, the illustrative embodiments update thread priority settings in a thread switch control register for an executing thread to control balance flush speculation and dispatch flush speculation to achieve the target power efficiency mode.

Abstract: A method and a system are described that involve processing a request in multiple threads and dispatching the request to a set of applications. The method includes receiving the request, wherein the request contains application context and session data, creating a request context object and associating it with the application context and the session data, storing an identifier of a first thread that processes the request in the request context object associated with the thread, creating a set of threads from the first thread to process the request in parallel threads, each thread in the set having a unique identifier and inheriting the request context object from the first thread, and invoking a request dispatcher on each thread in the set to forward the request to the set of applications.

Abstract: A processor includes: a plurality of registers; an instruction readout circuit configured to read out an instruction from a memory; an instruction generation circuit configured to generate instructions for saving data into a predetermined storage area, for the respective registers, if the instruction read out by the instruction readout circuit is an instruction causing the data stored in each of the plurality of registers to be saved; and an instruction execution circuit configured to execute the instruction read out from the memory and the instructions generated by the instruction generation circuit.

Abstract: In one embodiment, a method includes powering on a testing system, whereby a unit present signal is included in the system, the unit present signal communicating to a management complex unit (MCU) that a unit under test (UUT) has been inserted into a corresponding architecture, the signal being sent through a relay such that it can be sent or connected at a later time. The UUT is installed in the system and a programming protocol is initiated. The system is then powered off, whereby the unit present signal is set to open and the system is subsequently powered on. When the UUT is plugged in, the MCU does not see it. The system can include a second relay that allows power being fed to the UUT to be broken such that when the UUT is subsequently powered up, the board is reset and not removed from the architecture.

Abstract: The simultaneous processing of requests under multiple user identifiers is facilitated. The requests are processed by user servers, in which a user server has an association with a particular user. A user server has a static identity associated therewith and is capable of processing a plurality of requests prior to terminating. The requests are dispatched to the appropriate user servers via a dispatcher server coupled to the user servers.

Abstract: In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.

Abstract: A method of using co-routines to implement a function-like interface between a BASIC program and the points in the system where SIP and SDP data (for example) are to be modified. This co-routine interface is intuitive from the end-user's perspective, and both real-time efficient and flexible from the system designer's perspective, and is applied to provide user-customized SIP and SDP modifications in an easy-to-use way that gives the end-user great flexibility while protecting the system from the undesirable side-effects that could result from a tightly coupled co-routine interface.