Abstract: A method and system for scheduling tasks on a processor, the tasks being scheduled by an operating system to run on the processor in a predetermined order, the method comprising identifying and creating task groups of all related tasks; assigning the tasks in the task groups into a single common run-queue; selecting a task at the start of the run-queue; determining if the task at the start of the run-queue is eligible to be run based on a pre-defined timeslice allocated and on the presence of older starving tasks on the runqueue; executing the task in the pre-defined time slice; associating a starving status to all unexecuted tasks and running all until all tasks in the run-queue complete execution and the run-queue become empty.

Abstract: A mechanism is provided for determining whether to use cache affinity as a criterion for software thread dispatching in a shared processor logical partitioning data processing system. The server firmware may store data about when and/or how often logical processors are dispatched. Given these data, the operating system may collect metrics. Using the logical processor metrics, the operating system may determine whether cache affinity is likely to provide a significant performance benefit relative to the cost of dispatching a particular logical processor to the operating system.

Abstract: A channel-less system and method are provided for multithreaded communications with a direct memory access (DMA) controller. The method accepts a plurality of DMA command messages directed to a fixed port address. The DMA command messages are arranged in a first-in first-out (FIFO) queue, in the order in which they are received. The DMA command messages are supplied to a DMA controller from the FIFO queue, and in response to the DMA command message, data transfer operation are managed by the DMA controller. Following the completion of each data transfer operation, a transfer complete message indicating completion is sent. In one aspect, DMA command messages are arranged in a plurality of parallel FIFO queues, and CD sets are stored in a plurality of context memories, where each context memory is associated with a corresponding FIFO queue.

Abstract: A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.

Abstract: The multi-threading changeover control apparatus of the present invention changes over threads in an information processing device in which a multi-threading method is used, and comprises a thread changeover request unit outputting a thread changeover request signal after a cache miss occurs in which an instruction to be fetched is not stored when the instruction is fetched or a thread execution priority order change request unit outputting a thread execution priority order change request signal.

Abstract: A method of enabling state save and debug operations for co-routines for first failure data capture (FFDC) in an event-driven environment. A stack management utility allocates space for a context structure, which includes a state field, and a stack pointer in a buffer. A context management utility initializes a first context structure of a first co-routine and saves a state of the first context structure in response to an execution request for a second co-routine. The context management utility sets a second context structure as a current context. When execution of the current context is complete, the context management utility restores the first context structure of the first co-routine as the current context. If the state field is not set to a valid value, a state save function “state saves” all allocated co-routine stacks and context structures, restores the entire system to a previous valid state, and restarts operations.

Abstract: Provided is a method and apparatus for ensuring a deterministic execution characteristic of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A lock controlling apparatus based on a deterministic progress index (DPI) may include a loading unit to load a DPI of a first core and a DPI of a second core among DPIs of a plurality of cores at a lock acquisition point in time of each thread, a comparison unit to compare the DPI of the first core and the DPI of the second core, and a controller to assign a lock to a thread of the first core when the DPI of the first core is less than the DPI of the second core and when the second core corresponds to a last core to be compared among the plurality of cores.

Abstract: Provided is the virtual computer system including an emulation module for emulating an operation based on an operation code for executing the operation of hardware of a server system, an exception event handler module for calling the emulation module when an exception event is generated by a CPU, a code management module for managing a promotion code for emulating the operation of the hardware of the server system, a frequency judgment module for judging whether a frequency of the operation of the hardware of the server system is high, and a switching module for determining whether to call the emulation module by the exception event handler module or to call the emulation module by executing the promotion code based on the judged frequency. Accordingly, the virtual computer system can simultaneously achieve high performance and memory saving in an emulation system.

Abstract: An article of manufacture, method and system are provided for facilitating input/output (I/O) processing of at least one guest processing system. The article of manufacture includes at least one computer-usable medium having computer-readable program code logic to facilitate the I/O processing of the at least one guest processing system. The computer-readable program code logic when executing performing the following: emulating on a native system an I/O architecture for the at least one guest processing system, the emulating including: providing multiple device managers for a plurality of I/O devices of the I/O architecture; providing at least one communications adapter process interfacing the multiple device managers to the at least one network driver process; and wherein the multiple device managers translate I/O messages in at least one guest processing system format to messages in native system format for processing by the at least one communications adapter process, thereby facilitating I/O processing.

Abstract: The present invention provides an apparatus and method that increases the utilization by processors on shared resources. It provides the minimum latency in a multiprocessor system during usage right exchange between multi-processors on a shared resource. The apparatus provides a timed mailbox including a timer. The timed mailbox is at least associated with a first processor and a second processor. The second processor starts to utilize a shared resource to perform a task. According to a predetermined clock cycle number, the timed mailbox issues a signal in advance to notify the first processor of the availability of the shared resource to be utilized by the first processor.

Abstract: Machine-readable media, methods, apparatus and system are described. In some embodiments, a virtual machine monitor of a computer platform may comprise a service virtual machine created by the virtual machine monitor partitioning an underlying hardware machine to support execution of a plurality of overlying guest operating systems, wherein the plurality of guest operating systems comprise a guest operating system complying with a non-native guest system architecture different from a host system architecture with which the hardware machine complies. The service virtual machine may further comprise a translation layer to translate instructions from the guest operating system complying with the non-native guest system architecture into instructions complying with the host system architecture.

Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.

Abstract: A method of virtualizing memory through shadow page tables that cache translations from multiple guest address spaces in a virtual machine includes a software version of a hardware tagged translation look-aside buffer. Edits to guest page tables are detected by intercepting the creation of guest-writable mappings to guest page tables with translations cached in shadow page tables. The affected cached translations are marked as stale and purged upon an address space switch or an indiscriminate flush of translations by the guest. Thereby, non-stale translations remain cached but stale translations are discarded. The method includes tracking the guest-writable mappings to guest page tables, deferring discovery of such mappings to a guest page table for the first time until a purge of all cached translations when the number of untracked guest page tables exceeds a threshold, and sharing shadow page tables between shadow address spaces and between virtual processors.

Abstract: A control apparatus for an input-output device includes a hardware part and a software part, in which a controller in the hardware part carries out a control operation in accordance with a signal from the input-output device, outputs a result of the control operation to a process, and has a timer unit to be excited at a constant period; and the software part has an information process part, a control process part, and an interrupt control unit to switch over the information process part and control process part one another, in which the interrupt control unit suspends an execution of the information process part to execute the control process part in priority and resume the information process part by switching over to the information process part from the control process part, when the execution of the control process part is terminated.

Abstract: Provided is a method and apparatus for measuring a performance or a progress state of an application program to perform data processing and execute particular functions in a computing environment using a micro architecture. A thread progress tracking apparatus may include a selector to select at least one thread constituting an application program; a determination unit to determine, based on a predetermined criterion, whether an instruction execution scheme corresponds to a deterministic execution scheme having a regular cycle or a nondeterministic execution scheme having an irregular delay cycle with respect to each of at least one instruction constituting a corresponding thread; and a deterministic progress counter to generate a deterministic progress index with respect to an instruction that is executed by the deterministic execution scheme, excluding an instruction that is executed by the nondeterministic execution scheme.

Abstract: A computer system includes an Open Bus Hypervisor having the highest privilege level. An Open Bus Hypervisor is a set of modules that operate on the root level. The Open Bus Hypervisor provides support for processing, filtering and redirecting of low level events. The Open Bus Hypervisor is used primarily for maintenance and support of computer virtualization features, which are implemented within computer system CPU. Additionally, the Open Bus Hypervisor can be used for supporting new hardware and software modules installed on a computer system. A Virtual Machine Monitor (VMM) runs with fewer privileges than the Open Bus Hypervisor. A Primary Virtual Machine (PVM) runs without system level privileges and has a Primary Operating System (POS) running within it.

Abstract: A system, methods and apparatus perform remote access commands between nodes and allow preemption of context resources in an architecture such as Infiniband. The system detects an original request in a request queue for a data access task to access data from a first node to a second node and issues a first request from a first node to a second node. The first request requests the data access task be performed between the first node and the second node. The system receives, at the first node, a first response from the second node that partially completes the data access task. The system issues at least one subsidiary request from the first node to the second node to further complete the data access task between the first node and the second node. The subsidiary request(s) are based on an amount of partial completion of the data access task between the first node and the second node.

Abstract: A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The system includes a state machine that determines an optimum length of a pipeline architecture based on a processing function to be performed. A pipeline sequence controller, responsive to the state machine, varies the depth of the pipeline based on the optimum length. A plurality of clock splitter elements, each associated with a corresponding plurality of latch stages in the pipeline architecture, are coupled to the pipeline sequence controller and adapted to operate in a functional mode, one or more clock gating modes, and a pass-through flush mode. For each of the clock splitter elements operating in the pass-through flush mode, data is passed through the associated latch stage without oscillation of clock signals associated therewith.

Abstract: A multi-mode parallel 3-D graphics system having multiple graphics processing pipelines with multiple GPUs supporting a parallel graphics rendering process having time, frame and object division modes of operation, wherein each GPU comprises video memory, a geometry processing subsystem and a pixel processing subsystem, and wherein 3D scene profiling is performed in real-time, and the parallelization state/modes of the system are dynamically controlled to meet graphics application requirements. The multiple modes of parallel graphics rendering use real-time graphics application profiling, and dynamic control over time-division, frame-division, and object-division modes of parallel operation, within the same parallel graphics platform, which can be realized on PC-based computing system architectures.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: A system for sharing a trusted platform module (TPM) comprises a TPM operable to execute an operating system (OS)-level process, the TPM operable to pause the execution of the OS-level process and execute a non-OS-level process.

Abstract: Data structure creation, organization and management techniques for data local to user-level threads are provided. In one embodiment, a method includes generating, for a user-level thread (“shred”) to run on a thread unit that is not managed by an operating system (“OS”), a storage area for local data and maintaining state in the storage area across a context switch from the thread unit that is not managed by the OS to a second thread unit that is managed by the OS. Other embodiments are also described and claimed.

Abstract: Systems and methods for switching from a first Internet context to a second Internet context without process shutdown are described. Internet context data, such as cookies, history and user-defined data, is stored in containers unique to each user on a system. Internet content is stored in a common location so redundant downloaded information is not stored. Content information is found or stored by hashing a URL and indexing the memory location according to the resulting hash value. If content data is specific to a particular user, a hash is performed on a combination of the URL and an ordinal associated with the user's unique identity to obtain a hash value unique to the user. The user-specific content is then stored and the memory location is indexed according to the unique hash value.

Abstract: A method, system, and computer usable program product for context aware data protection. Information about an access context is received in a data processing system. A resource affected by the access context is identified. The identification of the resource may include deriving knowledge about resource by making an inference from a portion of contents of the resource that the access context affects the resource, making an inference that the access context affects a second resource thereby inferring that the resource has to be modified, determining that the access context is relevant to the resource, or a combination thereof. The resource is received. A policy that is applicable to the access context is identified. A part of the resource to modify according to the policy is determined. The part is modified according to the policy and the access context to form a modified resource. The modified resource is transmitted.

Abstract: A system and method for managing a remote procedure call (RPC) system in a distributed system is disclosed. The distributed computing system is typically implemented as a client server model. A server implements several procedures and offers these procedures as services to clients in the distributed computing system. A server handles multiple RPC requests from multiple clients. A client sends an RPC request to a server; the server processes the requested procedure, and sends a reply back to the client.

Abstract: A device stores a plurality of applications and a list of associations for those applications. The applications are preferably stored within a secondary memory of the device, and once launched each application is loaded into RAM. Each application is preferably associated to one or more of the other applications. Preferably, no applications are launched when the device is powered on. A user selects an application, which is then launched by the device, thereby loading the application from the secondary memory to RAM. Whenever an application is determined to be associated with a currently active state application, and that associated application has yet to be loaded from secondary memory to RAM, the associated application is pre-launched such that the associated application is loaded into RAM, but is set to an inactive state.

Abstract: The invention sets forth an approach to context switching that utilizes scan chains modified to perform context switching operations. The design requires substantially less additional silicon area and design engineering effort than existing context switch approaches, while operating substantially faster and providing additional debug observability during context switching operations.

Abstract: A barrier synchronization register, accessible to the nodes in a distributed data processing system, has portions thereof allotted to threads which are present in multiple groups. The barrier synchronization register portion allotted to a given thread has stored therein, over time, group identifier numbers. In this way the state space of a barrier synchronization register is shared over more than one group of process threads.

Abstract: A method for providing a context-based service to a terminal of a communication network, includes, at a context server cooperating with the communication network: a) receiving a query from a service application suitable for implementing the context based service, the query indicating that the context server should perform an action when a query condition is fulfilled, the query condition referring to one or more attributes of derived context information indicative of a context of the terminal; b) generating a query evaluation trigger indicating that the query condition should be evaluated when the derived context information is updated; c) identifying raw context information allowing to derive the derived context information; d) generating a calculation trigger indicating that the derived context information should be calculated when an update of the raw context information is received from the terminal; e) receiving from the terminal an update of the raw context information and, according to the calculation

Abstract: A technique for quickly switching between a first operating system (OS) and a second OS involves deactivating the first OS and booting the second OS from memory. The technique can include inserting a context switching layer between the first OS and a hardware layer to facilitate context switching. It may be desirable to allocate memory for the second OS and preserve state of the first OS before deactivating the first OS and booting the second OS from memory.

Abstract: A virtual machine is extended to include native support for co-routines. In this manner, high-level programmers are afforded access to such functionality. More particularly, supplied is a mechanism inside the virtual machine to enable method/function state to be maintained and subsequently restored. Consequently, a method/function can be called multiple times and resume where it last left off. This provides direct support for tier splitting patterns, iterators and comprehensions, among other things.

Abstract: A computer system receives a data collection and creates an administration table. A main process locks the data collection against unauthorized access using an association, in a lock table, between it and a lock identifier required for data collection access by processes. The main process divides the data collection into subgroups. The lock identifier and each subgroup are forwarded to one of the processes; the subgroups being parallel processed by recipient processes that access and update the data collection using the lock identifier, and set the lock identifier and update the administration table regarding the processing done by the recipient process, the administration table being common to all of the subgroups. After the recipient processes, the data collection is unlocked by the main process by removing the association between the data collection and the lock identifier in the lock table.

Abstract: Adaptive modifications of spinning and blocking behavior in spin-then-block mutual exclusion include limiting spinning time to no more than the duration of a context switch. Also, the frequency of spinning versus blocking is limited to a desired amount based on the success rate of recent spin attempts. As an alternative, spinning is bypassed if spinning is unlikely to be successful because the owner is not progressing toward releasing the shared resource, as might occur if the owner is blocked or spinning itself. In another aspect, the duration of spinning is generally limited, but longer spinning is permitted if no other threads are ready to utilize the processor. In another aspect, if the owner of a shared resource is ready to be executed, a thread attempting to acquire ownership performs a “directed yield” of the remainder of its processing quantum to the other thread, and execution of the acquiring thread is suspended.

Abstract: Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2T threads. A particular register is accessed in a register bank that has 2(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Abstract: A method of address-level log-based synchronization comprises a thread attempting to acquire a lock on an object. If its lock attempt fails, a thread logs, at a synchronization log, data access operations directed at the shared data object, and waits for a notification from the lock-owning thread indicating whether the logged operations succeeded. If its lock attempt succeeds, the lock-owning thread performs data access operations on the shared data object, and arbitrates among requests logged by other threads in the synchronization log, applying the modifications logged in the requests that do not conflict with other modification operations, and rejecting the requests that conflict. The master sends a success notification to the logging threads whose requests were accepted, and a failure notification to the logging threads whose requests were rejected.

Abstract: Provided is a method and apparatus for an adaptive context switching for a fast block input/output. The adaptive context switching method may include: requesting, by a process, an input/output device to perform an input/output of data; comparing a Central Processing Unit (CPU) effectiveness based on whether the context switching is performed; and performing the input/output through the context switching to a driver context of the input/output device, or directly performing, by the process, the input/output based on a comparison result of the CPU effectiveness.

Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.

Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, which is an Intel or similar Complex Instruction Set Computer architecture, comprising selecting a first operating system to have a relatively high priority (the realtime operating system, such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.

Abstract: A computer system dynamically scales back latch requests for system resources. Tasks seeking access to system resources each dynamically determine the probability that the task will gain access to the latch relating to a given system resource. Where the task estimates that its probability is below a defined threshold, the task will suspend itself for a defined sleep time. The task dynamically adjusts the length of the sleep time based on the number of times the task enters the suspended state and on the relative changes in the estimated probability that the task will gain access to the resource.

Abstract: A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution fairness between pairs of potentially executing threads. A switch enabler determines forward progress of each executing thread. The resulting indicators from the thread prioritizer and switch enabler may aid in the determination of whether or not to switch a particular potentially executing thread into execution resources.

Abstract: Application states may be stored and retrieved using policies that define various contexts in which the application is used. The application states may define configurations or uses of the application, including connections to and interactions with other applications. Applications that are virtualized may have state that is defined within a usage context and multiple states or configurations may be stored and recalled based on the usage context. Policies may define the context and what parameters are to be saved, and may be applied when applications are operated in a virtualized manner.

Abstract: In an application in which context switching often occurs such as in a real time OS, it is possible to significantly reduce the overhead caused by the context switching. The OS issues a Swap instruction and a context switch starts. The Swap instruction is issued together with a thread (i.e., context) ID to be replaced, to a thread control unit (9). The thread ID is used to uniquely identify threads stored in a context cache (8). The thread control unit (9) saves data from a register file (1) to the context cache (8) via a context-dedicated bus (12) and transmits data of a new thread from the context cache (8) to the register file (1). According to the thread ID received, the thread control unit (9) automatically interchanges the necessary number of data in the register file (1) and the data in the context cache (8).

Abstract: A disk drive is described which executes distributed computing tasks including a CPU and associated memory. The communication interface with the host computer is modified to allow the host computer to send executable code for a task to the drive and to allow the drive to communicate the results and status information about the task to the host computer. In a preferred embodiment the disk drive has a task control program, task program code, task data and status information for the distributed task. In alternative embodiments, the disk drive can communicate with other similar disk drives in the bus to provide the results of computation to the other processors. The RAM memory, and mass storage are intimately connected through the associated hard disk controller such that the exact location of the required data and program instructions are known.

Abstract: In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted.

Abstract: A profiler may analyze processes being run by a processor. The profiler may include logic to periodically sample a value of an instruction pointer that indicates an instruction in the first process that is currently being executed by the processor and logic to update profile data based on the sampled value. The profiler may additionally include logic to determine, in response to a context switch that includes the operating system switching the active process from the first process to another of the plurality of processes, whether the first process executes for greater than a first length of time; logic to stop operation of the profiler when the first process executes for greater than the first length of time; and logic to clear the profile data when the first process fails to execute for greater than the first length of time.

Abstract: Embodiments of the present invention are directed to a communication system that provides various automated operations, including linking applications and metadata across computational devices, using a stimulus to automatically find and launch associative and/or contextual materials and/or information required to conduct a work session without manually having to locate and launch each of these materials and/or information, and, by monitoring user behavior, creating and maintaining tokens defining the state of an instance of a workflow for later workflow resumption.

Abstract: A real-time operating system (RTOS) for use with minimal-memory controllers has a kernel for managing task execution, including context switching, a plurality of defined tasks, individual ones of the tasks having subroutines callable in nested levels for accomplishing tasks. In the RTOS context switching is constrained to occur only at task level, and cannot occur at any lower sub-routine level. This system can operate with a single call . . . return stack, saving memory requirement. The single stack can be implemented as either a general-purpose stack or as a hardware call . . . return stack. In other embodiments novel methods are taught for generating return addresses, and for using timing functions in a RTOS.

Abstract: A method and system for automated error handling in system management flows by enhancing workflow engines by an error handling component and by adding a supportive error handling layer to invoked system management tasks which serves as the counterpart to the workflow engine's error handling component. The additional functionality of the task-provided error handling layer is accessible for the workflow engine via extended Web services interfaces. The workflow engine's error handling component and the task-provided error handling layer allow for the definition of a standard protocol between the workflow engine and invoked tasks for automated error handling. Furthermore, an interface and method of communication between the enhanced workflow engine and an external error resolving device (such as an expert system) is defined with the purpose of using the external error resolving device for automatic error recovery.

Abstract: A multithreaded computer system of the present invention includes a plurality of processor elements (PEs) and a parallel processor controller which switches threads in each PE. The parallel processor controller includes a plurality of execution order registers which hold, for each processor element, an execution order of threads to be executed; a plurality of counters which count an execution time for a thread that is being executed by each processor element and generate a timeout signal when the counted time reaches a limit assigned to the thread; and a thread execution scheduler which switches the thread that is being executed to the thread to be executed by each processor element based on an execution order held in the execution order register and the timeout signal.

Abstract: Systems and methods for redundancy management in fault tolerant computing are provided. The systems and methods generally relate to enabling the use of non-custom, off-the-shelf components and tools to provide redundant fault tolerant computing. The various embodiments described herein, generally speaking, use a decrementer register in a general purpose processor for synchronizing identical operations across redundant general purpose processors, execute redundancy management services in the kernels of commercial off-the-shelf real-time operating systems (RTOS) running on the general purpose processors, and use soft coded tables to schedule operations and assign redundancy management parameters across the general purpose processors.