Abstract: In one aspect, a method of fabricating a nanowire FET device includes the following steps. A layer of III-V semiconductor material is formed on an SOI layer of an SOI wafer. Fins are etched into the III-V material and SOI layer. One or more dummy gates are formed over a portion of the fins that serves as a channel region of the device. A gap filler material is deposited onto the wafer. The dummy gates are removed selective to the gap filler material, forming trenches in the gap filler material. The SOI layer is removed from portions of the fins within the trenches thereby forming suspended nanowire channels in the channel regions of the device. The trenches are filled with at least one gate material to form one or more replacement gates surrounding the nanowire channels in a gate-all-around configuration.

Abstract: Disclosed herein are a branched nanowire having parasitic nanowires grown at a surface of the branched nanowire, and a method for fabricating the same. The branched nanowire may be fabricated in a fractal form and seeds of the parasitic nanowires may be formed by thermal energy irradiation and/or a wet-etching process. The branched nanowire may effectively be used in a wide variety of applications such as, for example, sensors, photodetectors, light emitting elements, light receiving elements, and the like.

Abstract: Nanowires useful as heterogeneous catalysts are provided. The nanowire catalysts are useful in a variety of catalytic reactions, for example, the oxidative coupling of methane to C2 hydrocarbons. Related methods for use and manufacture of the same are also disclosed.

Abstract: Transparent conductive films comprising silver nanowires dispersed in polyvinyl alcohol or gelatin can be prepared by coating from aqueous solvent using common aqueous solvent coating techniques. These films have good transparency, conductivity, and stability. Coating on a flexible support allows the manufacture of flexible conductive materials.

Abstract: This invention provides novel nanofiber enhanced surface area substrates and structures comprising such substrates for use in various medical devices, as well as methods and uses for such substrates and medical devices. In one particular embodiment, methods for enhancing cellular functions on a surface of a medical device implant are disclosed which generally comprise providing a medical device implant comprising a plurality of nanofibers (e.g., nanowires) thereon and exposing the medical device implant to cells such as osteoblasts.

Abstract: A magnetic memory according to an embodiment includes: a magnetic nanowire; first insulating layers provided on a first surface of the magnetic nanowire, each of the first insulating layers having a first and second end faces, a thickness of the first insulating layer over the first end face being thicker than a thickness of the first insulating layer over the second end face; first electrodes on surfaces of the first insulating layers opposite to the first surface; second insulating layers on the second surface of the magnetic nanowire, each of the second insulating layers having a third and fourth end faces, a thickness of the second insulating layer over the third surface being thicker than a thickness of the second insulating layer over the fourth end face; and second electrodes on surfaces of the second insulating layers.

Abstract: A method of generating light is disclosed. The method comprises: directing an optical pulse to a semiconductor optical amplifier being at a temperature above 0° C. The optical pulse is preferably characterized by a wavelength within an emission spectrum of the semiconductor optical amplifier and by a pulse area selected to induce Rabi oscillations in the semiconductor optical amplifier, and to emit light at a frequency of at least 1 THz.

Abstract: A multi junction photovoltaic cell for converting light into electrical energy, comprising a substrate (3) having a surface (31), wherein a region (4) at the surface (31) of the substrate (3) is doped such that a first p-n junction is formed in the substrate (3). The photovoltaic cell has a nanowire (2) that is arranged on the surface (31) of the substrate (3) at a position where the doped region (4) is located in the substrate (3), such that a second p-n junction is formed at the nanowire (2) and in series connection with the first p-n junction.

Abstract: Methods of metal assisted chemical etching III-V semiconductors are provided. The methods can include providing an electrically conductive film pattern disposed on a semiconductor substrate comprising a III-V semiconductor. At least a portion of the III-V semiconductor immediately below the conductive film pattern may be selectively removed by immersing the electrically conductive film pattern and the semiconductor substrate into an etchant solution comprising an acid and an oxidizing agent having an oxidation potential less than an oxidation potential of hydrogen peroxide. Such methods can form high aspect ratio semiconductor nanostructures.

Abstract: A pressing force sensor that includes a flat membrane piezoelectric element and a support. The flat membrane piezoelectric element includes a piezoelectric sheet having a piezoelectric constant d14. A first electrode is formed on a first main surface of the piezoelectric sheet and a second electrode is formed on a second main surface thereof. Long directions of the first electrode and the second electrode and a uniaxial stretching direction of the piezoelectric sheet form an angle of 45°. An opening portion having an elliptical section is formed on the support. The flat membrane piezoelectric element abuts the opening portion of the support. The support and the flat membrane piezoelectric element are disposed such that the opening portion is included within an area of the second electrode.

Abstract: The present invention relates to hierarchical structured nanotubes, to a method for preparing the same and to an application for the same, wherein the nanotubes include a plurality of connecting nanotubes for constituting a three-dimensional multi-dendrite morphology; and the method includes the following steps: (A) providing a polymer template including a plurality of organic nanowires; (B) forming an inorganic layer on the surface of the organic nanowires in the polymer template; and (C) performing a heat treatment on the polymer template having the inorganic layer on the surface so that partial atoms of the organic nanowires enter the inorganic layer.

Abstract: A composite for providing electromagnetic shielding including a plurality of nanotubes; and a plurality of elongate metallic nanostructures.

Abstract: A method of manufacturing an interconnection of an embodiment includes: forming a via which penetrates an interlayer insulation film on a substrate; forming an underlying film in the via; removing the underlying film on a bottom part of the via; forming a catalyst metal inactivation film on the underlying film; removing the inactivation film on the bottom part of the via; forming a catalyst metal film on the bottom part of the via on which the inactivation film is removed; performing a first plasma treatment and a second plasma treatment using a gas not containing carbon on a member in which the catalyst metal film is formed; forming a graphite layer on the catalyst film after the first and second plasma treatment processes; and causing a growth of a carbon nanotube from the catalyst film on which the graphite layer is formed.

Abstract: Optoelectronic device including light-emitting means in the form of nanowires (2, 3) having a core/shell-type structure and produced on a substrate (11), in which said nanowires comprise an active zone (22, 32) including at least two types of quantum wells associated with different emission wavelengths and distributed among at least two different regions (220, 221; 320, 321) of said active zone, in which the device also includes a first electrical contact zone (15) on the substrate and a second electrical contact zone (16) on the emitting means, in which said second zone is arranged so that, as the emitting means are distributed according to at least two groups, the electrical contact is achieved for each of said at least two groups at a different region of the active zone, and the electrical power supply is controlled so as to obtain the emission of a multi-wavelength light.

Abstract: Disclosed herein is a semiconducting nanoparticle comprising a one-dimensional semiconducting nanoparticle having a first end and a second end; where the second end is opposed to the first end; and two first endcaps, one of which contacts the first end and the other of which contacts the second end respectively of the one-dimensional semiconducting nanoparticle; where the first endcap that contacts the first end comprises a first semiconductor and where the first endcap extends from the first end of the one-dimensional semiconducting nanoparticle to form a first nanocrystal heterojunction; where the first endcap that contacts the second end comprises a second semiconductor; where the first endcap extends from the second end of the one-dimensional semiconducting nanoparticle to form a second nanocrystal heterojunction; and where the first semiconductor and the second semiconductor are chemically different from each other.

Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, he selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

Abstract: Embodiments of the invention provide a method for direct heteroepitaxial growth of vertical III-V semiconductor nanowires on a silicon substrate. The silicon substrate is etched to substantially completely remove native oxide. It is promptly placed in a reaction chamber. The substrate is heated and maintained at a growth temperature. Group III-V precursors are flowed for a growth time. Preferred embodiment vertical Group III-V nanowires on silicon have a core-shell structure, which provides a radial homojunction or heterojunction. A doped nanowire core is surrounded by a shell with complementary doping. Such can provide high optical absorption due to the long optical path in the axial direction of the vertical nanowires, while reducing considerably the distance over which carriers must diffuse before being collected in the radial direction. Alloy composition can also be varied. Radial and axial homojunctions and heterojunctions can be realized. Embodiments provide for flexible Group III-V nanowire structures.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

Abstract: A mechanism is provided for storing multiple bits in a domain wall nanowire magnetic junction device. The multiple bits are encoded based on a resistance of the domain wall nanowire magnetic junction device using a single domain wall. The single domain wall is shifted to change the resistance of the domain wall nanowire magnetic junction device to encode a selected bit. The resistance is checked to ensure that it corresponds to a preselected resistance for the selected bit. Responsive to the resistance corresponding to the preselected resistance for the selected bit, the selected bit is stored. Responsive to the resistance not being the preselected resistance for the selected bit, the single domain wall is shifted until the resistance corresponds to the preselected resistance.

Abstract: A method for forming porous metal structures and the resulting structure may include forming a metal structure above a substrate. A masking layer may be formed above the metal structure, and then etched using a reactive ion etching process with a mask etchant and a metal etchant. Etching the masking layer may result in the formation of a plurality of pores in the metal structure. In some embodiments, the metal structure may include a first end region, a second end region, and an intermediate region. Before etching the masking layer, a protective layer may be formed above the first end region and the second end region, so that the plurality of pores is contained within the intermediate region. In some embodiments, the intermediate metal region may be a nanostructure such as a nanowire.

Abstract: A method for creating a nanostructure according to one embodiment includes depositing material in a template for forming an array of nanocables; removing only a portion of the template such that the template forms an insulating layer between the nanocables; and forming at least one layer over the nanocables. A nanostructure according to one embodiment includes a nanocable having a roughened outer surface and a solid core. A nanostructure according to one embodiment includes an array of nanocables each having a roughened outer surface and a solid core, the roughened outer surface including reflective cavities; and at least one layer formed over the roughened outer surfaces of the nanocables, the at least one layer creating a photovoltaically active p-n junction. Additional systems and methods are also presented.

Abstract: Claimed methods reduce leakage currents in transparent conductive films comprising conductive nanostructures without substantially impairing the films' optical properties or physical integrity. Imposition of electrical stimuli to separate conductive regions leads to reduced conductivity of the intervening lesser conductive regions.

Abstract: A semiconductor device, such as an LED, includes a plurality of first conductivity type semiconductor nanowire cores located over a support, a continuous second conductivity type semiconductor layer extending over and around the cores, a plurality of interstitial voids located in the second conductivity type semiconductor layer and extending between the cores, and first electrode layer that contacts the second conductivity type semiconductor layer and extends into the interstitial voids.

Abstract: The present application relates to a method for making a carbon nanotube field emitter. A carbon nanotube film is drawn from the carbon nanotube array by a drawing tool. The carbon nanotube film includes a triangle region. A portion of the carbon nanotube film closed to the drawing tool is treated into a carbon nanotube wire including a vertex of the triangle region. The triangle region is cut from the carbon nanotube film by a laser beam along a cutting line. A distance between the vertex of the triangle region and the cutting line can be in a range from about 10 microns to about 5 millimeters.

Abstract: A negative active material and a lithium battery including the negative active material. The negative active material includes a carbonaceous substrate with a plurality of recessed portions at its surface; and a silicon-based nanowire placed in each of the recessed portions. The negative active material provides the silicon-based nanowires with separate places to control volumetric expansion of the silicon-based nanowires, and thus, a lithium battery including the negative active material has improved efficiency and lifetime.

Abstract: A method of fabricating an electronic device includes the following steps. A SOI wafer is provided having a SOI layer over a BOX. At least one first/second set of nanowires and pads are patterned in the SOI layer. A conformal gate dielectric layer is selectively formed surrounding a portion of each of the first set of nanowires that serves as a channel region of a transistor device. A first metal gate stack is formed on the conformal gate dielectric layer surrounding the portion of each of the first set of nanowires that serves as the channel region of the transistor device in a gate all around configuration. A second metal gate stack is formed surrounding a portion of each of the second set of nanowires that serves as a channel region of a diode device in a gate all around configuration.

Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.

Abstract: A top-down method of fabricating vertically aligned Group III-V micro- and nanowires uses a two-step etch process that adds a selective anisotropic wet etch after an initial plasma etch to remove the dry etch damage while enabling micro/nanowires with straight and smooth faceted sidewalls and controllable diameters independent of pitch. The method enables the fabrication of nanowire lasers, LEDs, and solar cells.

Abstract: A method of arranging a diamagnetic rod includes levitating a diamagnetic rod above a contact line at which a first magnet contacts a second magnet, the first magnet and the second magnet having diametric magnetization in a direction perpendicular to the contact line.

Abstract: A method for forming a nanostructure according to one embodiment includes creating a hole in an insulating layer positioned over an electrically conductive layer; and forming a nanocable in the hole such that the nanocable extends through the hole in the insulating layer and protrudes therefrom, the nanocable being in communication with the electrically conductive layer. Additional systems and methods are also presented.

Abstract: An embodiment relates to a method of manufacturing a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.

Abstract: A light-emitting device epitaxially-grown on a GaAs substrate which contains an active region composed of AlxGa1-xAs alloy or of related superlattices of this materials system is disclosed. This active region either includes tensile-strained GaP-rich insertions aimed to increase the forbidden gap of the active region targeting the bright red, orange, yellow, or green spectral ranges, or is confined by regions with GaP-rich insertions aimed to increase the barrier height for electrons in the conduction band preventing the leakage of the nonequilibrium carriers outside of the light-generation region.

Abstract: Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

Abstract: A method of bonding a metal to a substrate is disclosed herein. The method involves forming a nano-brush on a surface of the substrate, where the nano-brush includes a plurality of nano-wires extending above the substrate surface. In a molten state, the metal is introduced onto the substrate surface, and the metal surrounds the nano-wires. Upon cooling, the metal surrounding the nano-wires solidifies, and during the solidifying, at least a mechanical interlock is formed between the metal and the substrate.

Abstract: A method of fabricating quantum confinements is provided. The method includes depositing, using a deposition apparatus, a material layer on a substrate, where the depositing includes irradiating the layer, before a cycle, during a cycle, and/or after a cycle of the deposition to alter nucleation of quantum confinements in the material layer to control a size and/or a shape of the quantum confinements. The quantum confinements can include quantum wells, nanowires, or quantum dots. The irradiation can be in-situ or ex-situ with respect to the deposition apparatus. The irradiation can include irradiation by photons, electrons, or ions. The deposition is can include atomic layer deposition, chemical vapor deposition, MOCVD, molecular beam epitaxy, evaporation, sputtering, or pulsed-laser deposition.

Abstract: The present invention provides a metal nanowire-containing composition containing at a least metal nanowire and a heterocyclic compound having an interaction potential of less than ?1 mV.

Abstract: A method of preparing a metal nanorod. The method includes seeding a metal nanoparticle within the lumen of a nanotube, and growing a metal nanorod from the seeded metal nanoparticle to form a metal nanorod-nanotube composite. In some cases, the nanotube includes metal binding ligands attached to the inner surface. Growing of the metal nanorod includes incubating the seeded nanotube in a solution that includes: a metal source for the metal in the metal nanorod, the metal source including an ion of the metal; a coordinating ligand that forms a stable complex with the metal ion; a reducing agent for reducing the metal ion, and a capping agent that stabilizes atomic monomers of the metal. Compositions derived from the method are also provided.

Abstract: The invention concerns the production of segmented nanowires and components having said segmented nanowires. For the production of the nanowire structural element, a template based process is used preferably, wherein the electrochemical deposition of the nanowires in nanopores is carried out. In this manner, numerous nanowires are created in the template foil. For the electrochemical deposition of the nanowires, a reversed pulse procedure with an alternating sequence consisting of cathodic deposition pulses and anodic counter-pulses is carried out. By this means, segmented nanowires can be produced.

Abstract: Various embodiments of the present invention are direct to nanoscale, reconfigurable, memristor devices. In one aspect, a memristor device comprises an electrode (301,303) and an alloy electrode (502,602). The device also includes an active region (510,610) sandwiched between the electrode and the alloy electrode. The alloy electrode forms dopants in a sub-region of the active region adjacent to the alloy electrode. The active region can be operated by selectively positioning the dopants within the active region to control the flow of charge carriers between the electrode and the alloy electrode.

Abstract: Methods of producing nanowires and resulting nanowires are described. In one implementation, a method of producing nanowires includes energizing (i) a metal-containing reagent; (ii) a templating agent; (iii) a reducing agent; and (iv) a seed-promoting agent (SPA) in a reaction medium and under conditions of a first temperature for at least a portion of a first duration, followed by a second temperature for at least a portion of a second duration, and the second temperature is different from the first temperature.

Abstract: Nanostructures and photovoltaic structures are disclosed. A nanostructure according to one embodiment includes an array of nanocables extending from a substrate, the nanocables in the array being characterized as having a spacing and surface texture defined by inner surfaces of voids of a template; an electrically insulating layer extending along the substrate; and at least one layer overlaying the nanocables. A nanostructure according to another embodiment includes a substrate; a portion of a template extending along the substrate, the template being electrically insulative; an array of nanocables extending from the template, portions of the nanocables protruding from the template being characterized as having a spacing, shape, and surface texture defined by previously-present inner surface of voids of the template; and at least one layer overlaying the nanocables.

Abstract: Provided are methods for producing nanostructures and nanostructures obtained thereby. The methods include heating a certain point of a substrate dipped into a precursor solution of the nanostructures so that the nanostructures are grown in a liquid phase environment without evaporation of the precursor solution. The methods show excellent cost-effectiveness because of the lack of a need for precursor evaporation at high temperature. In addition, unlike the vapor-liquid-solid (VLS) process performed in a vapor phase, the method includes growing nanostructures in a liquid phase environment, and thus provides excellent safety and eco-friendly characteristics as well as cost-effectiveness. Further, the method includes locally heating a substrate dipped into a precursor solution merely at a point where the nanostructures are to be grown, so that the nanostructures are grown directly at a desired point of the substrate. Therefore, it is possible to grow and produce nanostructures directly in a device.

Abstract: A transparent conductor including a conductive layer coated on a substrate is described. More specifically, the conductive layer comprises a network of nanowires which may be embedded in a matrix. The conductive layer is optically transparent and flexible. It can be coated or laminated onto a variety of substrates, including flexible and rigid substrates.

Abstract: An ultra-efficient device for converting light into electricity has a dielectric medium for input light propagation, a metallic medium having an array of surface-plasmon-polariton (SPP) resonator cavities formed at nano-scale and distributed in the metallic medium below the dielectric-metal interface, each nano-scale resonator cavity having a hollow interior as a metal cathode in which a metal anode is disposed, another metallic medium electrically coupled to the anode, and another dielectric medium insulating the anode medium from the cathode medium. In each cavity, the cathode is shaped, dimensioned and spaced from the anode so that standing waves of SPP excitations generated by the input light cause quantum field emission of electrons to be rectified as an electrical output. The SPP resonator cavities may be formed in a plurality of diametral sizes corresponding to component light wavelengths to allow full spectrum energy conversion of broadband light input.

Abstract: The present invention relates to a metal nanobelt and a method of manufacturing the same, and a conductive ink composition and a conductive film including the same. The metal nanobelt can be easily manufactured at a normal temperature and pressure without requiring the application of high temperature and pressure, and also can be used to form a conductive film or conductive pattern that exhibits excellent conductivity if the conductive ink composition including the same is printed onto a substrate before a heat treatment or a drying process is carried out at low temperature. Therefore, the metal nanobelt and the conductive ink composition may be applied very appropriately for the formation of conductive patterns or conductive films for semiconductor devices, displays, solar cells in environments requiring low temperature heating. The metal nanobelt has a length of 500 nm or more, a length/width ratio of 10 or more, and a width/thickness ratio of 3 or more.

Abstract: A biomolecule immobilization substrate comprising a titania nanotube is provided. Stable undercoordinated titanium sites on the surface of titanium dioxide nanotubes provide for the binding of biomolecules in multiple layers and aggregates. Corresponding methods of immobilizing and storing biomolecules are provided. Enzymatic or other biological activities of titania nanotube bound biomolecules can be preserved or enhanced.

Abstract: A method for making silicon nanorods is provided. In accordance with the method, Au nanocrystals are reacted with a silane in a liquid medium to form nanorods, wherein each of said nanorods has an average diameter within the range of about 1.2 nm to about 10 nm and has a length within the range of about 1 nm to about 100 nm.

Abstract: A resistive device includes at least one strain gauge (12, 14) comprising silicon nanowires, a power supply (16) that has at least one current source (22, 24) able to generate a current (Ibias) for biasing the strain gauge; and acquisition means (18) able to deliver a measurement signal which can be used to determine the variation in the electrical resistance of the gauge. The power supply includes a chopper (26) allowing the biasing current generated by each current source to flow through each gauge only during a fraction of an operating cycle of the device.