Abstract: Amongst the candidates for very high efficiency solid state light sources and full solar spectrum solar cells are devices based upon InGaN nanowires. Additionally these nanowires typically require heterostructures, quantum dots, etc which all place requirements for these structures to be grown with relatively few defects and in a controllable reproducible manner. Additionally flexibility according to the device design requires that the nanowire at the substrate may be either InN or GaN. According to the invention a method of growing relatively defect free nanowires and associated structures for group IIIA-nitrides is presented without the requirement for foreign metal catalysts and overcoming the non-uniform growth of prior art non-catalyst growth techniques. According to other embodiments of the invention self-organizing dot-within-a-dot nanowire and dot-within-a-dot-within-a-well nanowire structures are presented.

Abstract: A method is provided for eliminating catalyst residues that are present on the surface of solid structures. The solid structures are made from a first material and are obtained by catalytic growth from a substrate. The method includes the following steps: catalytically growing, from the catalyst residues, solid structures made from a second material; and selectively eliminating the solid structures made from the second material, thereby eliminating the catalyst residues.

Abstract: The device according to the invention comprises a nanostructured LED with a first group of nanowires protruding from a first area of a substrate and a contacting means in a second area of the substrate. Each nanowire of the first group of nanowires comprises a p-i-n junction and a top portion of each nanowire or at least one selection of nanowires is covered with a light-reflecting contact layer. The contacting means of the second area is in electrical contact with the bottom of the nanowires, the light-reflecting contact layer being in electrical contact with the contacting means of the second area via the p-i-n junction. Thus when a voltage is applied between the contacting means of the second area and the light-reflecting contact layer, light is generated within the nanowire. On top of the light-reflecting contact layer, a first group of contact pads for flip-chip bonding can be provided, distributed and separated to equalize the voltage across the layer to reduce the average serial resistance.

Abstract: The disclosure relates generally to nano-filters and methods of forming same, and methods of filtration. The nano-filter includes a substrate and at least one nanowire structure located between an inlet and an outlet. The nanowire structure may include a plurality of vertically stacked horizontal nanowires.

Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.

Abstract: A phase-controllable magnetic mirror, system, and method of use are described. The mirror has a ground plate with a surface, a dielectric layer disposed over the surface and having a plurality of electrically-isolated dielectric sections, the dielectric sections defining a plurality of unit cells. The unit cells change their dielectric constant based on an applied voltage such that cells incident photons having a first phase and re-emit photons having a second, different phase. A method of use includes aberrating a wave front and re-emitting, with a phase-controllable magnetic mirror, a second wave front having a different wave front contour. A system including the phase-controllable magnetic mirror has a processor configured to receive aberration measurements and provide selected bias voltages or illumination of the unit cells to make the re-emitted wave front have less aberration than the incident wave front.

Abstract: A shift register type magnetic memory according to an embodiment includes: a magnetic nanowire; a magnetic material chain provided in close vicinity to the magnetic nanowire, the magnetic material chain including a plurality of disk-shaped ferromagnetic films arranged along a direction in which the magnetic nanowire extends; a magnetization rotation drive unit configured to rotate and drive magnetization of the plurality of ferromagnetic films; a writing unit configured to write magnetic information into the magnetic nanowire; and a reading unit configured to read magnetic information from the magnetic nanowire.

Abstract: Provided is a silicon-wafer-based germanium semiconductor photodetector configured to be able to provide properties of high gain, high sensitivity, and high speed, at a relatively low voltage. A germanium-based carrier multiplication layer (e.g., a single germanium layer or a germanium and silicon superlattice layer) may be provided on a silicon wafer, and a germanium charge layer may be provided thereon, a germanium absorption layer may be provided on the charge layer, and a polysilicon second contact layer may be provided on the absorption layer. The absorption layer may be configured to include germanium quantum dots or wires.

Abstract: A method for fabricating one-dimensional metallic nanostructures comprises steps: sputtering a conductive film on a flexible substrate to form a conductive substrate; placing the conductive substrate in an electrolytic solution, and undertaking electrochemical deposition to form one-dimensional metallic nanostructures corresponding to the conductive film on the conductive substrate. The method fabricates high-surface-area one-dimensional metallic nanostructures on a flexible substrate, exempted from the high price of the photolithographic method, the complicated process of the hard template method, the varied characteristic and non-uniform coating of the seed-mediated growth method.

Abstract: A nanowire FET device includes a SOI wafer having a SOI layer over a BOX, and a plurality of nanowires and pads patterned in the SOI layer, wherein the nanowires are suspended over the BOX; an interfacial oxide surrounding each of the nanowires; and at least one gate stack surrounding each of the nanowires, the gate stack having (i) a conformal gate dielectric present on the interfacial oxide (ii) a conformal first gate material on the conformal gate dielectric (iii) a work function setting material on the conformal first gate material, and (iv) a second gate material on the work function setting material. A volume of the conformal first gate material and/or a volume of the work function setting material in the gate stack are/is proportional to a pitch of the nanowires.

Abstract: Disclosed are synthetic nanocarrier methods, and related compositions, comprising B cell and/or MHC Class II-restricted epitopes and immunosuppressants in order to generate tolerogenic immune responses, such as the generation of antigen-specific regulatory B cells.

Abstract: Disclosed herein is a structure having a spatially organized polymer nanostructured thin film and a metal coating on the film. The thin film is made by directing a monomer vapor or pyrolyzed monomer vapor towards a substrate at an angle other than perpendicular to the substrate, and polymerizing the monomer or pyrolyzed monomer on the substrate.

Abstract: A vapor-grown graphite fibers (VGGF) composition and a mixture containing the VGGF composition and applications thereof are provided. The VGGF composition includes a carbon ingredient containing a carbon content of at least 99.9 wt %. The carbon ingredient has a graphitization degree of at least 75%, and the carbon ingredient includes non-fibrous carbon and fibrous VGGF, wherein an area ratio of the non-fibrous carbon to the fibrous VGGF measured by a scanning electron microscopy (SEM) is about equal to or smaller than 5%. The fibrous VGGF include graphite fibers having a 3-D linkage structure, wherein the content of the graphite fibers having the 3-D linkage structure in the fibrous VGGF measured by the SEM is about between 5 area % and 50 area %. The VGGF composition and its mixture are applied to the composite materials, thereby promoting the strength, electric and thermal conductivity of the composite materials.

Abstract: Techniques for increasing effective device width of a nanowire FET device are provided. In one aspect, a method of fabricating a FET device is provided. The method includes the following steps. A SOI wafer is provided having an SOI layer over a BOX. Nanowire cores and pads are etched in the SOI layer in a ladder-like configuration. The nanowire cores are suspended over the BOX. Epitaxial shells are formed surrounding each of the nanowire cores. A gate stack is formed that surrounds at least a portion of each of the nanowire cores/epitaxial shells, wherein the portions of the nanowire cores/epitaxial shells surrounded by the gate stack serve as channels of the device, and wherein the pads and portions of the nanowire cores/epitaxial shells that extend out from the gate stack serve as source and drain regions of the device.

Abstract: A nanowire sensor having a nanowire in a network structure includes: source and drain electrodes formed over a substrate; a nanowire formed between the source and drain electrodes and having a network structure in which patterns of intersections are repeated; and a detection material fixed to the nanowire and selectively reacting with a target material introduced from outside.

Abstract: Provided herein are methods for dehydrating single-walled metal oxide nanotubes by heating the SWNT under vacuum at 250-300° C.; methods of dehydroxylating SWNT, comprising heating the SWNT under vacuum at 300-340° C., and methods for maximizing the pore volume of a SWNT, comprising heating the SWNT at 300° C. under vacuum to partially dehydroxylate and dehydrate the SWNT; methods of modifying the inner surface of a single walled aluminosilicate nanotube (SWNT), comprising dehydration or dehydration and dehydroxylation, followed by reacting the SWNT with a derivative under anhydrous conditions to produce a SWNT that is derivatized on its inner surface. The invention also includes single-walled nanotubes produced by the methods of the invention.

Abstract: An incandescent light source display includes a substrate, a plurality of first electrode down-leads, a plurality of second electrode down-leads and a plurality of heating units. The plurality of first electrode down-leads are located on the substrate in parallel to each other and the plurality of second electrode down-leads are located on the substrate in parallel to each other. The first electrode down-leads cross the second electrode down-leads and corporately define a grid having a plurality of cells. Each of the incandescent light sources is located in correspondence with each of the cells. Each incandescent light source includes a first electrode, a second electrode and an incandescent element. The incandescent element includes a carbon nanotube structure.

Abstract: Disclosed is an electrically conductive feature on a substrate, and methods and compositions for forming the same, wherein the electrically conductive feature includes metallic anisotropic nanostructures and is formed by injetting onto the substrate a coating solution containing the conductive anisotropic nanostructures.

Abstract: In one aspect, a FET device is provided. The FET device includes a substrate; a semiconductor material on the substrate; at least one gate on the substrate surrounding a portion of the semiconductor material that serves as a channel region of the device, wherein portions of the semiconductor material extending out from the gate serve as source and drain regions of the device, and wherein the source and drain regions of the device are displaced from the substrate; a planarizing dielectric on the device covering the gate and the semiconductor material; and contacts which extend through the planarizing dielectric and surround the source and drain regions of the device.

Abstract: The disclosure provides a thermoelectric conversion structure and its use in heat dissipation device. The thermoelectric conversion structure includes a thermoelectric element, a first electrode and an electrically conductive heat-blocking layer. The thermoelectric element includes a first end and a second end opposite to each other. The first electrode is located at the first end of the thermoelectric element. The electrically conductive heat-blocking layer is between the thermoelectric element and the first electrode.

Abstract: The method utilizes a conducting trench base with non-conducting trench walls to corral charged particles precisely into the trenches. The nanoparticles are close packed in the channels and highly ordered. This approach utilizes the charge on the particles to selectively deposit them within the trenches, as all nanoparticles in solution can be charged, and this can be extended to any nanoparticle system beyond gold. Also, this method results in the layer-by-layer growth of the gold nanoparticles. Therefore the depth of the nanoparticle layers within the trenches is controllable. This allows the possibility of heterolayered structures of different nanoparticle layers. Further this method ensures that assembly occurs to fill the void space available provided the back-contacting electrode is more conducting than the trench walls. This allows nanoparticle assemblies to be corralled into any lithographically defined shape, which makes this approach highly adaptable to a range of applications.

Abstract: A composite laminate for use on an external part of an aerospace vehicle has improved ultraviolet resistance and resistance to microcracking from thermal cycling. The laminate comprises a nanoreinforcement film, a support veil, and a composite layer. The laminate also can have a lightning strike protection layer and an external paint and primer. The nanoreinforcement film can comprise carbon nanomaterial and a polymer resin, and the composite layer has one or more layers of a reinforcement and a polymer resin. The carbon nanomaterial can be carbon nanofibers, and the nanoreinforcement film can have an areal weight of less than about 100 g/m2. The carbon nanomaterial can also comprise carbon nanofibers and carbon nanotubes.

Abstract: A device and method for forming nanostructures includes providing a monocrystalline semiconductor layer on a flexible substrate and stressing the substrate in accordance with a crystal cleave plane to initiate cracks in the semiconductor layer. The cracks are propagated on the crystal cleave plane through the semiconductor layer where the cracks are spaced by an intercrack distance as determined by applying a particular strain. The strain is released to provide parallel structures on the flexible substrate.

Abstract: In one embodiment, a catalyst assembly includes a substrate including a substrate base and a number of substrate hairs extending longitudinally from the substrate base, the substrate base including a metal M, the number of substrate hairs including an oxide of the metal M; and a catalyst film contacting at least a portion of the substrate.

Abstract: Means for reducing an arsenic ion concentration in the solution to the degree of ultra trace amount are provided. Ammonium molybdate is supported by a nanostructure material by mixing the nanostructure material, which is obtained after the nanostructure material such as an alumina reacts with a surfactant, in the solution containing the ammonium molybdate. The nanostructure material supporting an arsenic ion adsorption compound such as ammonium molybdate can selectively adsorb and remove trace of arsenic ion in the solution by a room temperature treatment without a water conditioning such as pH control. In our removal system of arsenic, extra posttreatments are not needed because special pretreatments are not carried out, and special heating equipments are not used. Accordingly, our removal system of arsenic can be constructed at low cost. Furthermore, it can supply an arsenic-free solution by be constructed at multi stages.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A magnetic domain wall shift register memory device includes a nanowire and a magnetic reference layer island disposed on the nanowire, wherein an interface between the nanowire and the magnetic tunnel junction island is a magnetic tunnel junction aligned with a width of the nanowire.

Abstract: A magnetic domain wall shift register memory device includes a nanowire, a plurality of pinning sites disposed along the nanowire and a control line arranged substantially parallel to the nanowire and configured to support a current.

Abstract: A method of fabricating a self-aligning magnetic tunnel junction the method includes patterning a lithographic strip on a second magnetic material deposited on a first magnetic material that is disposed on a substrate, forming a top magnetic strip by etching an exposed portion of the second magnetic material, patterning a nanowire and a magnetic reference layer island over the substrate and forming the nanowire and the magnetic reference layer island by etching an exposed portion of the first magnetic layer and an exposed portion of the top magnetic strip, wherein an interface between the magnetic nanowire and the magnetic reference layer island is an magnetic tunnel junction aligned with a width of the nanowire.

Abstract: A vertically oriented nanometer-wires structure is disclosed. The vertically oriented nanometer-wires structure includes a non-crystalline base and many straight nanometer-wires. The straight nanometer-wires are uniformly distributed on the non-crystalline base, and the angle between each of the straight nanometer-wire and the non-crystalline base is 80-90 degrees. The straight nanometer-wires structure can be widely applied in semiconductor, optoelectronic, biological and energy field. What is worth to be noticed is that the non-crystalline base can be glass, ceramics, synthetic, resin, rubber or even metal foil, and the straight nanometer-wires and the non-crystalline base are still orthogonal to each other.

Abstract: A complimentary metal oxide semiconductor (CMOS) device includes a wafer having a buried oxide (BOX) layer having a first region with a first thickness and a second region with a second thickness, the first thickness is less than the second thickness, a nanowire field effect transistor (FET) arranged on the BOX layer in the first region, the nanowire FET, and a finFET arranged on the BOX layer in the second region.

Abstract: Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to fabricate such devices are also described. One or more embodiments of the present invention are directed at approaches for varying the gate width of a transistor structure comprising a nanowire stack having a distinct number of nanowires. The approaches include rendering a certain number of nanowires inactive (i.e. so that current does not flow through the nanowire), by severing the channel region, burying the source and drain regions, or both. Overall, the gate width of nanowire-based structures having a plurality of nanowires may be varied by rendering a certain number of nanowires inactive, while maintaining other nanowires as active.

Abstract: Metal nanowires, such as silver nanowires coated on a substrate were sintered together to form fused metal nanowire networks that have greatly improved conductivity while maintaining good transparency and low haze. The method of forming such a fused metal nanowire networks are disclosed that involves exposure of metal nanowires to various fusing agents on a short timescale. The resulting sintered network can have a core-shell structure in which metal halide forms the shell. Additionally, effective methods are described for forming patterned structure with areas of sintered metal nanowire network with high conductivity and areas of un-sintered metal nanowires with low conductivity. The corresponding patterned films are also described.

Abstract: A light emitting diode includes a substrate, a first-type semiconductor layer, a nanorod layer and a transparent planar layer. The first-type semiconductor layer is disposed over the substrate. The nanorod layer is formed on the first-type semiconductor layer. The nanorod layer includes a plurality of nanorods and each of the nanorods has a quantum well structure and a second-type semiconductor layer. The quantum well structure is in contact with the first-type semiconductor layer, and the second-type semiconductor layer is formed on the quantum well structure. The transparent planar layer is filled between the nanorods. A surface of the second-type semiconductor layer is exposed out of the transparent planar layer.

Abstract: A light-emitting device includes a first conductive semiconductor layer formed on a substrate, a mask layer formed on the first conductive semiconductor layer and having a plurality of holes, a plurality of vertical light-emitting structures vertically grown on the first conductive semiconductor layer through the plurality of holes, a current diffusion layer surrounding the plurality of vertical light-emitting structures on the first conductive semiconductor layer, and a dielectric reflector filling a space between the plurality of vertical light-emitting structures on the current diffusion layer.

Abstract: Disclosed are p-n zinc (Zn) oxide nanowires and a methods of manufacturing the same. A p-n Zn oxide nanowire includes a p-n junction structure in which phosphorus (P) is on a surface of a Zn oxide nanowire.

Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.

Abstract: The present invention relates to a negative electrode material for a secondary battery and to a method for manufacturing same. The negative electrode material includes a graphite matrix and a plurality of tin-oxide nanorods disposed on the graphite matrix. Thus, when the negative electrode material is used as the negative electrode for a secondary battery, the negative electrode material may provide high initial capacity (1010 mAhg?1) and coulombic efficiency, superior rate capability, and improved electrochemical properties. Further, the method for manufacturing the negative electrode material for a secondary battery includes: a step of activating a surface of graphite; coating tin-oxide nanoparticles onto the activated surface of the graphite so as to form tin-oxide seed-type graphite; and heating the tin-oxide seed-type graphite using heated water in order to grow a plurality of tin-oxide nanorods.

Abstract: A molecule sensor included in a molecule sensor device has a semiconductor substrate, a bottom gate, a source portion, a drain portion, and a nano-scale semiconductor wire. The bottom gate is for example a poly-silicon layer formed on the semiconductor substrate and electrically insulated from the semiconductor substrate. The source portion is formed on the semiconductor substrate and insulated from the semiconductor substrate. The drain portion is formed on the semiconductor substrate and insulated from the semiconductor substrate. The nano-scale semiconductor wire is connected between the source portion and the drain portion, formed on the bottom gate, insulated from the bottom gate, and has a decoration layer thereon for capturing a molecular. The source portion, drain portion, and nano-wire semiconductor wire are for example another poly-silicon layer. The bottom gate receives a specified voltage to change an amount of surface charge carriers of the nano-scale semiconductor wire.

Abstract: A p-type transparent conductive oxide and a solar cell containing the p-type transparent conducting oxide, wherein the p-type transparent conductive oxide includes a molybdenum trioxide doped with an element having less than six valence electrons, the element is selected from the group consisting of alkali metals, alkaline earth metals, group III elements, group IV, group V, transition elements and their combinations. Doping an element having less than six valence electron results in hole number increase, and thus increasing the hole drift velocity, and making Fermi level closer to the range of p-type materials. Hence, a p-type transparent conductive material is generated. This p-type transparent conducting oxide not only has high electron hole drift velocity, low resistivity, but also reaches a transmittance of 88% in the visible wavelength range, and therefore it is very suitable to be used in solar cells.

Abstract: Embodiments of the present invention are directed systems and methods for reading the resistance states of crossbar junctions of a crossbar array. In one aspect, a system includes one or more sense amplifiers connected to column wires of the crossbar array, a reference row wire connected to each sense amp, and a wire driver connected to the reference row wire and configured to drive the reference row wire. The sense amplifiers are configured so that when a selected row wire of the crossbar array is driven by a sense voltage, the column wires are held at approximately zero volts and pass currents through the column wires and sense amplifiers to the reference row wire so that resistive voltage losses along the reference row wire substantially mirror the resistive voltage losses along the selected row wire, allowing the sense amplifiers to determine the crossbar junction resistance states.

Abstract: A thin film transistor includes: a silicon nanowire on a substrate, the silicon nanowire having a central portion and both side portions of the central portion; a gate electrode on the central portion; and a source electrode and a drain electrode spaced apart from the source electrode on the both side portions, the source electrode and the drain electrode electrically connected to the silicon nanowire, respectively.

Abstract: A method for making zinc oxide nano-structure, the method includes the following steps. Firstly, providing a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, providing a growing substrate and forming a metal layer thereon. Thirdly, depositing a catalyst layer on the metal layer. Fourthly, placing the growing substrate into the reacting room together with a quantity of zinc source material. Fifthly, introducing a oxygen-containing gas into the reacting room. Lastly, heating the reacting room to a temperature range of 500˜1100° C.

Abstract: A semiconductor nanowire is formed integrally with a wraparound semiconductor portion that contacts sidewalls of a conductive cap structure located at an upper portion of a deep trench and contacting an inner electrode of a deep trench capacitor. The semiconductor nanowire is suspended from above a buried insulator layer. A gate dielectric layer is formed on the surfaces of the patterned semiconductor material structure including the semiconductor nanowire and the wraparound semiconductor portion. A wraparound gate electrode portion is formed around a center portion of the semiconductor nanowire and gate spacers are formed. Physically exposed portions of the patterned semiconductor material structure are removed, and selective epitaxy and metallization are performed to connect a source-side end of the semiconductor nanowire to the conductive cap structure.

Abstract: A rechargeable lithium cell comprising: (a) an anode comprising a prelithiated lithium storage material or a combination of a lithium storage material and a lithium ion source; (b) a hybrid cathode active material composed of a meso-porous structure of a carbon, graphite, metal, or conductive polymer and a phthalocyanine compound, wherein the meso-porous structure is in an amount of from 1% to 99% by weight based on the total weight of the meso-porous structure and the phthalocyanine combined, and wherein the meso-porous structure has a pore with a size from 2 nm to 50 nm to accommodate phthalocyanine compound therein; and (c) an electrolyte or electrolyte/separator assembly. This secondary cell exhibits a long cycle life and the best cathode specific capacity and best cell-level specific energy of all rechargeable lithium-ion cells ever reported.

Abstract: An axially hetero-structured nanowire includes a first segment that includes GaAs, and a second segment integral with the first that includes InxGa1-xAs. The parameter x has a maximum value x-max within the second segment that is at least 0.02 and less than 0.5. A nanostructured semiconductor component includes a GaAs (111)B substrate, and a plurality of nanopillars integral with the substrate at an end thereof. Each of the plurality of nanopillars can be a nanowire according to an embodiment of the current invention. A method of producing axially hetero-structured nanowires is also provided.

Abstract: A spatially organized polymer nanostructured thin film and a ligand adsorbate attached to the polymer nanostructured thin film and, optionally, an additional material or materials attached to the ligand adsorbate. A method for forming a structure by: providing a spatially organized polymer nanostructured thin film and a ligand adsorbate, and adsorbing the ligand adsorbate onto the thin film and, optionally, binding additional material or materials to the ligand adsorbate.

Abstract: Provided is a method for stabilizing a dispersion of a carbon nanomaterial in a lubricating oil basestock. The method includes providing a lubricating oil basestock; dispersing a carbon nanomaterial in the lubricating oil basestock; and adding at least one block copolymer thereto. The at least one block copolymer has two or more blocks includes at least one alkenylbenzene block and at least one linear alpha olefin block. The at least one block copolymer is present in an amount sufficient to stabilize the dispersion of the carbon nanomaterial in the lubricating oil basestock. Also provided is a lubricating engine oil having a composition including: a lubricating oil base stock; a carbon nanomaterial dispersed in the lubricating oil basestock; and at least one block copolymer.

Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.

Abstract: An electrospinning fine fiber production methodology for generating a significant amount of fibers with diameters of less than 100 nanometers is provided. Also, a filter media composite comprising a substrate layer and an electrospun fine fiber layer having a increased efficiency relative to pressure drop and/or a controlled pore size distribution is provided. According to some embodiments nylon is electrospun from a solvent combination of formic and acetic acids.