Abstract: The present disclosure provides a method for preparing a semiconductor structure. The method includes the following steps. A substrate including a conductive layer formed thereon is provided. The conductive layer is patterned to form a plurality of conductive patterns extending along a first direction. A cap layer is conformally formed to cover the plurality of conductive patterns. A patterned hard mask is formed over the cap layer. The plurality of conductive patterns are etched through the patterned hard mask to form a plurality of conductive islands. In some embodiments, the plurality of conductive islands are separated from each other by a plurality of first gaps along the first direction. In some embodiments, the plurality of conductive islands are separated from each other by the cap layer and a plurality of second gaps along a second direction that is different from the first direction.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.

Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.

Abstract: A computer-implemented method includes receiving download description information for an application from a network using an encrypted communications channel, wherein the download description information includes download address information specifying a network address from which application packages associated with the particular application can be retrieved; and downloading an application package associated with the particular application from the network address specified in the download address information, wherein the application package is downloaded using an unencrypted communications channel.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

Abstract: A multi-cell transistor includes a semiconductor structure, a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor extending in a first direction in the semiconductor structure, wherein the unit cell transistors are spaced apart from each other along a second direction, and an isolation structure that is positioned between a first group of the unit cell transistors and a second group of the unit cell transistors and that extends above the semiconductor structure.

Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

Abstract: A power conversion apparatus includes: a board; a first electronic component disposed on a first surface of the board; and a temperature sensor disposed on a second surface of the board which is opposite to the first surface. The power conversion apparatus may further include a first heat conductive member disposed between the first electronic component and the temperature sensor.

Abstract: A semiconductor device according to an embodiment includes a substrate, first to third conductors, and first and second contacts. The first conductor is provided in a first layer above the substrate. The first contact extends in a first direction, and is provided on the first conductor. The second conductor is provided in the first layer and is insulated from the first conductor. The third conductor is provided between the second conductor and the substrate. The second contact extends in the first direction through the second conductor, and is provided on the third conductor. A width of the second contact, as viewed in a second direction, differs between a portion above a boundary face that is included in the first layer and is parallel to the surface of the substrate, and a portion that is below the boundary face.

Abstract: Described herein is an integrated circuit device comprising a conductive line structure including a bit line and an insulating capping pattern; and an insulating spacer covering a side wall of the conductive line structure, the insulating spacer including an inner spacer and a char spacer. To form the insulating spacer, a polymer brush pattern may be chemically bonded to the inner spacer to cover a side wall of the conductive line structure; a first insulating spacer film covering the inner spacer and the polymer brush pattern may be formed; and a char spacer may be formed from the polymer brush pattern by pyrolyzing the polymer brush pattern in the absence of oxygen.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.

Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.

Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.

Abstract: Examples herein include a solid state drive microelectronics package assembly including a substrate and a plurality of microelectronic components coupled to the substrate. The plurality of microelectronic components may be being separated from one another end-to-end by a component gap. The microelectronics package may further include a die package coupled to the substrate, wherein the die package extends across the component gap and is vertically disposed between the plurality of microelectronic components and the substrate. In some examples, the microelectronics components and the die package are each coupled to the substrate by a plurality of connection components (e.g. a solder ball array). The plurality of connection components may be arranged on the microelectronics components to define one or more open areas devoid of any connection components. The die package may be positioned/nested within the one or more open areas to increase overall microelectronic component density of the microelectronics package.

Abstract: A three-dimensional semiconductor device includes gate electrodes including pad regions sequentially lowered by a first step portion in a first direction and sequentially lowered by a second step portion in a second direction perpendicular to the first direction, the second step portion being lower than the first step portion, wherein a length of a single pad region among pad regions sequentially lowered by the second step portion in the second direction is less than a length of a remainder of the pad regions in the second direction.

Abstract: A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.

Abstract: A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module includes an insulated-gate bipolar transistor, a metal-oxide-semiconductor field-effect transistor, and a lead frame. The insulated-gate bipolar transistor and the metal-oxide-semiconductor field-effect transistor are connected in parallel to each other and provided on the same lead frame. The cooler has a coolant flow passage. The coolant flow passage extends such that the coolant flow passage and the lead frame of the semiconductor module are opposed to each other. The semiconductor module is configured such that the metal-oxide-semiconductor field-effect transistor is not disposed further downstream than the insulated-gate bipolar transistor in a flow direction of a coolant in the coolant flow passage of the cooler.

Abstract: A substrate of the silicon on insulator type includes a semi-conducting film disposed on a buried insulating layer which is disposed on an unstressed silicon support substrate. The semi-conducting film includes a first film zone of tensile-stressed silicon and a second film zone of tensile-relaxed silicon. Openings through the buried insulating layer permit access to the unstressed silicon support substrate under the first and second film zones. An N channel transistor is formed from the first film zone and a P channel transistor is formed from the second film zone. The second film zone may comprise germanium enriched silicon forming a compressive-stressed region.

Abstract: Disclosed is a three-dimensional semiconductor device including a stack structure on a substrate and including electrodes that are vertically stacked on top of each other on a first region of a substrate, a vertical structure penetrating the stack structure and including a first semiconductor pattern, a data storage layer between the first semiconductor pattern and at least one of the electrodes, a transistor on a second region of the substrate, and a first contact coupled to the transistor. The first contact includes a first portion and a second portion on the first portion. Each of the first portion and the second portions has a diameter that increases with an increasing vertical distance from the substrate. A diameter of an upper part of the first portion is greater than a diameter of a lower part of the second portion.

Abstract: An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive structure on a substrate, forming an insulation layer on a sidewall of the first conductive structure, forming a second conductive structure a distance apart from the first conductive structure with the insulation layer therebetween, first removing a portion of the insulation layer by performing a first dry cleaning operation, second removing a reactant product used in the first dry cleaning operation or a first byproduct generated as a result of the first dry cleaning operation by performing a first purge operation, and third removing at least a portion of the remaining insulation layer by performing a second dry cleaning operation to form an air gap between the first and second conductive structures.

Abstract: Provided are an insulating ceramic paste, a ceramic electronic component, and a method for producing the ceramic electronic component that allow prevention of solder shorts between narrow-pitch terminal electrodes and suppression of generation of cracks in an insulator covering a portion of terminal electrodes during a firing step. The ceramic electronic component includes a ceramic multilayer substrate, terminal electrodes formed on a surface of the ceramic multilayer substrate, and an insulating ceramic film formed on the surface of the ceramic multilayer substrate so as to cover a portion of the terminal electrodes. An exposed surface portion (celsian-crystal-rich layer) of the insulating ceramic film has a thermal expansion coefficient that is lower than the thermal expansion coefficient of the ceramic multilayer substrate.

Abstract: The invention discloses an STI stress effect modeling method and device of an MOS device, and belongs to the technical field of parameter extraction modeling of devices. The method comprises the following steps: introducing the influence of temperature parameters on the STI stress effect of the MOS device, so as to form a function showing that the STI stress effect of the MOS device changes along with the temperature parameters; extracting the model parameter Model1 of the MOS device at normal temperature; on the basis of the Model1, extracting the parameter Model2 that the STI stress affects the properties of the MOS device at normal temperature; and on the basis of the Model2, extracting fitting parameters of the MOS device in the function so as to acquire final model parameters. The device comprises a first module, a second module, a third module and a fourth module.

Abstract: A semiconductor integrated circuit device, including a semiconductor layer of a first conductivity type, a first well region of a second conductivity type, a second well region of the second conductivity type, and a third well region of the first conductivity type. The device further includes an isolation region electrically isolating a predetermined region in the first well region, a first high-concentration region of the second conductivity type, disposed outside the isolation region and inside one of the first well region and the second well region, and a second high-concentration region of the second conductivity type, disposed inside the isolation region and inside one of the first well region and the second well region. The first and second high-concentration regions each have an impurity concentration that is higher than that of the first well region.

Abstract: A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.

Abstract: A circuit device having differently-strained NMOS and PMOS FinFETs is provided. In an exemplary embodiment, a semiconductor device includes a substrate with a first fin structure and a second fin structure formed thereup. The first fin structure includes opposing source/drain regions disposed above a surface of the substrate; a channel region disposed between the opposing source/drain regions and disposed above the surface of the substrate; and a first buried layer disposed between the channel region and the substrate. The first buried layer includes a compound semiconductor oxide. The second fin structure includes a second buried layer disposed between the substrate and a channel region of the second fin structure, such that the second buried layer is different in composition from the first. For example, the second fin structure may be free of the compound semiconductor oxide.

Abstract: A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.

Abstract: According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried layer at least one of in or over the substrate by processing the first side of the substrate; thinning the substrate from the second side of the substrate, wherein the buried layer includes a solid state compound having a greater resistance to the thinning than the substrate and wherein the thinning stops at the buried layer.

Abstract: A semiconductor device having a substrate, a dielectric layer over the substrate, a first gate conductor, an inter-gate dielectric structure and a second gate conductor is disclosed. A gate dielectric structure is disposed between the first gate conductor and the dielectric layer, and may include two or more dielectric films disposed in an alternating manner. The inter-gate dielectric structure may be disposed between the first gate conductor and the second gate conductor, and may include two or more dielectric films disposed in an alternating manner. The second gate conductor is formed in an L shape such that the second gate has a relatively low aspect ratio, which allows for a reduction in spacing between adjacent gates, while maintaining the required electrical isolation between the gates and contacts that may subsequently be formed.

Abstract: In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a dielectric layer. A via is provided through the passivation layer and the dielectric layer in the vicinity of the corners of the metallization. The via may be a “dummy” via without electrical connections to an active device and may be provided at a distance between approximately 1 micron (10?6 m.) and approximately 10 micron (10?5 m.) from each one of said converging sides landing on an underlying metal layer.

Abstract: A micromechanical pressure sensor device and a corresponding manufacturing method. The micromechanical pressure sensor device includes an ASIC wafer having a front side and a rear side, and a rewiring system, formed on the front side of the ASIC wafer, which includes a plurality of stacked strip conductor levels and insulation layers. The pressure sensor device also includes a MEMS wafer having a front side and a rear side, a first micromechanical functional layer which is formed above the front side of the MEMS wafer, and a second micromechanical functional layer which is formed above the first micromechanical functional layer.

Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.

Abstract: A multilayer wiring in a semiconductor device includes a first lower wiring formed in a first insulating layer, a via which is formed in a second insulating layer over the first insulating layer and which is connected to the first lower wiring, and an upper wiring connected to the via. The upper wiring has an outer edge at which a nick portion is formed beside a portion of the upper wiring to which the via is connected. The formation of the nick portion at the outer edge of the upper wiring prevents the via from enlarging.

Abstract: A type III-V semiconductor substrate is provided. Semiconductor material is removed from the type III-V semiconductor substrate such that the type III-V semiconductor substrate comprises one or more alignment features extending away from a main lateral surface. Each of the alignment features includes a first lateral surface that is vertically offset from the main lateral surface, and first and second vertical sidewalls that extend between the first lateral surface and the main lateral surface. An epitaxy blocker is formed on the first and second vertical sidewalls of each alignment feature. A type III-V semiconductor regrown layer is epitaxially grown on a portion of the semiconductor wafer that includes the one or more alignment features. The epitaxy blocker prevents the type III-V semiconductor regrown layer from forming on the first and second vertical sidewalls of the one or more alignment features.

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

Abstract: A semiconductor device and method of manufacturing the same is provided. The semiconductor device includes a semiconductor substrate and a stacked capacitor. The stacked capacitor is over the semiconductor substrate. The stacked capacitor includes a lower electrode plate, an upper electrode plate, a dielectric layer, a cap layer, a first via hole and a second via hole. The lower electrode plate is over the semiconductor substrate. The upper electrode plate is over the lower electrode plate. The dielectric layer is between the lower electrode plate and the upper electrode plate. The cap layer is over the upper electrode plate. The first via hole is through the cap layer, the upper electrode plate and the dielectric layer, partially exposing the lower electrode plate. The second via hole is through the cap layer, partially exposing the upper electrode plate.

Abstract: A semiconductor structure includes a semiconductor substrate with a first region and a second region defined thereon. The first region is disposed adjoining the second region in a first direction. The semiconductor substrate includes fin structures, first recessed fins, and a bump. The fin structures are disposed in the first region. Each fin structure is elongated in the first direction. The first recessed fins are disposed in the second region. Each first recessed fin is elongated in the first direction. A topmost surface of each first recessed fin is lower than a topmost surface of each fin structure. The bump is disposed in the second region and disposed between two adjacent recessed fins in the first direction. A topmost surface of the bump is higher than the topmost surface of each first recessed fin and lower than the topmost surface of each fin structure.

Abstract: The present disclosure provides a static random access memory (SRAM) cell comprising first, second, and third fins defined in various well regions. The fins are spaced from each other along a first direction and extend lengthwise generally along a second direction perpendicular to the first direction. The fins include source, drain, and channel regions for various pull-up, pull-down, and pass-gate fin field-effect transistors (FinFETs). The SRAM cell further includes various gate features over the fins and extending lengthwise generally along the first direction. The gate features include gate regions for the various FinFETs.

Abstract: A universal serial bus (USB) hub includes a USB AFE circuit module, a hub core and an isolator circuit module interposed between the USB AFE circuit module and the hub core. Data communications between the hub core and the first USB AFE circuit module pass through the isolator circuit module. A method for communicating through a universal serial bus hub includes providing a USB AFE circuit module, providing a hub core, providing an isolator circuit module interposed between the USB AFE circuit module and the hub core, and directing communication from the USB AFE circuit module to the hub core through the isolator circuit module.

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.

Abstract: A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.

Abstract: A method of fabricating a semiconductor structure is provided and includes the following steps. A semiconductor substrate including fin structures is provided. Each fin structure is partly located in a first region and partly located in a second region adjoining the first region. A fin remove process is performed for removing the fin structures in the second region. A fin cut process with a fin cut mask is performed for cutting a part of the fin structures in the first region. The fin cut mask includes cut patterns and a compensation pattern. The cut patterns are located corresponding to a part of the fin structures in the first region. The compensation pattern is located corresponding to the second region of the semiconductor substrate. A fin bump is formed in the second region and corresponding to the compensation pattern after the fin cut process and the fin remove process.

Abstract: A silicon interposer includes a substrate having a frontside surface and a backside surface, a first redistribution layer (RDL) structure disposed on the frontside surface, a plurality of first connecting elements disposed on the first RDL structure, a second RDL structure disposed on the backside surface, a plurality of second connecting elements disposed on the second RDL structure, and a plurality of through silicon vias in the substrate to electrically connect the first RDL structure to the second RDL structure. The first connecting elements have a first pitch. The second connecting elements have a second pitch. The second pitch is greater than the first pitch.

Abstract: A semiconductor device includes a spacer having a nitride/oxide/nitride (NON) structure. The spacer is disposed between a sidewall of a bit line and a bit line contact and a sidewall of a storage node contact plug to reduce coupling capacitance between the bit line and a storage node contact plug and between the bit line contact and the storage node contact plug.

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

Abstract: The present invention relates to the technical field of display by a touch screen, and particularly relates to a conductive bridging method, a bridging structure, a touch panel and a touch control display apparatus. The conductive bridging method comprises: sequentially forming an insulating layer and a self-assembled-monolayer on the base substrate provided with first electrode lines and second electrode lines which mutually intersect; forming via holes penetrating through the insulating layer and the self-assembled-monolayer; removing the self-assembled-monolayer between two adjacent via holes close to a same first electrode line; and forming a conductive film in the via holes and in a region between two adjacent via holes. In this way, a bridging connection is achieved with the help of the electrical conductivity of the conductive film.

Abstract: An integrated optical modulator includes, in part, a pair of waveguides and an inductor. The first waveguide is adapted to receive an incoming optical signal. The second waveguide includes a portion placed in proximity of the first waveguide so as to enable the incoming optical signal travelling in the first waveguide to couple to the second waveguide. The second waveguide comprises a p-n junction. The inductor has a first terminal coupled to the p-n junction and a second terminal coupled to a contact pad. The second waveguide has a circular shape. The inductor optionally has a spiral shape.

Abstract: A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.