Abstract: A semiconductor integrated circuit includes a plurality of stacked slices each configured to have a plurality of vias formed therein so that signals are transferred between the slices arranged in a vertical direction, wherein each of the plurality of slices is configured to transfer a pulse signal, generated during a test section, to a lowest slice of the plurality of slices through the vias connected thereto.

Abstract: A method of manufacturing a semiconductor device which can prevent leakage current caused by gate electrodes intersecting element isolation layers in a major axis of an active region, and which further has vertical channels to provide a sufficient overlap margin, and a semiconductor device manufactured using the above method. The device includes gate electrodes formed on element isolation layers that are disposed between active regions and have top surfaces that are higher than the top surfaces of the active regions. Since the gate electrodes are formed on the element isolation layers, leakage current in a semiconductor substrate is prevented. In addition, the gate electrodes are formed using a striped shape mask pattern, thereby obtaining a sufficient overlap margin compared to a contact shape or bar shape pattern.

Abstract: A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Abstract: A circuit substrate structure including a substrate, a dielectric stack layer, a first plating layer and a second plating layer is provided. The substrate has a pad. The dielectric stack layer is disposed on the substrate and has an opening exposing the pad, wherein the dielectric stack layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer located between the first dielectric layer and the second dielectric layer, and there is a gap between the portion of the first dielectric layer surrounding the opening and the portion of the second dielectric layer surrounding the opening. The first plating layer is disposed at the dielectric stack layer. The second plating layer is disposed at the pad, wherein the gap isolates the first plating layer from the second plating layer.

Abstract: An RRAM at an STI region is disclosed with a vertical BJT selector. Embodiments include defining an STI region in a substrate, implanting dopants in the substrate to form a well of a first polarity around and below an STI region bottom portion, a band of a second polarity over the well on opposite sides of the STI region, and an active area of the first polarity over each band of second polarity at the surface of the substrate, forming a hardmask on the active areas, removing an STI region top portion to form a cavity, forming an RRAM liner on cavity side and bottom surfaces, forming a top electrode in the cavity, removing a portion of the hardmask to form spacers on opposite sides of the cavity, and implanting a dopant of the second polarity in a portion of each active area remote from the cavity.

Abstract: A CMOS chip comprising a high performance device region and a high density device region includes a plurality of high performance devices comprising n-type field effect transistors (NFETs) and p-type field effect transistors (PFETs) in the high performance device region, wherein the high performance devices have a high performance pitch; and a plurality of high density devices comprising NFETs and PFETs in the high density device region, wherein the high density devices have a high density pitch, and wherein the high performance pitch is about 2 to 3 times the high density pitch; wherein the high performance device region comprises doped source and drain regions, NFET gate regions having an elevated stress induced using stress memorization technique (SMT), gate silicide and source/drain silicide regions, and a dual stressed liner, and wherein the high density device region comprises doped source and drain regions, gate silicide regions, and a neutral stressed liner.

Abstract: A reconstituted electronic device comprising at least one die and at least one passive component. A functional material is incorporated in the substrate of the device to modify the electrical behaviour of the passive component. The passive component may be formed in redistribution layers of the device. Composite functional materials may be used in the substrate to forms part of or all of the passive component. A metal carrier may form part of the substrate and part of the at least one passive component.

Abstract: A wafer includes a plurality of chips, each of the chips being spaced from each other by kerf-line regions including a reduced width.

Abstract: A semiconductor device including a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

Abstract: A method of forming one or more diodes in a fin field-effect transistor (FinFET) device includes forming a hardmask layer having a fin pattern, said fin pattern including an isolated fin area, a fin array area, and a FinFET area. The method further includes etching a plurality of fins into a semiconductor substrate using the fin pattern, and depositing a dielectric material over the semiconductor substrate to fill spaces between the plurality of fins. The method further includes planarizing the semiconductor substrate to expose the hardmask layer. The method further includes implanting a p-type dopant into the fin array area and portions of the FinFET area, and implanting an n-type dopant into the isolated fin area, a portion of the of fin array area surrounding the p-well and portions of the FinFET area. The method further includes annealing the semiconductor substrate.

Abstract: A donor wafer containing integrated semiconductor device. The donor wafer has a donor wafer membrane portion that has a device layer and a buried insulating layer. The donor wafer membrane portion has a number of integrated semiconductor devices where each integrated semiconductor device within the plurality of semiconductor devices corresponds to a die formed on the donor wafer. The donor wafer membrane portion has a diameter of at least 200 mm. The donor wafer has a crystalline substrate that is substantially removed from an area of the donor wafer membrane portion such that the device layer and the buried insulating layer of the donor wafer membrane in the area is configured to conform to a pattern specific topology on an acceptor surface. The donor wafer further has a support structure attached to regions of the donor wafer that are outside of the donor wafer membrane portion.

Abstract: A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive layer underneath the second layer, the at least one conductive layer is constructed to provide a back-bias to a portion of the plurality of second single crystal transistors.

Abstract: A methodology is disclosed enabling the formation of silicon trench profiles for devices, such as SSRW FETs, having a resultant profile that enables desirable epitaxial growth of semiconductor materials. Embodiments include forming a trench in a silicon wafer between STI regions, thermally treating the silicon surfaces of the trench, and forming Si:C in the trench. The process eliminates a need for an isotropic silicon etch to achieve a desirable flat surface. Further, the flat bottom surface provides a desirable surface for epitaxial growth of semiconductor materials, such as Si:C.

Abstract: A semiconductor device includes a semiconductor chip, an interposer, a surface circuit pattern, and a post array. The surface circuit pattern is formed on one surface of the interposer and includes chip side pads connected to an external connection pad of the semiconductor chip, junction pads, and interconnecting lines having an end connected to the chip side pads and another end connected to the junction pads. The interconnecting lines extend from the chip side pads toward an outer edge of the interposer. The post array includes conducting paths and insulating resin insulating the conductive paths from each other. The post array is arranged such that the conductive paths extend in a direction intersecting with the surface of the interposer. The conducting paths each have an end connected to the junction pad and another end to be connected to the printed wiring board.

Abstract: A semiconductor substrate having an isolation region and method of forming the same. The method includes the steps of providing a substrate having a substrate layer, a buried oxide (BOX), a silicon on insulator (SOI) layer, a pad oxide layer, and a pad nitride layer, forming a shallow trench region, etching the pad oxide layer to form ears and etching the BOX layer to form undercuts, depositing a liner on the shallow trench region, depositing a soft mask over the surface of the shallow trench region, filling the shallow trench region, etching the soft mask so that it is recessed to the top of the BOX layer, etching the liner off certain regions, removing the soft mask, and filling and polishing the shallow trench region. The liner prevents shorting of the semiconductor device when the contacts are misaligned.

Abstract: A memory array includes a rhomboid-shaped AA region surrounded by a first and second STI structures. The first STI structure extends along a first direction on the longer sides of the rhomboid-shaped AA region and has a depth d1. The second STI structure extends along the second direction on the shorter sides of the rhomboid-shaped AA region and has two depths: d2 and d3, wherein d1 and d2 are shallower than d3.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A nonvolatile memory device includes; a memory cell array designating a first memory cell group including first memory cells connected with a word line and disposed less than a reference distance from a word line voltage source in a word line direction, and a second memory cell group including second memory cells connected to the word line and disposed more than the reference distance from the word line voltage source in the word line direction, and control logic configured during a data processing operation to provide a first word line voltage to a first target memory cell among the first memory cells, and a second word line voltage different from the first word line voltage to a second target memory cell among the second memory cells.

Abstract: An array includes vertically-oriented transistors. The array includes rows of access lines and columns of data/sense lines. Individual of the rows include an access line interconnecting transistors in that row. Individual of the columns include a data/sense line interconnecting transistors in that column. The array includes a plurality of conductive lines which individually extend longitudinally parallel and laterally between immediately adjacent of the data/sense lines. Additional embodiments are disclosed.

Abstract: A transistor is formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench.

Abstract: A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.

Abstract: One embodiment of a semiconductor device includes a semiconductor body with a first side and a second side opposite to the first side. The semiconductor device further includes a first contact trench extending into the semiconductor body at the first side. The first contact trench includes a first conductive material electrically coupled to the semiconductor body adjoining the first contact trench. The semiconductor further includes a second contact trench extending into the semiconductor body at the second side. The second contact trench includes a second conductive material electrically coupled to the semiconductor body adjoining the second contact trench.

Abstract: The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.

Abstract: This disclosure relates to a method of making a semiconductor device. The method includes comparing a schematic design of the semiconductor device to a layout design of the semiconductor device. The method further includes generating layout style information based on the layout design and generating array edge information based on the layout design and the schematic design. The method further includes selectively revising the layout design using smart dummy insertion using the layout style information and the array edge information. The method further includes performing a design rule check on the revised layout design using the layout style information and the array edge information. This disclosure also relates to a system for making a semiconductor device and a semiconductor device.

Abstract: A thin film capacitor is characterized by forming a lower electrode, coating a composition onto the lower electrode without applying an annealing process having a temperature of greater than 300° C., drying at a predetermined temperature within a range from ambient temperature to 500° C., and calcining at a predetermined temperature within a range of 500 to 800° C. and higher than a drying temperature. The process from coating to calcining is performed the process from coating to calcining once or at least twice, or the process from coating to drying is performed at least twice, and then calcining is performed once. The thickness of the dielectric thin film formed after the first calcining is 20 to 600 nm. The ratio of the thickness of the lower electrode and the thickness of the dielectric thin film formed after the initial calcining step (thickness of lower electrode/thickness of the dielectric thin film) is preferably in the range 0.10 to 15.0.

Abstract: An electronic device, including an integrated circuit, can include a buried conductive region and a semiconductor layer overlying the buried conductive region, wherein the semiconductor layer has a primary surface and an opposing surface lying closer to the buried conductive region. The electronic device can also include a first doped region and a second doped region spaced apart from each other, wherein each is within the semiconductor layer and lies closer to primary surface than to the opposing surface. The electronic device can include current-carrying electrodes of transistors. A current-carrying electrode of a particular transistor includes the first doped region and is a source or an emitter and is electrically connected to the buried conductive region. Another current-carrying electrode of a different transistor includes the second doped region and is a drain or a collector and is electrically connected to the buried conductive region.

Abstract: An integrated circuit includes first and second terminals. The integrated circuit further includes a first plurality of diodes arranged in series between the first terminal and a power supply terminal and a second plurality of diodes arranged in series between the second terminal and the power supply terminal. The integrated circuit also includes a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality of diodes. The first node is located between a first diode of the first plurality of diodes and a last diode of the first plurality of diodes, and the second node is located between a first diode of the second plurality of diodes and a last diode of the second plurality of diodes.

Abstract: An integrated circuit (IC) having an internal power supply voltage step down circuit provides efficiency while requiring a minimum of external terminals. In a first operating mode, a storage capacitor is charged from the power supply return of a group of circuits, while the group of circuits is powered from an input power supply voltage provided to the IC. In a second operating mode, the group of circuits is powered from the storage capacitor. The step-down circuit provides for halving the input power supply voltage, but multiple storage capacitors and additional operating modes can be provided for voltage division by greater factors. A sensing circuit can be employed to sense the voltage across the storage capacitor(s) and in response, select the operating mode, providing hysteretic control of the voltage supplied to the group of circuits.

Abstract: An fabrication of three-dimensional integrated devices and three-dimensional integrated devices fabricated therefrom are described. A device side of a donor wafer is coated with a polymer film and exposure of a substrate side to an oxidizing plasma creates a continuous SiO2 film. Portions of the substrate side are selectively coated with a polymer film and etching of uncoated areas removes at least a substantial portion of the crystalline substrate. A plasma etch tool etches a crystalline substrate to within a pre-determined thickness. The silicon portions of the substrate side are etched by exposure to TMAH. After etching, the donor semiconductor wafer is supported by portions of the substrate that were not etched. The supporting structure allows flexing of the donor semiconductor wafer within the etched areas to enable conformality and reliable bonding to the device surfaces of an acceptor wafer to form a three dimensional integrated device.

Abstract: A high-voltage integrated circuit device can include, in a surface layer of a p semiconductor substrate, an n region which is a high-side floating-potential region, an n? region which becomes a high-voltage junction terminating region, and an n? region which is an L-VDD potential region. A low-side circuit portion can be disposed in an n? region. Below a pickup electrode disposed in the high-voltage junction terminating region, a universal contact region in Ohmic contact with the pickup electrode can be disposed. The universal contact region has a p+ region and an n+ region that can be disposed in alternating contact along a surface of the p semiconductor substrate. By disposing the universal contact region in this way, the quantity of carriers flowing into the low-side circuit portion can be reduced when a negative surge voltage is input. Consequently, erroneous operation due to latchup of a logic portion can be minimized.

Abstract: A semiconductor device includes: a package; an input matching circuit and an output matching circuit in the package; and transistor chips between the input matching circuit and the output matching circuit in the package. Each transistor chip includes a semiconductor substrate having long sides and short sides that are shorter than the long sides, and a gate electrode, a drain electrode and a source electrode on the semiconductor substrate. The gate electrode has gate fingers arranged along the long sides of the semiconductor substrate and a gate pad commonly connected to the gate fingers and connected to the input matching circuit via a first wire. The drain electrode is connected to the output matching circuit via a second wire. The long sides of the semiconductor substrates of the transistor chips are oblique with respect to an input/output direction extending from the input matching circuit to the output matching circuit.

Abstract: Through gate fin isolation for non-planar transistors in a microelectronic device, such as an integrated circuit (IC). In embodiments, ends of adjacent semiconductor fins are electrically isolated from each other with an isolation region that is self-aligned to gate electrodes of the semiconductor fins enabling higher transistor packing density and other benefits. In an embodiment, a single mask is employed to form a plurality of sacrificial placeholder stripes of a fixed pitch, a first subset of placeholder stripes is removed and isolation cuts made into the semiconductor fins in openings resulting from the first subset removal while a second subset of the placeholder stripes is replaced with gate electrodes.

Abstract: An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact.

Abstract: An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N? type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.

Abstract: A disclosed memory device includes a three-dimension array structure that includes memory layers and transistor structures disposed between the memory layers. Each memory layer is connected to a common electrode, and each transistor structure includes transistors that share common column structures and common base structures. The transistors also each include a connector structure that is spaced apart from a common column structure by a common base structure.

Abstract: A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other.

Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

Abstract: A design support method includes: selecting, by a computer, a power feed point of an integrated semiconductor circuit on a first board model in which a power supply layer and a ground layer are stacked; determining a first placement position of a first protrusion portion from the first board model on a side of the first board model, the first protrusion portion being corresponding to the power feed point; determining a second placement position of a second protrusion portion from the first board model on the side of the first board model, the second protrusion portion provided so as to separate from the first placement position by a distance; and placing the first protrusion portion and the second protrusion portion on the first placement position and the second placement position, respectively.

Abstract: The disclosed aspects relate to controlling density of photomasks. One or more unprintable auxiliary patterns can be placed near a mask feature as well as onto a location of a feature of the main pattern. If a density is measured and is not within an acceptable density range, one or more printable auxiliary patterns can be replaced with unprintable auxiliary patterns and/or one or more unprintable auxiliary patterns can be replaced with printable auxiliary patterns. The disclosed aspects can be utilized to create a photomask and/or a semiconductor device, such as a large scale integrated circuit device, that comprises the photomask.

Abstract: Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.

Abstract: Disclosed are a laser annealing method and apparatus capable of forming a crystalline semiconductor thin film on the entire surface of a substrate without sacrificing the uniformity of crystallinity in a seam portion in a long-axis direction of laser light, the crystalline semiconductor thin film having good properties and high uniformity to an extent that the seam portion is not visually recognizable. During the irradiation of a linear beam, portions corresponding to the edges of the linear beam are shielded by a mask 10 which is disposed on the optical path of a laser light 2, and the mask 10 is operated so that the amount of shielding is periodically increased and decreased.

Abstract: A structure for picking up a collector region is disclosed. The structure includes a pair of polysilicon stacks formed in the isolation regions and extending below the collector region; and a pair of collector electrodes contacting on the polysilicon stacks, wherein the pair of polysilicon stacks includes: a first polysilicon layer located below the isolation regions, and a second polysilicon layer located on and in contact with the first polysilicon layer, the first polysilicon layer being doped with a dopant having a higher diffusivity or higher concentration than a dopant of the second polysilicon layer, wherein a depth of the polysilicon stacks is greater than a depth of the collector region; the depth of the collector region is greater than a depth of the second polysilicon layer; and the depth of the second polysilicon layer is greater than a depth of the isolation regions.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: A sensor array is integrated onto the same chip as core logic. The sensor array uses a first polysilicon and the core logic uses a second polysilicon. The first polysilicon is etched to provide a tapered profile edge in the interface between the sensor array and the core logic regions to avoid an excessive step. Amorphous carbon can be deposited over the interface region without formation of voids, thus providing for improved manufacturing yield and reliability.

Abstract: There is provided a technology capable of providing desirable operation characteristics in a field effect transistor formed in an active region surrounded by a trench type element isolation part. An element isolation part includes trench type element isolation films, diffusion preventive films each including a silicon film or a silicon oxide film, and having a thickness of 10 to 20 nm formed over the top surfaces of the trench type element isolation films, and silicon oxide films each with a thickness of 0.5 to 2 nm formed over the top surfaces of the diffusion preventive films. The composition of the diffusion preventive film is SiOx (0?x<2). Each composition of the trench type element isolation films and the silicon oxide films is set to be SiO2.

Abstract: In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

Abstract: The present invention is a method for providing an integrated circuit assembly, the integrated circuit assembly including an integrated circuit and a substrate. The method includes mounting the integrated circuit to the substrate. The method further includes, during assembly of the integrated circuit assembly, applying a low processing temperature, at least near-hermetic, glass-based coating directly to the integrated circuit and a localized interconnect interface, the interface being configured for connecting the integrated circuit to at least one of the substrate and a second integrated circuit of the assembly. The method further includes curing the coating. Further, the integrated circuit may be a device which is available for at least one of sale, lease and license to a general public, such as a Commercial off the Shelf (COTS) device. Still further, the coating may promote corrosion resistance and reliability of the integrated circuit assembly.