Abstract: Systems and methods for reducing gate leakage current and positive bias temperature instability drift are provided. In one embodiment, a system comprises a p-channel field effect transistor (PFET) device on a semiconductor substrate, and a high voltage transistor on the substrate. The system also comprises a plurality of silicides formed in the substrate, the plurality of silicides formed proximate to the PFET device and the high voltage transistor. Further, the system comprises a buffer oxide layer formed over the substrate, the PFET device, and the high voltage transistor and a moisture barrier formed over the buffer layer, the moisture barrier comprised of silicon oxynitride. Additionally, the system comprises an interlayer dielectric device formed over the moisture barrier and a plurality of electrical contacts extending through the interlayer dielectric, the moisture barrier, and the buffer oxide layer, wherein the plurality of electrical contacts are electrically connected to the plurality of silicides.

Abstract: A semiconductor die with an integrated electronic circuit, configured so as to be mounted in a housing with a capacitive transducer e.g. a microphone. A first circuit is configured to receive an input signal from the transducer at an input node and to provide an output signal at a pad of the semiconductor die. The integrated electronic circuit comprises an active switch device with a control input, coupled to a pad of the semiconductor die, to operatively engage or disengage a second circuit interconnected with the first circuit so as to operate the integrated electronic circuit in a mode selected by the control input. That is, a programmable or controllable transducer. The second circuit is interconnected with the first circuit so as to be separate from the input node. Thereby less noise is induced, a more precise control of the circuit is obtainable and more advanced control options are possible.

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

Abstract: A semiconductor device includes: a SOI substrate including a support layer, a first insulation film and a SOI layer; a first circuit; a second circuit; and a trench separation element. The SOI substrate further includes a first region and a second region. The first region has the support layer, the first insulation film and the SOI layer, which are stacked in this order, and the second region has only the support layer. The trench separation element penetrates the support layer, the first insulation film and the SOI layer. The trench separation element separates the first region and the second region. The first circuit is disposed in the SOI layer of the first region. The second circuit is disposed in the support layer of the second region.

Abstract: A semiconductor storage device according to an embodiment comprises active areas on a semiconductor substrate. An element isolation is arranged between the active areas and filled by an insulating film. A plurality of memory cells configured to store data are formed on the active areas. Air gaps are arranged between upper-end edge parts of the active areas where the memory cells are formed and an insulating film in the element isolation.

Abstract: Example embodiments relate to a method of forming a germanium (Ge) silicide layer, a semiconductor device including the Ge silicide layer, and a method of manufacturing the semiconductor device. A method of forming a Ge silicide layer according to example embodiments may include forming a metal layer including vanadium (V) on a silicon germanium (SiGe) layer. The metal layer may have a multiple-layer structure and may further include at least one of platinum (Pt) and nickel (Ni). The metal layer may be annealed to form the germanium silicide layer. The annealing may be performed using a laser spike annealing (LSA) method.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a substrate having a first conductor-type, a buried layer of a second conductor-type on the substrate, a drain, and a first guard-ring on one side of the drain, a second guard-ring on one side of the first guard-ring, and a third guard-ring on one side of the second guard-ring.

Abstract: A semiconductor storage device according to an embodiment includes a memory cell array provided on a semiconductor substrate and comprising a plurality of memory cells configured to store data therein, and a peripheral circuit part provided on the semiconductor substrate and configured to control the memory cell array. An element isolation part is provided between active areas where the memory cells and the peripheral circuit part are formed. A sidewall film is provided on a side surface of the active area in the peripheral circuit part.

Abstract: Provided is a semiconductor wafer. In the semiconductor wafer, formation and etching of an n type epitaxial layer and formation and etching of a p type epitaxial layer are alternately performed for at least three times, so that all semiconductor layers are formed of epitaxial layers on a semiconductor substrate. Thereby, the respective semiconductor layers can be formed to have reduced widths. Thus, if a required breakdown voltage is the same, dopant concentrations of the respective semiconductor layers can be increased and a resistance value of the wafer can be reduced. In addition, a space portion remaining in the end is buried with an insulating layer, so that a defect can be avoided in a junction surface of the epitaxial layers.

Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and an aromatic ring-containing compound, the aromatic ring-containing compound including at least one of a moiety represented by the following Chemical Formula 1 and a moiety represented by the following Chemical Formula 2:

Abstract: A method of manufacturing double-sided semiconductor die by performing a first plurality of processes to a first side of a wafer and performing a second plurality of processes to a second side of the wafer, thereby forming at least a first semiconductor device on the first side of the wafer and at least a second semiconductor device on the second side of the wafer. The wafer may be cut to form a plurality of die having at least one semiconductor device on each side.

Abstract: An interconnect is disclosed with enhanced immunity of electrical conductivity to defects. The interconnect includes a material with charge carriers having topological surface states. Also disclosed is a method for fabricating such interconnects. Also disclosed is an integrated circuit including such interconnects. Also disclosed is a gated electronic device including a material with charge carriers having topological surface states.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form superimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract: Integrated-circuit chips are fabricated according to a process wherein weak portions are formed in a substrate wafer surrounding a plurality of locations. An integrated-circuit chip is defined at each location by destroying the weak portions so as to singulate integrated-circuit chips.

Abstract: A hard mask composition, a method of forming a pattern, and a semiconductor integrated circuit device, the hard mask composition including a solvent; and a compound, the compound including a structural unit represented by the following Chemical Formula 1:

Abstract: Thermal communication of matched transistors formed in lower electrical resistance subregions of first and second active substrate regions is provided by thermally conductive members formed to extend over isolation regions between higher electrical resistance subregions of the first and second regions. In one form, thermal communication is done, with or without contacts, through insulating layers to metal layers formed over the substrate. In another form, thermal communication is done through a polysilicon layer formed over the substrate.

Abstract: To improve a performance of a semiconductor device having a capacitance element. An MIM type capacitance element, an electrode of which is formed with comb-shaped metal patterns composed of the wirings, is formed over a semiconductor substrate. A conductor pattern, which is a dummy gate pattern for preventing dishing in a CMP process, and an active region, which is a dummy active region, are disposed below the capacitance element, and these are coupled to shielding metal patterns composed of the wirings and then connected to a fixed potential. Then, the conductor pattern and the active region are disposed so as not to overlap the comb-shaped metal patterns in the wirings in a planar manner.

Abstract: Provided is an IC package.

Abstract: A contact plug 40 electrically connected to an impurity diffusion region between sidewalls of an adjacent pair of memory cells 1 is provided to pass through an interlayer dielectric film 18. A side wall of a contact hole 41 is covered with a sealing film 42 denser than the interlayer dielectric film 18. The contact plug 40 includes a barrier metal film 43 formed to cover a surface of the sealing film 42 and a bottom surface portion of the contact hole 41 and a metal plug 44 embedded in the contact hole 41 in a state surrounded by the barrier metal film 43.

Abstract: A method for tone inversion for integrated circuit fabrication includes providing a substrate with an underlayer on top of the substrate; creating a first pattern, the first pattern being partially etched into a portion of the underlayer such that a remaining portion of the underlayer is protected and forms a second pattern, and such that the first pattern does not expose the substrate located underneath the underlayer; covering the first pattern with a layer of image reverse material (IRM); and etching the second pattern into the substrate.

Abstract: According to one exemplary embodiment, a power managing semiconductor die with reduced power consumption includes a power island including an event detection block and an event qualification block. The event detection block is configured to activate the event qualification block in response to an input signal initiated by an external event. The input signal is coupled to the event detection block, for example, via a bond pad situated in an I/O region of the power managing semiconductor die. The event qualification block is configured to determine if the external event is a valid external event. The event qualification block resides in a thin oxide region and the event detection block resides in a thick oxide region of the semiconductor die. The power managing semiconductor die further includes a power management unit configured to activate the event qualification block in response to power enable signal outputted by the event detection block.

Abstract: A diode comprises a P-type well formed in a semiconductor substrate, at least one N-type impurity doping area formed in the P-type well, an isolation area formed to surround the N-type impurity doping area, a P-type impurity doping area formed to surround the isolation area, first contacts formed in the N-type impurity doping area in a single row or a plurality of rows, and second contacts formed in the P-type impurity doping area in a single row or a plurality of rows, wherein pin resistance can be adjusted through changing any one of a distance between the N-type impurity doping area and the P-type impurity doping area, a contact pitch between the first contacts, and a contact pitch between the second contacts.

Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.

Abstract: A standard cell library includes a first power rail, a second power rail, a third power rail, a first standard cell, and second standard cells. The first power rail extends in a first direction. The second power rail extends in the first direction, and is spaced apart from the first power rail by a predetermined spacing in a second direction perpendicular to the first direction. The third power rail extends in the first direction between the first power rail and the second power rail. The first standard cell has at least one cell having a first cell height, and is arranged between the first power rail and the second power rail. The second standard cells have at least two cells, each having a second cell height, that are in contact with each other in the second direction, and are in contact with the first standard cell in the first direction.

Abstract: Provided is a method for generating, and for connecting in series, stripe-shaped elements, wherein less space is required for the series connection as compared to the prior art.

Abstract: A method of forming an isolation layer of a semiconductor device is disclosed herein, the method comprising the steps of providing a semiconductor substrate in which a tunnel insulating layer and a charge storage layer are formed on an active area and a trench is formed on an isolation area; forming a first insulating layer for filling a lower portion of the trench; forming a porous second insulating layer on the first insulating layer for filling a space between the charge storage layers; forming a third insulating layer on a side wall of the trench and the second insulating layer, the third insulating layer having a density higher than that of the second insulating layer; and forming a porous fourth insulating layer for filling the trench.

Abstract: This patent pertains to a new technique of increasing the amount of energy absorbed by an antenna. It accomplishes this by broadcasting a spike that attracts the signal when the fields of its oscillating charge are at their strongest.

Abstract: A method for manufacturing a semiconductor device includes forming an N-well and a P-well formed in a semiconductor substrate. An isolation layer may be formed in the semiconductor substrate. At least one dummy active pattern may be formed in a boundary area between the N-well and the P-well. A salicide blocking layer may be over the upper surface of the at least one dummy active pattern. A non-salicide region may be formed over the upper surface of the at least one dummy active pattern by carrying out a salicide process over the semiconductor substrate provided with the salicide blocking layer.

Abstract: A semiconductor device having strain material is disclosed. In a particular embodiment, the semiconductor device includes a first cell including a first gate between a first drain and a first source. The semiconductor device also includes a second cell adjacent to the first cell. The second cell includes a second gate between a second drain and a second source. The semiconductor device further includes a shallow trench isolation area between the first source and the second source. A first amount of strain material over the first source and over the second source is greater than a second amount of strain material over the first drain and over the second drain.

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

Abstract: A semiconductor on insulator (SOI) wafer includes a semiconductor substrate having first and second main surfaces opposite to each other. A dielectric layer is disposed on at least a portion of the first main surface of the semiconductor substrate. A device layer has a first main surface and a second main surface. The second main surface of the device layer is disposed on a surface of the dielectric layer opposite to the semiconductor substrate. A plurality of intended die areas are defined on the first main surface of the device layer. The plurality of intended die areas are separated from one another. A plurality of die access trenches are formed in the semiconductor substrate from the second main surface. Each of the plurality of die access trenches are disposed generally beneath at least a respective one of the plurality of intended die areas.

Abstract: Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

Abstract: An electronic component includes a high voltage switching transistor encased in a package. The high voltage switching transistor comprises a source electrode, a gate electrode, and a drain electrode all on a first side of the high voltage switching transistor. The source electrode is electrically connected to a conducting structural portion of the package. Assemblies using the abovementioned transistor with another transistor can be formed, where the source of one transistor can be electrically connected to a conducting structural portion of a package containing the transistor and a drain of the second transistor is electrically connected to the second conductive structural portion of a package that houses the second transistor. Alternatively, the source of the second transistor is electrically isolated from its conductive structural portion, and the drain of the second transistor is electrically isolated from its conductive structural portion.

Abstract: The invention relates to multi-planar logic components in a three-dimensional (3D) integrated circuit (IC) apparatus configuration. A multi-planar integrated circuit connected by through silicon vias is configured to connect microprocessor, FPGA and memory components. The integrated circuit components may be on tiles of layers of the 3D IC.

Abstract: A semiconductor integrated circuit includes a first semiconductor substrate in which a part of an analog circuit is formed between the analog circuit and a digital circuit which subjects an analog output signal output from the analog circuit to digital conversion; a second semiconductor substrate in which the remaining part of the analog circuit and the digital circuit are formed; and a substrate connection portion which connects the first and second semiconductor substrates to each other. The substrate connection portion transmits an analog signal which is generated by a part of the analog circuit of the first semiconductor substrate to the second semiconductor substrate.

Abstract: It is an object of the present invention to provide a micro-electro-mechanical-device having a microstructure and a semiconductor element over one surface. In particular, it is an object of the present invention to provide a method for simplifying the process of forming the microstructure and the semiconductor element over one surface. A space in which the microstructure is moved, that is, a movable space for the microstructure is formed by procecssing an insulating layer which is formed in a process of forming the semiconductor element. The movable space can be formed by forming the insulating layer having a plurality of openings and making the openings face each other to be overlapped each other.

Abstract: Isolation of III-nitride devices may be performed with a dopant selective etch that provides a smooth profile with little crystal damage in comparison to previously used isolation techniques. The dopant selective etch may be an electro-chemical or photo-electro-chemical etch. The desired isolation area may be identified by changing the conductivity type of the semiconductor material to be etched. The etch process can remove a conductive layer to isolate a device atop the conductive layer. The etch process can be self stopping, where the process automatically terminates when the selectively doped semiconductor material is removed.

Abstract: A method and structure for uncovering captive devices in a bonded wafer assembly comprising a top wafer and a bottom wafer. One embodiment method includes forming a plurality of cuts in the top wafer and removing a segment of the top wafer defined by the plurality of cuts. The bottom wafer remains unsingulated after the removal of the segment.

Abstract: A fuse structure includes a substrate, a fuse conductive trace disposed closer to a first chip surface than to a second chip surface facing away from the first chip surface, a metallization layer on the substrate disposed on a side of the fuse conductive trace facing away from the first chip surface, and a planar barrier multilayer assembly disposed between the fuse conductive trace and the metallization layer and including multiple barrier layers of different materials, wherein the fuse conductive trace, the metallization layer and the barrier multilayer assembly are arranged such that when cutting the fuse conductive trace and the barrier multilayer assembly, a first area of the metallization layer is electrically isolated from a second area of the metallization layer.

Abstract: A semiconductor device includes an inverter having an NMOSFET and a PMOSFET having sources, drains and gate electrodes respectively, the drains being connected to each other and the gate electrodes being connected to each other, and a pnp bipolar transistor including a collector (C), a base (B) and an emitter (E), the base (B) receiving an output of the inverter.

Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.

Abstract: A semiconductor device comprising: a first single crystal silicon layer comprising first transistors, first alignment mark, and at least one metal layer overlying said first single crystal silicon layer, wherein said at least one metal layer comprises copper or aluminum more than other materials; a second layer overlying said at least one metal layer, said second layer comprising second transistors, second alignment mark, and a through via through said second layer, wherein said through via is a part of a connection path between said first transistors and said second transistors, wherein alignment of said through via is based on said first alignment mark and said second alignment mark and effected by a distance between said first alignment mark and said second alignment mark.

Abstract: A word line driver includes an active area having a length that extends in a first direction over a semiconductor substrate. A plurality of fingers formed over an upper surface of the active area. Each of the plurality of fingers has a length that extends in a second direction and forms a MOS transistor with a portion of the active area. A first dummy structure is disposed between an outer one of the plurality of fingers and an edge of the semiconductor substrate. The first dummy structure includes a portion that is at least partially disposed over a portion of the active area.

Abstract: A semiconductor device including reentrant isolation structures and a method for making such a device. A preferred embodiment comprises a substrate of semiconductor material forming at least one isolation structure having a reentrant profile and isolating one or more adjacent operational components. The reentrant profile of the at least one isolation structure is formed of substrate material and is created by ion implantation, preferably using oxygen ions applied at a number of different angles and energy levels. In another embodiment the present invention is a method of forming an isolation structure for a semiconductor device performing at least one oxygen ion implantation.

Abstract: An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

Abstract: A silicon based module, including: a substrate; a first chip assembly fixed to the substrate, the first chip assembly including a first silicon chip and a first driver die having electrical circuitry; and a second chip assembly fixed to the substrate, the second chip assembly including a second silicon chip and a second driver die having electrical circuitry. Portions of the first and second chip assemblies are aligned in a longitudinal direction for the substrate; and portions of the first and second silicon chips are aligned in a width direction orthogonal to the longitudinal direction. Method for forming a silicon based module.

Abstract: A semiconductor integrated circuit having a diode element includes a diffusion layer which constitutes the anode and two diffusion layers which are provided on the left and right sides of the anode and which constitute the cathode, such that the anode and the cathode constitute the diode. A well contact is provided to surround both the diffusion layers of the anode and cathode. Distance tS between a longer side of the well contact and the diffusion layers of the cathode is shorter, while distance tL between a shorter side of the well contact and the diffusion layers of the anode and cathode is longer (tL>tS). Accordingly, the resistance value between the diffusion layer of the anode and the shorter side of the well contact is larger, so that the current from the diffusion layer of the anode is unlikely to flow toward the shorter side of the well contact.

Abstract: The present invention relates to a surface mountable acoustic transducer system, comprising one or more transducers, a processing circuit electrically connected to the one or more transducers, and contact points arranged on an exterior surface part of the transducer system. The contact points are adapted to establish electrical connections between the transducer system and an external substrate, the contact points further being adapted to facilitate mounting of the transducer system on the external substrate by conventional surface mounting techniques.

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract: A method of implementing a capacitor in an integrated circuit package is disclosed. The method comprises coupling the capacitor to a first surface of a substrate of the integrated circuit package; positioning an integrated circuit die over the capacitor, wherein the integrated circuit die has a first plurality of solder bumps and a second plurality of solder bumps separated by a region having no solder bumps; coupling the integrated circuit die to the first surface of the substrate over the capacitor, wherein the region having no solder bumps is positioned over the capacitor; and encapsulating the integrated circuit die and the capacitor.