Abstract: A digital-to-analog converter (DAC) disposed in a data transmission path to convert data from a digital format to an analog format to be transmitted is powered down during a receive mode of operation for a wireless communication device. Likewise, an analog-to-digital converter (ADC) disposed in a data reception path to convert received data from an analog format to a digital format is powered down during a transmit mode of operation.

Abstract: A method and apparatus for digitizing a data signal, the method comprising the steps of receiving an input analog data signal, splitting the received input analog data signal into a plurality of split signals, and mixing at least one of the split signals with a predetermined periodic function with a predetermined frequency. The split signals are then digitized and combined mathematically to form a single output data stream that is a substantially correct representation of the original input signal.

Abstract: A signal converting apparatus for integrating an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC) and an integration unit thereof are provided. The present invention integrates ADC and DAC, that do not operate simultaneously, into a signal converting apparatus (SCA), wherein a control signal decides whether an analog-to-digital mode or a digital-to-analog mode is selected. By sharing the operational amplifiers and other components in the SCA, the chip area and the cost are significantly reduced. In addition, in the integration unit, by switching a plurality of capacitor sets with various capacitances, the capacitance coefficients required for switching ADC and DAC are obtained.

Abstract: In an A/D converter having a single flux quantum circuit having a flux quantum as an information carrier, a superconducting amplifier circuit driven by an AC current, and a semiconductor circuit, the operations of the circuits are synchronized with each other and a data signal from the single flux quantum circuit is transmitted to the semiconductor circuit. An AC current as the power source of a superconducting amplifier circuit is inputted as a master clock signal to the single flux quantum circuit and the semiconductor circuit to synchronize the operations of the circuits with the master clock signal. The single flux quantum circuit has a clock signal frequency multiplier circuit, a demultiplexing circuit and a memory circuit.

Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.

Abstract: An apparatus is provided for measuring an output of a high-speed data transmission circuit. The apparatus includes a programmable reference voltage generator operable to generate a reference voltage that is variable between a plurality of levels. The apparatus also includes a quantizer to quantize an output of the high-speed data transmission circuit relative to the reference voltage level input thereto. Also included is a clock generator operable to generate a clock having a transitioning time (rise-time, fall-time or both) that is less than one quarter of a minimum switching period of the output of the circuit. Finally, the apparatus includes a sampler operable to sample the quantized output with the clock to produce a plurality of samples which measure the output of the circuit.

Abstract: A signal processing circuit can obtain a ratiometric output with high precision and high responsiveness in a relatively easy and simple way. A pulse generation circuit generates a pulse signal corresponding to an input signal. An integration part generates an integrated voltage having a time slope proportional to an input voltage with a duration specified by the pulse signal being set as an integration period. A hold part holds and outputs a difference voltage between a start voltage and an end voltage of the integrated voltage in the integration period. The integration period is specified at the timing of the pulse signal output from the pulse output circuit, and a ratiometric output is generated by sample holding the integral signal.

Abstract: A digital-to-analog converter system is provided that controls a phase of an output signal produced by a digital-to-analog converter (DAC). A digital input signal and a phase control signal are each applied to the DAC. The DAC then produces an analog output signal based on the input signal and the phase control signal, wherein the analog signal comprises an output with a frequency and a phase component. The DAC further produces a phase adjustment signal that is conveyed to an auxiliary circuit that determines a phase difference between a reference signal and the phase adjustment signal and generates the phase control signal based on the phase difference, wherein a phase of the analog output signal is adjusted based on the phase control signal. By controlling the phase of an analog output signal of a DAC, DAC-to-DAC skew may be minimized.

Abstract: A method and apparatus for calibrating a current source to a reference current through the use of 1-bit current comparisons. A temporary current source is first calibrated to the reference current, which allows an input offset current generated by the current comparator to be memorized. The current to be calibrated is then fine-tuned to the temporary current within specified limits, which effectively cancels comparison error that is generated by the input offset current.

Abstract: The current cell matrix includes 63 upper current cells and one lower current cell. Each of the current cells has 4 constant current transistors having the same size with respect to each other. The upper current cell outputs drain currents of all the constant current transistors when the cell is selected by the upper decoder. The lower current cell outputs drain currents of none, one or two constant current transistors in accordance with the select signal from the lower decoder. The analog output terminal combines and outputs the currents of the selected constant current cells. The current cell type digital-to-analog converter has the decreased differential linearity error and the decreased integral linearity error.

Abstract: An analog portion of a mixed-mode integrated circuit system includes a plurality of analog input cells, a plurality of analog output cells, and an interconnect array. The input cells are configured to program analog functions. The output cells are configured to provide Analog and digital outputs corresponding to the programmed analog functions. The interconnect array processes the programmed analog functions into signals indicative of the analog functions. The interconnect array selectively provides the signals to the plurality of analog output cells.

Abstract: A method and apparatus for digitizing a data signal. An input analog data signal, is received and split into a plurality of split signals. At least one of the split signals is mixed with a predetermined periodic function with a predetermined frequency. The split signals are then digitized and combined mathematically to form a single output data stream that is a substantially correct representation of the original input signal.

Abstract: A sigma-delta modulator includes a summing junction that receives an input signal. A plurality of integrators are arranged in series, the integrators output an integrated signal value to a multi-input quantizer. The multi-input quantizer has a plurality of comparators each with switched capacitor inputs. The multi-input quantizer outputs a quantized signal to a multi-bit feedback DAC that drives the summing junction.

Abstract: A training method of a digital-analog converter is provided. The digital-analog converter comprises a plurality of parallel capacitors, each of which is floatingly coupled to a plurality of correcting capacitors. Two voltages outputted from the digital-analog converter are received and compared. When a latter output voltage is lower than or equal to a former output voltage, the correcting capacitor is used to correct the capacitor corresponding to the latter output voltage until the latter output voltage is higher than the former output voltage. When the latter output voltage is higher than the former output voltage, a new voltage is outputted from the digital-analog convert and compared with the latter output voltage. The steps of comparing and correcting are repeated until every latter output voltage is higher than every former output voltage.

Abstract: DC offset is compensated for in an analog front end (AFE) circuit having an amplifier and an analog-to-digital converter (ADC). First data processed by the ADC are low pass filtered and estimated DC offset data of the ADC are obtained in ADC DC offset calibration mode. Second data processed by the ADC and the amplifier are low pass filtered, and a first DC offset of the ADC are substantially removed from the filtered second data by subtracting the estimated DC offset data from the filtered second data, thereby obtaining second compensated DC offset data of the amplifier in an amplifier DC offset calibration mode. The second compensated DC offset data is iteratively improved and first compensated DC offset data of the amplifier are obtained. The first compensated DC offset data are transformed into an analog signal, and the analog signal is subtracted from an input signal of the amplifier during operation mode.

Abstract: A system and method for converting an analog voltage signal to a digital representation at high speeds, known as an analog to digital converter (A/D converter), is provided in the form of an N-bit A/D converter, made by N superconducting, preferably HTC, transmission lines. The N lines are arranged adjacently and in parallel with each other. On each line 2N?1 Josephson Junctions (JJs) are embedded in series. The JJs form a matrix over the configuration of the N superconducting transmission lines. A scanning electron beam is made to impinge on this arrangement across the lines at a high frequency, while it is deflected by the applied voltage signal along the direction of the lines. A voltage step is generated upon hitting any one of the JJs. In this manner upon each cross-scanning of the beam, an N-bit step voltage pattern is generated on the lines.

Abstract: A waveform acquisition system that captures and digitizes a wideband electrical signal through a bank of front end filters, frequency down converters, and conventional digitizers (A/D converters). A software algorithm reconstructs the composite input signal and applies the necessary corrections to remove the effects of hardware impairments. This approach is possible because it uses a class of filters that exhibit the quality of perfect waveform reconstruction, allowing signals whose spectral components overlap multiple filter bands, to be faithfully reconstructed. A calibration generator switched into the input port serves as a reference for quantifying and removing hardware errors. The channelized analog-to-digital converter (ADC) effectively multiplies the bandwidth and sampling rate of the conventional digitizer performance in a single channel by the number of channels in the system.

Abstract: An AD converter capable of achieving both an improved processing speed and a reduced circuit area in good balance. The AD converter pipelines analog-to-digital conversion by using a two-stage configuration consisting of a first conversion unit, or the prior stage, and a second conversion unit, or the subsequent stage. The first conversion unit is a conversion unit of noncyclic type. The second conversion unit is a conversion unit of cyclic type. The second conversion unit is given a conversion processing speed higher than that of the first conversion unit so that the second conversion unit performs cyclic processing twice while the first conversion unit performs conversion processing once.

Abstract: An electronic circuit for the direct conversion of a capacitive transducer signal to a digital delta-sigma bit stream is disclosed. The electronic circuit is comprised of two functional blocks, in which the variable transducer capacitance is first transformed and represented by a frequency modulated (FM) signal by a variable frequency oscillator, and subsequently converted to a digital delta-sigma representation using a frequency delta-sigma modulator. The electronic circuit eliminates any need for analog components in conjunction with the capacitive transducer, and hence simplifies the front-end circuit for applications where digital signal processing (DSP) is used. The output bit stream of the electronic circuit is similar to other analog to digital delta-sigma converters, and can therefore be processed using similar digital techniques.

Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.

Abstract: A system and method for analog-to-digital conversion using digital pulse width modulation (PWM) is disclosed. The method and system according to the disclosed invention converts an analog input signal to a digital signal in pulse code modulated (PCM) form. The disclosed invention uses a feedback circuit to perform PWM of the analog input signal. The PWM signal is then decimated to obtain the digital signal in PCM form. The system according to the disclosed invention requires lower operating frequency and dissipates lesser power than prior art systems providing the same sampling frequency and resolution. The operation at a lower frequency is achieved by obtaining two samples from every pulse of the PWM signal; the first sample being obtained from the right duty ratio, and the second sample being obtained form the left duty ratio. Further, the disclosed invention has lesser implementation complexity and higher signal-to-noise ratio than prior art.

Abstract: When digitizing a voltage, a capacitor is charged, through an impedance, to a voltage value (Um) dependent on the voltage to be digitized. The limits of that one of a plurality of voltage ranges in which said voltage value (Um) lies, are ascertained, and the two limits of that voltage range are defined as a first limit and second limit; the voltage at the capacitor is modified to the first limit by a charge modification circuit containing an impedance, and a first time interval needed therefor is identified; the voltage at the capacitor is modified to the second limit; the voltage at the capacitor is modified from the second to the first limit via the charge modification circuit. A seond time interval needed therefor is identified. Based on values of the first time interval and second time interval, a digital value is calculated, which serves as an indication of how much the voltage value (Um) at the capacitor differs from one of said two limits.

Abstract: A system for determining impulse events of an asset by sampling and digitizing a complex signal sensed by a transducer monitoring the asset into a digitized signal with a sampling device operatively coupled to the transducer, transforming the digitized signal into a plurality of maximum and minimum value pairs each pair having an associated location correlated to a relative movement of a moving member of the asset with a processor operatively coupled to the sampling device, and a monitor and/or a computerized condition monitor having the processor integrally formed therewith or operatively coupled thereto for comparing at least one of the plurality of maximum and minimum value pairs and its respective location to at least one known value for determining impulse events based on the comparison step for providing asset protection.

Abstract: An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Abstract: A method and apparatus for communicating digital data on a bus arrangement is provided. The bus arrangement includes one or more encoding circuits, decoding circuits, and transmission mediums. Each encoding circuit includes a digital-to-analog converter circuit communicatively coupled to a multi-phase analog encoding circuit. Each decoding circuit corresponds to a respective encoding circuit and includes a multi-phase analog decoding circuit communicatively coupled to an analog-to-digital converter circuit, and a multiplexing circuit communicatively coupled to the analog-to-digital converter circuit. Each respective encoding circuit and a corresponding decoding circuit is communicatively coupled by a transmission medium. Digital data is converted to at least one analog signal and encoded upon a radio frequency carrier signal. The carrier signal is transmitted to a destination where it is decoded and the digital data reconstituted.

Abstract: CMP methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced.

Abstract: A power supply particularly suitable for high-speed optical data transmission employs readily available components to achieve desired voltage tolerances. More specifically, a voltage signal supplied to a load is converted into a digital signal and provided to a processor that derives a digital correction signal from the digital signal. The digital correction signal is then converted to an analog correction signal and is used by a feedback control circuit in the power supply to regulate the output voltage.

Abstract: An operational amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a first stage circuit operate in response to a clock signal. An operation amplifier, a sub A/D converter, a D/A converter, and an operation amplifier in a second stage circuit operate in response to a clock signal having a frequency three times as high as that of the first clock signal. An analog signal output from the operational amplifier in the first stage is applied to an input node in the second stage circuit through a switch. An analog signal output from an operational amplifier in the second stage circuit is applied to an input node in the second stage circuit through a switch.

Abstract: A communications system includes physical layer hardware and a processing unit. The physical layer hardware is adapted to communicate data over a communications channel in accordance with a plurality of control codes. The physical layer hardware is adapted to demodulate an incoming analog signal to generate a digital receive signal and modulate a digital transmit signal to generate an analog transmit signal. The processing unit is adapted to execute a privileged driver for interfacing with the physical layer hardware. The privileged driver includes program instructions for implementing a protocol layer to decode the digital receive signal, encode the digital transmit signal, and configure the physical layer hardware for receipt of the digital receive signal and transmission of the digital transmit signal based on the plurality of control codes.

Abstract: A method for controlling in closed loop an analog system generating an output signal from a control signal, wherein the control signal is a series of digital values, each new digital value being determined based on the difference between a signal linked to the output signal and the last determined value of the control signal multiplied by a selected factor. The present invention also relates to a device for controlling an analog system generating an analog output signal.

Abstract: A method and apparatus of processing waveforms acquired in a waveform digitizing instrument utilizing multiple, interleaved digitizing elements is provided to improve the accuracy of the data acquired is provided. The present method utilizes measured analog-to-digital converter frequency response characteristics to generate sets of coefficients. When data is acquired by a waveform digitizing system, the present method utilizes these coefficients to correct the waveform, thus undoing the adverse effects of the non-ideal frequency response characteristics, resulting in a waveform acquired with higher fidelity. The waveform resulting from this method is a waveform that more closely represents the signal sampled by the digitizing system.

Abstract: The invention relates to an arrangement for converting a binary input signal corresponding to an n-bit thermometer code into a binary output code different therefrom,

Abstract: A method for high speed communications uses an inventive Q-Gray code. The Q-Gray code simplifies the hardware needed to convert analog Q-Gray code signals to digital signals. An analog-to-digital converter can use a plurality of comparators for receiving the multilevel signal and a plurality of decoder blocks coupled to comparators for decoding the multilevel signal. Each decoder block can include an equal number of inputs. Specifically, each decoder block can also include a parity detector with an equal number of inputs. Each decoder block can also employ a bank of identical parity detectors relative to another decoder block. Each comparator of the analog to digital converter can have an individually or externally adjustable (or both) threshold level.

Abstract: The current cell matrix includes 63 upper current cells and one lower current cell. Each of the current cells has 4 constant current transistors having the same size with respect to each other. The upper current cell outputs drain currents of all the constant current transistors when the cell is selected by the upper decoder. The lower current cell outputs drain currents of none, one or two constant current transistors in accordance with the select signal from the lower decoder. The analog output terminal combines and outputs the currents of the selected constant current cells. The current cell type digital-to-analog converter has the decreased differential linearity error and the decreased integral linearity error.

Abstract: A receiving apparatus and a receiving method for receiving a signal modulated by a multi-carrier modulation scheme for transmitting the information code using a plurality of carriers. The signal contains data carriers and regularly-inserted pilot carriers fixed in amplitude and phase. The cross-correlation between the received signals with the data carriers distant to such an extent as to eliminate the correlation with each other is calculated, and based on the result of the cross-correlating operation by the correlating operation unit, the signal correlation component as related to the pilot carriers is extracted.

Abstract: An apparatus and method for signal processing in a root-mean-square (RMS) meter. In representative embodiments, the root-mean-square (RMS) meter includes an RMS converter having a converter input and a converter output. The RMS converter converts a time varying signal applied to the converter input to a signal at the converter output. The value of the signal at the converter output is indicative of the RMS value of the applied signal. The signal at the converter output comprises a non-time varying component and a time varying component as determined by a time constant of the RMS converter. The RMS meter further includes an inverting amplifier having an inverter input and an inverter output. The converter output is connected to the inverter input. In addition, the RMS meter includes a switch having first, second, and central contacts. The converter output is connected to the first contact, and the inverter output is connected to the second contact.

Abstract: Tones that are generated by a telephone or PC (such as DTMF tones) and subject to loss or noise during generation or during transmission along a medium are detected and replaced with substantially noise-free and distortionless digital signals. In one embodiment, the replacement of the tones is done in a modem embodied in an Internet telephony Gateway/Terminal, such as in a network access server coupling a time division multiplexed telephone line to a packet-switched network. The replacement of the tones may also be performed in any suitable device that provides an interface between a time division multiplexed transmission medium and a packet switched data network, such as in the modems of a cellular telephone network to Internet network access server.

Abstract: A system, method and apparatus for triggering a plurality of test and measurement instruments in a substantially simultaneous manner.

Abstract: An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Abstract: A decimation filter in which a coefficient word length of a last-stage FIR filter is shorter than that which attains a necessary attenuation rate, and an interpolation filter in which a coefficient word length of a first-stage FIR filter is the same. The coefficient is arranged such that a region in which attenuation is insufficient is caused intensively around a Nyquist frequency. The attenuation in such a region relative to the first or last-stage FIR filter is enhanced so as to ensure sufficient attenuation, by its preceding or following FIR filter. As a result, sufficient attenuation is maintained in an inhibition region while maintaining a relatively small circuit size.

Abstract: The system includes a unipolar A/D converter, which samples analog signal inputs thereto, the A/D converter being used in a protective relay for electric power systems. The unipolar A/D converter is responsive to input voltage values and current values from the power line to produce corresponding digital signals. The A/D converter has a ground pin voltage reference at least as negative as the most negative point of the input signal to be processed.

Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.

Abstract: A data transmission system is provided including a clock source, semiconductor integrated circuit devices, a controller configured to control the semiconductor integrated circuit devices, and a clock signal pass connected to the clock source, the controller and the semiconductor integrated circuit devices. The data transmission system may include a daisy chain data pass connected to the controller and the semiconductor integrated circuit devices, and a two-way data strobe signal pass connected to the controller and the semiconductor integrated circuit devices. The clock source, the semiconductor integrated circuit devices and the controller transmit and receive therebetween a clock signal via the clock signal pass. The semiconductor integrated circuit devices and the controller transmit and receive therebetween multi-valued current data via the daisy chain data pass, and a data strobe signal in the form of a binary voltage signal via the two-way data strobe signal pass.

Abstract: CMP systems and methods in which a polishing pad is moved relative to a wafer and a retainer ring implement instructions for applying required pressure to the wafer for CMP operations. Accuracy of computations of the pressures, and of conversion of the pressure to force, is improved without use of high resolution components, such as high resolution digital devices. Such improved accuracy is achieved using both digital and analog operations, and by converting values of required pressure or force from one set of units to a second set of units and then back to the first set of units. A quantization process is performed using data processed by average resolution digital devices. The process transfers both pressure/force scale and pressure/force set point data between separate processors to obtain computed values of pressure and force having acceptable accuracy, such that quantization errors are eliminated or significantly reduced.

Abstract: A method is provided for analog/digital converting of at least one analog low-frequency signal with an analog/digital converter which can detect only an analog signal with a frequency above a predetermined border frequency value, wherein at least one analog low-frequency signal and at least one analog high-frequency signal are provided. An analog intermediate signal is generated from said analog low-frequency signal(s) and said analog high-frequency signal(s) and is input to the analog/digital converter. The analog intermediate signal is converted into a digital intermediate signal, and a digital low-frequency signal corresponding to said analog low-frequency signal is determined from the digital intermediate signal.

Abstract: A system for measuring signals in a non-linear network is provided which reduces the reliance on hardware and processing support when correcting for A/D offset by performing a pair of dual slope measurement cycles with an integrating analog to digital converter (ADC) circuit. Each of the measurement cycles has at least four phases including a first integrating phase and a first de-integrating phase followed by a second integrating phase and a second de-integrating phase. The system further includes an ADC controller operatively communicative with the integrating ADC circuit for detecting when the first count value is reached during the second de-integrating phase and then resetting the second count value in response to this detection so that the second count value is offset corrected at the end of the second de-integration phase. As a result, a difference calculation is automatically performed during the measurement cycle.

Abstract: A digital protective relay comprises a protective relay arithmetic processing unit for judging, based on a relay judgement quantity obtained by converting a system electric quantity into a digital value, whether in an operating state or in a non-operating state, and a time synchronizing unit for inputting a time reference signal from outside and synchronizing an internal timer of the digital protective relay with an external reference time. The time synchronizing unit includes an A/D converting unit for A/D converting the time reference signal inputted from outside with a resolution of at least 2 bits, and a decoding unit for decoding a time code signal by making a judgement as to a magnitude of the time reference signal with respect to a digital value obtained by the A/D converting unit.

Abstract: A highly efficient analog-to-digital (A/D) converter circuit that converts an external analog signal sequentially generated from an external analog signal source into an n-bit digital data signal (n is an integer equal to or more than two) includes a digital-to-analog (D/A) converter circuit that converts an n-bit digital data signal into an analog signal and outputting the analog signal from a first output terminal, a comparator that compares a signal level of an external analog signal supplied from an external device with a signal level of the analog signal outputted from the first output terminal, and a digital integrator circuit that digitally integrates a 1-bit digital data signal outputted from the comparator and thereby producing an n-bit digital data signal.

Abstract: A method of photonic analog-to-digital conversion including the steps of using an analog signal to modulate a laser, splitting the modulated optical output into 2N paths, attenuating the different paths along a gradient, then splitting each path again and recombining with an adjacent path in such a way that only one path has significant energy. An implementation architecture is also provided which includes a laser source, a modulator for modulating the laser source in accordance with an analog input signal, a first splitter section for splitting the modulated optical output into 2N paths, and for attenuating the different paths along a gradient, an interferometer section for splitting each path again and for recombining the signals in such a way that only one path has significant energy, and a decoder section for outputting a digital word corresponding to the analog input signal.

Abstract: An SMBus protocol is terminated at a personal computer and a remote-control connection control device for converting signals to data that can be received by each device inside a wired remote control is provided. The remote-control connection control device comprises an A/D converter and a register. After being stored in the register, data transmitted from a CPU as SDATA are outputted from SOUT as serial data and exercises direct control over both an LCD driver and a backlight. An analog signal inputted from the switch of the wired remote control is inputted to the remote-control connection control device as an AIN and after being converted into a digital value, the signal is read into the CPU as SDATA via an SMBus and the command is executed.