Abstract: A continuous time sigma delta analog to digital converter may use a finite impulse response filter for delay compensation. In some embodiments, the filter may be simplified by using only the first and/or second filter coefficients.

Abstract: The present invention relates to an alarm management system intended to be carried onboard an aircraft. More precisely, the invention is aimed at improving the certainty level relating to the integrity of the announcements of faults or information intended for the pilot and based on voice syntheses. For this purpose, the present invention proposes a device and a method for detecting the digital origin of an analog signal providing a validity signal (VAL) enabling the voice announcements made to the pilot to be rendered secure.

Abstract: A display device driving circuit includes: a grayscale signal output circuit, grayscale signal lines, a grayscale voltage output circuit, grayscale voltage lines, a digital-analog conversion circuit, a first to third switches. The grayscale signal output circuit outputs complementary signals as a digital grayscale signal. The grayscale signal lines receive the complementary signals. The grayscale voltage output circuit outputs analog grayscale voltages. The grayscale voltage lines receive the analog grayscale voltages. The digital-analog conversion circuit selects and outputs one of the analog grayscale voltages in response to the complementary signals. The first switch shuts off a first connection path between the grayscale signal output circuit and the digital-analog conversion circuit. The second switch shuts off a second connection path between the grayscale voltage output circuit and the digital-analog conversion circuit.

Abstract: A cyclic A/D converter 21 provides an amplification type noise cancellation process and cyclic A/D conversion in which a plurality of capacitors and an operational amplifier are shared without complicated processing. In the cyclic A/D converter 21, a gain stage 23 uses first to third capacitors 33, 35 and 37 and an operational amplifier circuit 39 to perform the process for noise cancellation and amplification to generate a difference signal between first and second signal levels. In the process for noise cancellation, the difference between the first signal level VR and the second signal level VS is generated. The amplification of this difference is carried out in conjunction with the process for noise cancellation. The gain stage 23 uses the first to third capacitors 33, 35 and 37 and the operational amplifier circuit 39 to perform the process for cyclic A/D conversion of the difference signal. A sub A/D converter circuit 25 receives a signal VOP from an output (e.g.

Abstract: In many applications, which use amplifiers that operate at less than 50% duty cycle, it would be advantageous to reduce the number amplifiers to reduce power consumption. Here, an amplifier is provided which is time multiplexed to accommodate multiple data paths. Additionally, reset circuitry or a reset mechanism is provided at the output terminals of this amplifier to briefly short the output terminals to generally prevent glitching that may result from switching between data paths.

Abstract: A television receiving system is disclosed, comprising an input terminal, a down-converter, an amplifier, an analog-to-digital converter (ADC), a demodulator, and an isolation circuit. The input terminal receives an RF signal. The down*converter, coupled to the input terminal, converts the RF signal to an intermediate frequency (IF) signal. The amplifier, coupled to the down-converter, amplifies the IF signal. The analog-to-digital converter, coupled to the amplifier, converts the amplified IF signal to digital data. The demodulator, coupled to the ADC, processes the digital data to generate baseband data. The isolation circuit, coupled between the amplifier and ADC, isolates the amplified IF signal from being affected by interference induced by the ADC.

Abstract: An image sensor circuit comprises a pixel cell array having a plurality of pixel cells arranged along a plurality of column lines, a plurality of readout circuits connected to said column lines, each of which comprises an analog-to-digital converter and a multiplexer for selectively applying an output signal of one of said column lines to said analog-to-digital converter. Between two of said column lines which are connected to a first one of said readout circuits located at a first side of said pixel cell array, there is a column line which is connected to a second one of said readout circuits located at a second side of said pixel cell array opposite to said first side.

Abstract: Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.

Abstract: A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.

Abstract: Embodiments of the invention provide a digital-to-analog converter (DAC) that is configured to process upper data bits, a control data bit, and a lower data bit using two decoders and a control logic. The resulting DAC provides high resolution output using a minimum circuit area. Embodiments of the invention also provide a sample and hold circuit for a DAC that reduces the effects of parasitic capacitance at the input of an operational amplifier (OP-AMP).

Abstract: A sensor system for generating sample analog signals for processing by a signal processing circuit that utilizes non-constant weights includes a plurality of signal generating elements and a switching network having a plurality of switches operably coupled to the plurality of signal generating elements. The switching network is configured to switch the plurality of signal generating elements between a plurality of different configurations. The system includes a dynamic element matching (DEM) control system for controlling the switch network to implement a second order DEM rotation scheme in which the plurality of signal generating elements are switched to each configuration in the plurality of configurations in a first sequence and then switched to each configuration in the plurality in a second sequence, the second sequence being the reverse of the first sequence.

Abstract: An apparatus for generating an image of touch on or about a touch-sensitive surface comprising a touch panel is disclosed. The touch panel can include a plurality of touch sensors configured for detecting one or more touch events occurring at distinct locations at about the same time. Each touch event can comprise a touching of an object against the touch-sensitive surface. A plurality of receive channels can be coupled to the touch panel for generating values representative of detected touch events. The receive channels can include a charge redistribution successive approximation register digital-to-analog converter (SAR ADC) configured to convert an analog waveform into a digital representation via a binary search and outputting the digital representation to an output register. The SAR ADC architecture can be such that it the dynamic input range can be scaled and offset adjusted.

Abstract: An architecture for use in wireless receiver applications, particularly for ADC conversion of received in-phase I and quadrature Q signals. A single ADC is shared to convert both signals, and the ADC input is alternately switched between the i and q signals. In an embodiment, the ADC is clocked at an increased sample rate, and the digital output signals are aligned to compensate for the phase difference resulting from the implementation of the single ADC.

Abstract: A data driver, including a first digital-to-analog converter configured to select two reference voltages of a plurality of reference voltages depending on upper bits of data, and a second digital-to-analog converter configured to divide the two reference voltages into a plurality of voltages and supply any one voltage of the two reference voltages and the divided voltages to an output terminal as a data signal depending on lower bits of the data, wherein the second digital-to-analog converter is configured to supply an intermediate gray scale voltage to the output terminal prior to supplying the data signal, the intermediate gray scale voltage having a voltage between the two reference voltages.

Abstract: A method and apparatus is described for recording and digitizing intensity profiles (IP) of the papillary structure of the skin with high intensity resolution using sensors S with low intensity resolution. For this purpose, a plurality of digital image signals (DS, DS1, DS2) of an identical subarea e.g. of a fingerprint are recorded, whereby the continuous intensity domain (KI) of the fingerprint is scanned in different intensity resolutions, and/or different portions (A1, A2) of said continuous intensity domain (KI) are mapped to discrete intensity domains of the single digital image signals (DS, D1, DS2). By the pixelwise combination of all digital image signals (DS, DS1, DS2), a digital fingerprint image signal (PS) is finally produced whose discrete intensity domain (DI) represents a larger portion of the continuous intensity domain (KI) of the fingerprint and/or has a higher resolution intensity than each single one of the digital image signals (DS, DS1, DS2).

Abstract: A direct sampling tuner includes a low noise amplifier and an optional dynamically configurable band pass filter coupled to the low noise amplifier. The optional filter is configured to pass a selected band of channels. The tuner further includes a relatively high accuracy, multi-bit analog-to-digital converter (“ADC”) coupled to the LNA or to the optional dynamically configurable band pass filter. The ADC operates at greater than about twice a frequency of a sampled signal. The ADC directly samples the spectrum of the selected channels at the Nyquist rate, thus avoiding image problems presented by conventional tuners.

Abstract: A method of digitizing an analog signal is provided, comprising the steps of separating the analog signal spanning a frequency range into a plurality of frequency bands, and then translating at least one of the signals to a lower frequency band in accordance with a local oscillator and digitizing the at least one translated signal with digitizing elements having a frequency range less than the analog signal frequency range. A fixed relationship of the phase of the local oscillator and a repetitive signal generated in accordance with a writing to a circular buffer of the digitized representation of the at least one of the plurality of frequency bands is then defined. Signals corresponding to the other of the plurality of frequency bands are digitized and written to corresponding circular buffers. Finally, a digital representation of the analog signal is formed from the digitized signals.

Abstract: A wireless local area network (WLAN) transceiving integrated circuit services voice communications in a WLAN with at least one other wireless device and includes a WLAN interface, a transcoder, and a switch box. The WLAN interface wirelessly communicates with at least one wireless device to receive inbound packetized audio data from the at least one wireless device and to transmit outbound packetized audio data to the at least one wireless device. The transcoder receives the inbound packetized audio data and converts the inbound packetized audio data to inbound Pulse Code Modulated (PCM) WLAN audio data. The WLAN interface also receives outbound PCM WLAN audio data and converts the outbound PCM WLAN audio data to the outbound packetized audio data. The switch box operably couples between the transcoder and a PCM bus, to which an audio COder/DECoder (CODEC) couples. A speaker and a microphone coupled to the audio CODEC.

Abstract: Certain aspects of a method and system for simultaneous FM transmission and FM reception using a shared antenna and a direct digital frequency synthesizer (DDFS) may be disclosed. In a FM transceiver that receives FM signals at a frequency f1 and transmits FM signals at a frequency f2, aspects of the method may include generating via a DDFS, a signal corresponding to a difference between f1 and f2 to enable simultaneous transmission and reception of FM signals via shared antenna.

Abstract: A data conversion system acquires samples of low frequency signal components of an applied analog signal at a first data conversion rate and samples of high frequency signal components of the applied analog signal at a second data conversion rate that is higher than the first data conversion rate. The data conversion system applies a first correction filter to the acquired samples of the low frequency signal components to provide a first filtered signal and applies a second correction filter to the acquired samples of the high frequency signal components to provide a second filtered signal. The data conversion system interpolates the first filtered signal to provide an interpolated signal, and sums the interpolated signal with the second filtered signal to provide an output signal.

Abstract: An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

Abstract: A communication device and the method thereof are disclosed in embodiments of the present invention. The communication device includes a level determining module, an digital to analog converter and an analog to digital converter. The level determining module determines a plurality of voltage levels and voltage intensity thereof according to an estimating signal to generate a first digital signal. The digital to analog converter converts the first digital signal into a pulse shaped analog signal according to the plurality of voltage levels and voltage intensity thereof. The analog to digital converter converts a first difference signal into a second digital signal wherein the first difference signal equals the result of subtracting the pulse shaped analog signal from a receiving signal.

Abstract: A cyclic A/D converter 21 provides an amplification type noise cancellation process and cyclic A/D conversion in which a plurality of capacitors and an operational amplifier are shared without complicated processing. In the cyclic A/D converter 21, a gain stage 23 uses first to third capacitors 33, 35 and 37 and an operational amplifier circuit 39 to perform the process for noise cancellation and amplification to generate a difference signal between first and second signal levels. In the process for noise cancellation, the difference between the first signal level VR and the second signal level VS is generated. The amplification of this difference is carried out in conjunction with the process for noise cancellation. The gain stage 23 uses the first to third capacitors 33, 35 and 37 and the operational amplifier circuit 39 to perform the process for cyclic A/D conversion of the difference signal. A sub A/D converter circuit 25 receives a signal VOP from an output (e.g.

Abstract: A comparator has a differential input stage, a current source coupled to the differential input stage for providing a tail current to one side of the differential input stage, and a differential load coupled to the differential pair and having at least one diode coupled load transistor per differential side. A load current through either one of the at least one diode coupled load transistor on either differential side is mirrored with a current mirror configuration to provide a current be fed to a respective node, each node being coupled to a respective variable biasing current source and a respective other side of the differential input stage, so as to provide a variable positive feedback to the differential input stage.

Abstract: Clock processors are provided to economically control system and data clocks in high-speed signal converters. The processors generally include at least one of a delay-locked loop, phase-locked loop or a duty cycle stabilizer which generates an error signal in its operation. In the example of a stabilizer, it is configured to respond to an input clock to initiate a first portion of each cycle of the system clock and to include a control loop to provide an error signal that controls a second portion of the cycle to thereby maintain a selected duty cycle. The processors also include a data clock aligner configured to share the error signal and provide a data clock that is delayed by a selected delay from a selected one of the input and system clocks. In addition to providing effective control that is independent of disturbing effects (e.g., temperature and clock rate), the shared use reduces processor costs.

Abstract: In an embodiment, a circuit device includes a first counter responsive to a clock signal and to a first control word having a first precision. The counter produces a first control signal related to the first control word at a first output. The circuit device further includes a second counter responsive to the clock signal and to a second control word having the first precision. The second counter produces a second control signal related to the second control word at a second output. The circuit device also includes a filtering circuit responsive to the first output and the second output to receive the first and second control words. The filtering circuit is adapted to produce an output control signal related to the first and second control words, where the output control signal has a second precision that is greater than the first precision.

Abstract: A sensing apparatus includes a reference voltage generation circuit for generating a first and a second reference signals having different constant voltage levels, an A/D conversion circuit having a ring-gate-delay circuit, and a correction circuit for correcting an output value of the A/D conversion circuit. The A/D conversion circuit converts a load signal and the first and second reference signals to digital data based on the number of times a pulse signal input to the ring-gate-delay circuit circulates through the ring-gate-delay circuit. The correction circuit corrects the output value based on a ratio of a first difference between the digital data to a second difference between the digital data.

Abstract: A method for converting data includes matching dynamic elements by repeatedly selecting a portion of unit elements among N unit elements according to data and a circulation direction. An existence of a tone generation possibility is determined by comparing a present pointer position with a previous pointer position and by comparing present data with previous data. At least one of the present pointer position and the circulation direction is changed based on the existence of the tone generation possibility. The present pointer position and the present data are stored or the changed pointer position and the present data are stored. Unit elements are sequentially selected by the present data from the stored pointer position in the circulation direction or the changed circulation direction. The present pointer position is moved by the present data in the circulation direction or the changed circulation direction.

Abstract: A semiconductor device includes: input terminals identified by channel numbers and configured to receive analog signals; analog input pads identified by pad numbers and connected with whole or part of the input terminals; a data holding section configured to hold a data of the input terminals; a channel designating section configured to generate a channel designation signal to designate one of the channel numbers; and a channel translating section configured to translate the channel number indicated by the channel designation signal into a specific one of the pad numbers based on the held data. An A/D converting section is configured to convert the analog signal inputted from the analog input pad corresponding to the specific pad number into a digital signal.

Abstract: A method and apparatus for simplifying a structure needed to delay data in delay units when a reference signal and data are transmitted by using chaotic signals are provided. The method includes delaying data by at least two delay times, wherein each of the delay times occurs sequentially; multiplexing the data, which has been delayed, according to a control signal; and transmitting the data and a reference signal which corresponds to the data at an interval of delay time. The apparatus includes a first delay unit which is configured to delay data for a first delay time; a second delay unit which is configured to delay the data output from the first delay unit for a second delay time; and a multiplexer which is configured to multiplex the data from the first and second delay units according to a control signal.

Abstract: A receiver (1300) includes a mixing digital-to-analog converter (DAC) (1306), a direct digital frequency synthesizer (DDFS) (132A) and an interface (134D). The mixing DAC (1306) includes a radio frequency (RF) transconductance section (1308) and a switching section (1310). The RE transconductance section (1308) includes an input for receiving an RF signal and an output for providing an RE current signal. The switching section (1310) is coupled to the RF transconductance section (1308) and includes inputs for receiving bits associated with a digital local oscillator (LO) signal and an output that is configured to provide an analog output signal. The DDFS (132A) includes outputs configured to provide the bits associated with the digital LO signal to the inputs of the switching section (1310). The interface (134D) is coupled to the DDFS (132A) and is configured to align the bits provided by the DDFS (132A) with a first clock signal.

Abstract: Methods and systems are provided for an improved phase detector utilizing analog-to-digital converter (ADC) components. In an embodiment, the method includes from an ADC having a sampling clock signal that determines sampling instants, obtaining a first comparison value between an analog signal and a first threshold voltage at a first sampling instant, and obtaining a second comparison value between the analog signal and a second threshold voltage at a second sampling instant. The method further includes, from a supplemental circuit, obtaining a third comparison value between the analog signal and a third threshold voltage at a third sampling instant between the first and second sampling instants. The method further includes processing the first, second, and third comparison values to determine a phase relationship between the analog signal and the sampling clock.

Abstract: The invention provides a system and method for providing pluggable pattern matching for servlets. This feature allows application servers that incorporate the invention to support non-J2EE pattern matching schemes in their http request resolution. The pluggable pattern matching feature is targeted primarily at customers who want to implement custom URL matching patterns. Since this feature is not J2EE compliant, some other form of configuration is necessary. In one embodiment an XML file (weblogic.xml) is used to configure the new pattern matching utilities. By modifying the settings in the weblogic.xml file, users are able to plug their own custom pattern matching utility classes into the weblogic server.

Abstract: Circuits and methods for determining component ratios are provided. An analog to digital converter circuit may include comparison capacitors arranged in an upper group and a lower group for quantizing analog signals into the digital domain. In addition to determining the lower bits during an analog to digital conversion of an input sample, the lower group of comparison capacitors may also be used during calibration mode to quantize a ratio signal that represents the capacitor mismatches of the upper group rather than using a dedicated digital-to-analog converter to perform this function.

Abstract: A method for configuring a circuit for providing a power OK (POK) signal is described. The method includes identifying a voltage range and voltage interval, dividing the voltage range into a plurality of segments, selecting a reference voltage for each segment, and selecting resistor values for a plurality of voltage dividers for dividing an output voltage from a precision voltage reference into each of the reference voltages. A power OK signal generator and method for generating a power OK signal are also described.

Abstract: A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.

Abstract: A waveform acquisition system that captures and digitizes a wideband electrical signal through a bank of front end filters, frequency down converters, and conventional digitizers (A/D converters). A software algorithm reconstructs the composite input signal and applies the necessary corrections to remove the effects of hardware impairments. This approach is possible because it uses a class of filters that exhibit the quality of perfect waveform reconstruction, allowing signals whose spectral components overlap multiple filter bands, to be faithfully reconstructed. A calibration generator switched into the input port serves as a reference for quantifying and removing hardware errors. The channelized analog-to-digital converter (ADC) effectively multiplies the bandwidth and sampling rate of the conventional digitizer performance in a single channel by the number of channels in the system.

Abstract: A defect detection system and related method take advantage of multilevel detection technique for detecting defects on an integrated circuit. The defect detection system utilizes an analog-to-digital converter for converting an analog sensing signal into an output code having a plurality of bits. The defect detection methods include an open test method and a short test method. The open and short test methods both include a calibrating method and a testing method individually. The calibrating method functions to determine a preset reference voltage for the analog-to-digital converter based on a predetermined code. The testing method makes use of the preset reference voltage and the predetermined code for generating the output code having a plurality of bits. The output code is then utilized to determine whether or not there are open or short defects on the integrated circuit and to classify the defects.

Abstract: A method and apparatus for monitoring and adjusting an analog signal of an operating circuit. The apparatus includes a control circuit, an analog-to-digital converter, and a comparator. The control circuit has an analog generator for generating the analog signal and an adjusting circuit for adjusting the strength of the analog signal. The analog-to-digital converter receives the analog signal and converts the analog signal to a digital signal. The comparator then compares the value of the digital signal to a predetermined value and generates a comparator signal. The adjusting circuit then receives the comparator signal and adjusts the strength of the analog signal based upon the value of the comparator signal. The method includes generating the analog signal, converting the analog signal to a digital signal, comparing the value of the digital signal to a predetermined value and adjusting the strength of the analog signal.

Abstract: A method is provided to reduce delay in signal processing of a digital control system. The method includes receiving outputs from a digital controller at a first frequency. A pre-load data value is then loaded into an accumulator register and output to a digital to analog converter (DAC). In one preferred embodiment, the pre-load data value is the value of the current digital controller output. In another preferred embodiment, the pre-load data value is the value of a previous digital controller output. The method additionally includes computing a step increment value that includes the difference between the most recent value output from the digital controller and the value output by the digital controller just prior to the most recent value. The step increment value is added to the pre-load data value in the accumulator register to create an augmented value, which is then output to the DAC.

Abstract: Methods and apparatus or systems for providing security based on innate characteristics of devices are disclosed. A method of providing security associated with communications from a digital device includes observing an analog signal associated with communications from the digital device, characterizing the digital device at least partially based on the analog signal, and providing a security feature at least partially based on the step of characterizing.

Abstract: An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

Abstract: A method and associated apparatus are described that enables unattended, remotely distributed appliances, such as vending machines, utility meters, thermostats and kitchen appliances (ovens, washing machines, refrigerators, etc.) to be connected inexpensively to each other and to a centrally located server. The apparatus 1) uses relatively simple “personality” modules to adapt the apparatus to the application in combination with a sophisticated core module that provides the intelligence needed to process data locally, to format that data and to transfer it to a remote server and 2) uses existing Internet-based communication links, thereby avoiding the costly proprietary links used with current state-of-the-art solutions.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A wireless device, method, and signal for use in communication of a wireless packet between transmitting device and a wireless receiving device via a plurality of antennas, wherein a signal generator generates wireless packet including a short-preamble sequence used for a first automatic gain control (AGC), a first long-preamble sequence, a signal field used for conveying a length of the wireless packet, an AGC preamble sequence used for a second AGC to be performed after the first AGC, a second long-preamble sequence, and a data field conveying data. The AGC preamble sequence is transmitted in parallel by the plurality of antennas.

Abstract: A radio frequency integrated circuit (RFIC) includes a digital to analog converter, an analog to digital converter, and a low noise amplifier. The digital to analog converter (DAC) is operably coupled to convert outbound symbols into outbound baseband signals, wherein the digital to analog converter is fabricated within a DAC portion of a substrate of the RFIC. The analog to digital converter (ADC) is operably coupled to convert inbound baseband signals into inbound symbols, wherein the analog to digital converter is fabricated within an ADC portion of the substrate. The low noise amplifier is operably coupled to amplify an inbound radio frequency (RF) signals. The low noise amplifier is fabricated within a radio portion of the substrate, wherein the DAC portion of the substrate is physically between the ADC portion and the radio portion of the substrate to provide isolation when the low noise amplifier and the ADC are active and the DAC is inactive.

Abstract: An imaging device with a semi-column-parallel pipeline analog-to-digital converter architecture. The semi-column-parallel pipeline architecture allows multiple column output lines to share an analog-to-digital converter. Analog-to-digital conversions are performed in a pipelined manner to reduce the conversion time, which results in shorter row times and increased frames rate and data throughput. The architecture also enhances the pitch of the analog-to-digital converters, which allows high performance, high resolution analog-to-digital converters to be used. As such, semi-column-parallel pipeline architecture overcomes the shortcomings of the typical serial and column-parallel architectures.

Abstract: A method is provided for correction of signal distortion, wherein the method comprises the steps of reading in a digital input signal value, determining a digital output signal value on the basis of the digital input signal value that has been read in, and outputting the digital output signal value to a signal processing path, wherein the digital output signal value is determined such that a predetermined systematic error of signal processing by the signal processing path with regard to the digital input signal value is compensated for.

Abstract: A tuner architecture is disclosed that mixes an analog RF input signal and a digital local oscillator signal to generate a output signal at a desired IF frequency, including low-IF and zero-IF solutions. The tuner provides a number of advantages over previous implementations, such as improved performance for low-IF and zero-IF architectures and a significant reduction in interference between adjacent paths in a multiple tuner solution. Other features and variations can be implemented, if desired, and related methods can be utilized, as well.

Abstract: Monitoring a converter (1) includes detecting whether a value of an input variable (2) for the converter (1) assumes a first prescribed input reference value (41) and checking whether an output variable (3) from the converter (1) likewise assumes a corresponding, second prescribed output reference value (61). This means that the operation of the converter is tested only at occasional instants, specifically only using individual, prescribed values. The fact that only prescribed values (41, 61) are compared with instantaneous values of the input and output variables (2, 3) means that the invention can be implemented using very simple means. The method is particularly suitable for monitoring the operation of a converter (1) in a control or protective device for an electrical switchgear assembly. In this context, when a malfunction in the converter (1) is detected, all protective functions which are dependent on the converter (1) are preferably turned off.