Integrated Circuit, Printed Circuit, Or Circuit Board Patents (Class 427/96.1)
  • Patent number: 8075807
    Abstract: An electrode paste for a solar cell comprising electrically conductive particles, lead-free glass frit, a resin binder and zinc oxide particles, wherein zinc oxide particles having a specific surface area of 6 m2/g or less are contained at 10% by weight or more based on the total amount of zinc oxide.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: December 13, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventor: Takuya Konno
  • Publication number: 20110290543
    Abstract: The present invention provides a wiring board giving good heat dissipation over a long period of use. The present invention also provides a method for producing board, including coating a surface of a metal substrate, which is made of an aluminium plate, with a composition containing a substance having a polysiloxane structure and inorganic particles having insulating and heat-dissipating properties, curing the composition, then bonding a copper foil to the cured composition, and partially removing the copper foil, thereby forming a wiring layer.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 1, 2011
    Applicant: AIN CO., LTD.
    Inventors: Koji Takeuchi, Masami Matsuda, Kaoru Ono, Makoto Hosoda
  • Patent number: 8062698
    Abstract: A process for printing conductive metal markings directly on a substrate under an ambient condition, including the steps of synthesizing or providing conductive the ink on a substrate to form conductive metallic nanoparticles into an ink; and printing the ink on a substrate to form conductive metallic markings on the substrate. The printed conductive metallic markings may form wires that behave as resonant RFID antenna applications.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: November 22, 2011
    Assignee: Xerox Corporation
    Inventors: Naveen Chopra, Peter M. Kazmaier, Dominique J. Lalisse, Paul F. Smith
  • Patent number: 8048479
    Abstract: A method for placing material onto a target board by means of a transfer board comprising a plurality of blind holes, the method comprising the steps of immersing the transfer board in a material bath, wherein a first pressure acts on the material bath and a second pressure acts in the blind holes, and wherein the first pressure and the second pressure are substantially equal; generating a pressure difference between the first pressure and the second pressure, so that the blind holes of the transfer board are filled at least partially with the liquid material; extracting the transfer board from the material bath; and positioning the transfer board opposite to the target board, the material being expelled from the blind holes, such that the material touches the target board.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: November 1, 2011
    Assignee: Qimonda AG
    Inventors: Harry Hedler, Roland Irsigler, Volker Lehmann, Judith Lehmann, legal representative
  • Patent number: 8048721
    Abstract: A method for filling multi-layer chip-stacked gaps is revealed, primarily comprising the steps as below. Firstly, a chip-stacked assembly is provided, comprising a substrate and a plurality of chips vertically stacked on the substrate where at least a first underfilling gap is formed between each two adjacent ones of the stacked chips with a height difference from the substrate. Then, the chip-stacked assembly is flipped and dipped into an underfilling material where the underfilling material is disposed in a storage tank in a flowing state to completely fill the first underfilling gap. Then, the chip-stacked assembly is taken out. Finally, the chip-stacked assembly is heated to cure the underfilling material filled in the first underfilling gap. Accordingly, multi-layer chip-stacked gaps with different heights can be simultaneously filled at one single step. The conventional underfilling difficulty of multi-layer chip-stacked gaps can be solved leading to higher productivity.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: November 1, 2011
    Assignee: Powertech Technology Inc.
    Inventors: Hung-Hsin Hsu, Wei-Chih Chien
  • Patent number: 8043536
    Abstract: A conductor paste for a ceramic substrate contains a) a conductive metal powder comprising a silver powder and a palladium powder; b) a glass powder; and c) an organic solvent, wherein the conductive metal powder has an average particle diameter of not more than 1.2 ?m, and the glass powder is a Bi2O3—SiO2—B2O3 type glass powder, and the content of the glass powder is in a range of from 1 to 6 wt % based on the weight of the paste.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: October 25, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Akira Inaba, Naoto Nakajima
  • Patent number: 8034401
    Abstract: A plurality of conductive patterns are formed so as to be arranged in a scanning direction of a recording head. A state of each of the conductive patterns and a state between the adjacent conductive patterns are electrically checked to detect a wire break and a short circuit in the conductive patterns.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: October 11, 2011
    Assignee: Canon Kabushiki kaisha
    Inventors: Seiichi Kamiya, Yuji Tsuruoka, Takashi Mori, Nobuhito Yamaguchi, Masao Furukawa
  • Patent number: 8025923
    Abstract: A method of manufacturing a structure, including forming a composite film composed of a coating film and an organic or inorganic film on top of a substrate by forming the coating film on the surface of a template provided on top of the substrate; forming the organic or inorganic film on the surface of the coating film, and removing a portion of the organic or inorganic film and a portion of the coating film; forming a second coating film on the surface of the composite film; forming an organic coating film on the substrate that covers the second coating film; removing a portion of the second coating film; and forming a structure composed of a metal or metal oxide later on the substrate by removing all residues left on the substrate except for the coating film and the second coating film.
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: September 27, 2011
    Assignees: Tokyo Ohka Kogyo Co., Ltd., Riken
    Inventors: Shigenori Fujikawa, Toyoki Kunitake, Hiromi Takaemoto, Mari Koizumi, Hideo Hada, Sanae Furuya
  • Patent number: 8012377
    Abstract: A method of synthesizing doped semiconductor nanocrystals.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: September 6, 2011
    Assignee: The Board of Trustees of the University of Arkansas
    Inventors: Xiaogang Peng, Narayan Pradhan
  • Patent number: 8003018
    Abstract: A composition for fabricating an electrode includes an organic binder and a conductive filler. About 3 to about 60 wt. % of the composition is the organic binder, about 5 to about 95 wt. % of the composition is the conductive filler, the conductive filler includes predominantly aluminum, the conductive filler has a flake shape, and the conductive filler has an average thickness of about 0.05 ?m to about 0.75 ?m.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: August 23, 2011
    Assignee: Cheil Industries, Inc.
    Inventors: Jae Hwi Cho, Kuninori Okamoto, Yong Hyun Kim, Hyun Don Kim
  • Publication number: 20110193672
    Abstract: A magnetic element and a method for manufacturing the same are provided. The magnetic element may be applied to various electronic devices requiring magnetic elements, for example, communication circuits and transformer circuits. The magnetic element mainly includes a substrate and an iron core. The substrate has an accommodation slot formed thereon, and the iron core is assembled in the accommodation slot. Furthermore, the substrate and the iron core are respectively disposed with a vertical circuit, and the substrate further has a horizontal circuit disposed on an upper surface and a lower surface respectively. After the above components are assembled, each vertical circuit and each horizontal circuit are electrically connected, so as to form the magnetic element having an coil architecture.
    Type: Application
    Filed: February 11, 2010
    Publication date: August 11, 2011
    Inventor: Tzung-Hua YANG
  • Patent number: 7972540
    Abstract: A process to fabricate an electronic device comprising: (a) liquid depositing a composition comprising a liquid, silver-containing nanoparticles, a replacement stabilizer comprising a carboxylic acid on the surface of the silver-containing nanoparticles, and a residual amount of an initial stabilizer on the surface of the silver-containing nanoparticles, resulting in a deposited composition; and (b) heating the deposited composition to form an electrically conductive layer comprising silver.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: July 5, 2011
    Assignee: Xerox Corporation
    Inventors: Yuning Li, Beng S Ong
  • Patent number: 7972650
    Abstract: A method for manufacturing an electronic circuit in three-dimensional space provides for interconnecting electronic components within the circuit by directly writing conducting lines. The method may include observing a direct writing tool of a direct write system using a vision system, determining proper placement of the direct writing tool at least partially based on the step of observing, and directly writing conducting lines in three dimensions using the proper placement. The direct writing may be on a surface or in free space. The method may include stacking a plurality of chips to provide a stack having a top surface and edges extending away from the top and interconnecting connections of the chips by directly writing conducting lines along one of the edges.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: July 5, 2011
    Assignee: nScrypt, Inc.
    Inventors: Kenneth H. Church, Patrick Clark, Dongjiang Xu, Lance Swan, Bryan Irwin, Vladimir Pelekhaty
  • Publication number: 20110155812
    Abstract: Disclosed is a conductive composition which can be used to form an aqueous conductive ink with increased conductivity. A film of the dry ink having a thickness of 5 microns or less has a surface roughness of less than 1.5 times the surface roughness of a cellulosic-based substrate which it coats. The aqueous conductive composition contains conductive particles, preferably silver, an anionic wetting agent and a styrene-acrylic copolymer. The composition is highly conductive and requires reduced drying energy. In addition, it may be applied to low cost substrates by high speed printing processes.
    Type: Application
    Filed: September 7, 2007
    Publication date: June 30, 2011
    Applicant: Sun Chemical Corp.
    Inventors: Jason Hayden Rouse, Dave Klein
  • Patent number: 7968008
    Abstract: Particles and particle films are provided. In certain examples, particles produced from a single phase process may be used to provide industrial scale synthesis of particles for use in devices such as printed wiring boards.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: June 28, 2011
    Assignee: Fry's Metals, Inc.
    Inventors: Sachin Parashar, Siuli Sarkar, Oscar Khaselev, Brian G. Lewis, Michael T. Marczi, Bawa Singh, Nitin Desai, Michael Liberatore
  • Publication number: 20110127075
    Abstract: An insulative coat film comprising one or two or more kinds of oxides having a dielectric constant (k) of 2.5 or smaller and expressed by a general formula of ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3, x?1) is used to form an interlayer insulation film. The insulative coat film applied by spin-coating is flat without reflecting underlying unevenness, and the heat-treated film has surface roughness of 1 nm or less in Ra and 20 nm or less in a P-V value. The interlayer insulation film containing the insulative coat film can have a wiring structure and an electrode formed only by etching without need of a CMP process.
    Type: Application
    Filed: August 14, 2008
    Publication date: June 2, 2011
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED, UBE INDUSTRIES, LTD., UBE-NITTO KASEI CO., LTD.
    Inventors: Tadahiro Ohmi, Takaaki Matsuoka, Atsutoshi Inokuchi, Kohei Watanuki, Tadashi Koike, Tatsuhiko Adachi
  • Publication number: 20110123796
    Abstract: An interposer film for IC packaging is disclosed. The interposer film comprises a substrate that supports a plurality of electrically conductive domains. The substrate contains a rigid rod type polyimide and about 5-60 wt % filler. The filler has at least one dimension that (on average) is less than about 800 nanometers, and the filler also has an average aspect ratio greater than about 3:1.
    Type: Application
    Filed: November 20, 2009
    Publication date: May 26, 2011
    Applicant: E.I. DUPONT DE NEMOURS AND COMPANY
    Inventors: BRIAN C. AUMAN, Thomas Edward Carney, Kostantinos Kourtakis, Salah Boussaad
  • Patent number: 7944171
    Abstract: An attachable wireless charging device includes a carrier board, a receiving coil, a circuit board, and at least two conductive wires. The carrier board has a back surface on which an adhesive layer is coated. The receiving coil is formed in the carrier board. The circuit board is mounted to one side of the carrier board and includes a power receiving circuit, which includes a receiving control circuit, a resonance control circuit, a regulation circuit, a control circuit, a polarity selection circuit, and a circuit output section, which are electrically and sequentially connected. Electrical connection is established between the receiving control circuit and the receiving coil. The at least two conductive wires are arranged at one side of the circuit board and are electrically connectable with the circuit output section of the circuit board. As such, an attachable wireless charging device featuring automatic determination of polarity connection is provided.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: May 17, 2011
    Inventor: Ming-Hsiang Yeh
  • Patent number: 7935277
    Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) zinc-containing additive; (c) glass frit wherein said glass frit is lead-free; dispersed in (d) organic medium. The present invention is further directed to an electrode formed from the composition above wherein said composition has been fired to remove the organic vehicle and sinter said glass particles. Still further, the invention is directed to a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition detailed above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.
    Type: Grant
    Filed: July 21, 2008
    Date of Patent: May 3, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Alan Frederick Carroll, Kenneth Warren Hang
  • Publication number: 20110096518
    Abstract: An electronic circuit module and a method of manufacturing the electronic circuit module are disclosed. In one embodiment, the electronic circuit module includes i) a substrate on which a circuit is formed, ii) a plurality of electrical devices electrically connected to the circuit and iii) a first molding unit coated on the substrate to cover at least the electrical devices. The module further includes i) a test terminal unit comprising a plurality of test wires and configured to inspect the circuit, wherein each of the test wires comprises a first end electrically connected to the circuit and a second end exposed from the first molding unit, and wherein the second ends of the test wires form an inspection unit and are adjacent to each other on the substrate and ii) a second molding unit coated on the substrate to cover the second ends of the test wires.
    Type: Application
    Filed: July 30, 2010
    Publication date: April 28, 2011
    Applicant: Samsung SDI Co., Ltd.
    Inventors: Jin-Hong An, Jae-Soon Kim
  • Publication number: 20110091152
    Abstract: A suspension board with circuit includes a circuit board including a metal supporting board, an insulating layer formed on the metal supporting board, and a conductive layer formed on the insulating layer; and an optical waveguide provided in the circuit board. The optical waveguide is provided with a positioning portion for positioning the optical waveguide and a near-field light generation portion for generating a near-field light by a light applied from the optical waveguide.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 21, 2011
    Applicant: Nitto Denko Corporation
    Inventor: Hajime Nishio
  • Publication number: 20110088931
    Abstract: Multilayer coatings comprising at least two layers wherein at least one layer comprises a composition comprising graphene sheets and at least one binder and wherein at least two layers have different compositions.
    Type: Application
    Filed: April 6, 2010
    Publication date: April 21, 2011
    Applicant: VORBECK MATERIALS CORP.
    Inventors: John S. Lettow, Dan Scheffer
  • Patent number: 7908965
    Abstract: A plurality of through holes having an equal size are formed in an underlay substrate. Positions of the plurality of through holes are suitably set according to the shape of a substrate sheet. Specifically, an equal number of through holes are formed in each of end blank corresponding regions that, when the substrate sheet and the underlay substrate are overlapped with each other, overlap with end blank regions of the substrate sheet, of the underlay substrate. In addition, the through holes are formed at equal spacing in portions excluding the end blank corresponding regions in a blank corresponding region, which overlaps with a blank region of the substrate sheet, of the underlay substrate.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: March 22, 2011
    Assignee: Nitto Denko Corporation
    Inventor: Takahiko Yokai
  • Patent number: 7910156
    Abstract: A method of making a circuitized substrate in which conductors are formed in such a manner that selected ones of the conductors include solder while others do not and are thus adapted for receiving a different form of connection (e.g., wire-bond) than the solder covered conductors. In one embodiment, the solder may be applied in molten form by immersing the substrate within a bath of the solder while in another the solder may be deposited using a screening procedure.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: March 22, 2011
    Assignee: Endicott Interconnect Technologies, Inc.
    Inventors: Norman A. Card, Robert J. Harendza, John J. Konrad, Tonya L. Mosher, Susan Pitely, Jose A. Rios
  • Patent number: 7910157
    Abstract: In the present invention, an insulating material is applied onto a substrate in a coating treatment unit to form a coating insulating film. The substrate is heated in the heating processing unit, whereby the coating insulating film is hardened partway. A brush is then pressed against the front surface of the coating insulating film in a planarization unit and moved along the front surface of the coating insulating film, thereby planarizing the coating insulating film. The substrate is then heated to completely harden the coating insulating film. According to the present invention, the coating film can be planarized without using the CMP technology.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: March 22, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Shouichi Terada, Tsuyoshi Mizuno, Takeshi Uehara
  • Patent number: 7910223
    Abstract: A planarization composition is disclosed herein that comprises: a) a structural constituent; and b) a solvent system, wherein the solvent system is compatible with the structural constituent and lowers the lowers at least one of the intermolecular forces or surface forces components of the planarization composition. A film that includes this planarization composition is also disclosed. In addition, another planarization composition is disclosed herein that comprises: a) a cresol-based polymer compound; and b) a solvent system comprising at least one alcohol and at least one ether acetate-based solvent. A film that includes this planarization composition is also disclosed. A layered component is also disclosed herein that comprises: a) a substrate having a surface topography; and b) a planarization composition or a film such as those described herein, wherein the composition is coupled to the substrate.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: March 22, 2011
    Assignee: Honeywell International Inc.
    Inventors: Wei Huang, Joseph Kennedy, Ronald Katsanes
  • Publication number: 20110061917
    Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.
    Type: Application
    Filed: September 11, 2009
    Publication date: March 17, 2011
    Applicant: ST-ERICSSON SA
    Inventors: Nedyalko Slavov, Heinz-Peter Wirtz, Kwei-Kuan Kuo
  • Publication number: 20110064870
    Abstract: Methods of swelling and topographically altering polymers of substrates using low foaming compositions are disclosed. Solvent swells which are stable, homogeneous and low foaming are applied to substrates containing polymers to swell and soften the polymers followed by applying an oxidizer to topographically alter and desmear the polymers in preparation for metallization of the substrate.
    Type: Application
    Filed: August 18, 2010
    Publication date: March 17, 2011
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Crystal P. L. LI, Dennis K. W. YEE, Michael CY TANG
  • Patent number: 7906045
    Abstract: The present invention is directed to a thick film conductive composition comprising: (a) electrically conductive silver powder; (b) Zn-containing additive wherein the particle size of said zinc-containing additive is in the range of 7 nanometers to less than 100 nanometers; (c) glass frit wherein said glass frit has a softening point in the range of 300 to 600° C.; dispersed in (d) organic medium. The present invention is further directed to a semiconductor device and a method of manufacturing a semiconductor device from a structural element composed of a semiconductor having a p-n junction and an insulating film formed on a main surface of the semiconductor comprising the steps of (a) applying onto said insulating film the thick film composition as describe above; and (b) firing said semiconductor, insulating film and thick film composition to form an electrode.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: March 15, 2011
    Assignee: E. I. du Pont de Nemours and Company
    Inventors: Yueli L. Wang, Alan Frederick Carroll, Kenneth Warren Hang, Richard John Sheffield Young
  • Patent number: 7901743
    Abstract: A method and system for treating a dielectric film on a plurality of substrates includes disposing the plurality of substrates in a batch processing system, the dielectric film on the plurality of substrates having a dielectric constant value less than the dielectric constant of SiO2. The plurality of substrates are heated, and a treating compound comprising a CxHy containing compound, wherein x and y represent integers greater than or equal to unity is introduced to the process system. A plasma is formed and at least one surface of the dielectric film on said plurality of substrates is exposed to the plasma.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: March 8, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Eric M. Lee, Dorel I. Toma
  • Patent number: 7901598
    Abstract: A solid electrolyte and a method of manufacturing the same are provided. The solid electrolyte contains x atomic % of lithium, y atomic % of phosphorus, z atomic % of sulfur, and w atomic % of oxygen, in which the x, the y, the z, and the w satisfy the following expressions (1)-(5): 20?x?45 ??(1) 10?y?20 ??(2) 35?z?60 ??(3) 1?w?10 ??(4) x+y+z+w=100 ??(5), and apexes of X-ray diffraction peaks in an X-ray diffraction pattern obtained by an X-ray diffraction method using a K?-ray of Cu exist at diffraction angles 2? of 16.7°±0.25°, 20.4°±0.25°, 23.8°±0.25°, 25.9°, 0.25°, 29.4°±0.25°, 30.4°±0.25°, 31.7°±0.25°, 33.5°±0.25°, 41.5°±0.25°, 43.7°±0.25°, and 51.2°±0.25°, respectively, in the X-ray diffraction pattern, and a half-width of each of the X-ray diffraction peaks is not larger than 0.5°.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: March 8, 2011
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Nobuhiro Ota
  • Publication number: 20110052828
    Abstract: A novel means for placing conductive metal traces on ceramic without adhesives, glues or any organic materials. Metal traces created by thermal spraying metal on to a prepared ceramic surface. The ceramic surface is prepared by creating recesses where the metal is to remain as circuit traces. Following thermal spray, the excess metal is removed from the surface leaving the metal electrically conductive traces in the ceramic recesses. This process improves metal to ceramic bond, reducing failures caused from thermal expansion differences between ceramic and metal traces and eliminates all organic adhesives.
    Type: Application
    Filed: September 3, 2009
    Publication date: March 3, 2011
    Inventors: Randy Allen Normann, Joseph Anthony Henfling
  • Patent number: 7897066
    Abstract: A conductor paste for a ceramic substrate contains a) a conductive metal powder comprising a silver powder and a palladium powder; b) a glass powder; and c) an organic solvent, wherein the conductive metal powder has an average particle diameter of not more than 1.2 ?m, and the glass powder is a Bi2O3—SiO2—B2O3 type glass powder, and the content of the glass powder is in a range of from 1 to 6 wt % based on the weight of the paste.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: March 1, 2011
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Akira Inaba, Naoto Nakajima
  • Publication number: 20110042813
    Abstract: Printed electronic device comprising a substrate onto at least one surface of which has been applied a layer of an electrically conductive ink comprising functionalized graphene sheets and at least one binder. A method of preparing printed electronic devices is further disclosed.
    Type: Application
    Filed: January 9, 2009
    Publication date: February 24, 2011
    Applicants: VORBECK MATERIALS CORPORATION, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: John M. Crain, John S. Lettow, Ilhan A. Aksay, Sibel A. Korkut, Katherine S. Chiang, Chuan-hua Chen, Robert K. Prud'Homme
  • Publication number: 20110030888
    Abstract: A method to manufacture microfluidic sensors, typically including componentizing substrate layers One such method includes providing a plurality of layers of material configured to permit their stacking to form at least a first cap layer, a first channel layer, an interrogation layer, and a second channel layer During assembly, ribbon sections of substrate layers are sandwiched to cooperatively align elements through-the-thickness of the sandwich Individual sensors are then removed from the sandwich ribbon A componentizing step includes forming one or more elements for successive sensors spaced along the axial length of a ribbon Certain elements include electrically conductive patterned structures preferably printed onto a substrate using conductive ink and a printing process, sometimes placing material in operable position to conduct electricity through the thickness of at least one nbbon Other elements may include channels, tunnels, and vias that can be machined, stamped, or cut into a ribbon section.
    Type: Application
    Filed: April 7, 2009
    Publication date: February 10, 2011
    Inventors: Harold E. Ayliffe, Curtis S. King
  • Patent number: 7883614
    Abstract: The method for manufacturing an electronic part includes a step of forming an opening hole onto an insulating member sandwiched between a conductor film and a lower conductor layer, from the conductor film, a step of making a surface of the lower conductor layer adhering the insulating member as bottom of the opening hole, and making a metal plating as a conductor portion grow in the opening hole from the lower conductor layer. In the method, after metal plating has reached the conductor film, the metal plating is grown on the conductor film and the conductor portion as electrode, to thereby form a thickness enough to form an upper conductive layer.
    Type: Grant
    Filed: June 8, 2004
    Date of Patent: February 8, 2011
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Hajime Kuwajima, Hiroki Hara, Hiroshi Yamamoto
  • Publication number: 20110027466
    Abstract: A composition includes a boron-containing hydrogen silsesquioxane polymer having a structure that includes: silicon-oxygen-silicon units, and oxygen-boron-oxygen linkages in which the boron is trivalent, wherein two silicon-oxygen-silicon units are covalently bound by an oxygen-boron-oxygen linkage therebetween.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 3, 2011
    Inventors: Sina Maghsoodi, Shahrokh Motallebi, SangHak Lim, Do-Hyeon Kim
  • Patent number: 7871666
    Abstract: A pattern forming system including a feeding reel for feeding a tape form substrate that is wound up, a winding reel for winding up the tape form substrate that is fed up, and a droplet discharge apparatus for discharging a droplet onto the tape form substrate, between the feeding reel and the winding reel, to form a pattern, wherein the droplet discharge apparatus includes a table that can move while sucking the tape form substrate, with a slack mechanism for the tape form substrate being placed on the both ends of the table in the longitudinal direction of the tape form substrate.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: January 18, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Kazuaki Sakurada, Noboru Uehara, Tsuyoshi Shintate
  • Patent number: 7870665
    Abstract: A conductor circuit and method of manufacturing a conductor circuit. The method includes forming a continuous conductor pattern on an insulating substrate, and connecting a short-circuit wire at a first position on the continuous conductor pattern such that two or more points on the continuous conductor pattern are short-circuited to each other by the short-circuit wire at the first position. An electrolytic plating film is formed on the continuous conductor pattern while the short-circuit wire is connected to the continuous conductor pattern at the first position, and the short-circuit wire is removed from the first position on the continuous conductor pattern to uncover a first exposed portion of the continuous conductor pattern.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: January 18, 2011
    Assignee: Ibiden Co., Ltd.
    Inventors: Toshihiro Nomura, Naotaka Higuchi
  • Publication number: 20110008245
    Abstract: Provided are methods for producing nanostructures and nanostructures obtained thereby. The methods include heating a certain point of a substrate dipped into a precursor solution of the nanostructures so that the nanostructures are grown in a liquid phase environment without evaporation of the precursor solution. The methods show excellent cost-effectiveness because of the lack of a need for precursor evaporation at high temperature. In addition, unlike the vapor-liquid-solid (VLS) process performed in a vapor phase, the method includes growing nanostructures in a liquid phase environment, and thus provides excellent safety and eco-friendly characteristics as well as cost-effectiveness. Further, the method includes locally heating a substrate dipped into a precursor solution merely at a point where the nanostructures are to be grown, so that the nanostructures are grown directly at a desired point of the substrate. Therefore, it is possible to grow and produce nanostructures directly in a device.
    Type: Application
    Filed: April 28, 2010
    Publication date: January 13, 2011
    Applicant: KAIST (Korea Advanced Institute of Science and Technology)
    Inventors: Inkyu PARK, Seung Hwan KO
  • Patent number: 7867563
    Abstract: The present invention is a method of mounting a plurality of components on a substrate.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: January 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Hidekazu Arase, Tohru Nakagawa, Hiroyuki Masuda
  • Publication number: 20100323099
    Abstract: To achieve good adherence of a resist coating, more specifically a photo imageable resist coating, to a copper base while ensuring that the copper base being very thin is not compromised, a non-etching non-resist composition for the treatment of the copper base is provided, said composition comprising at least one adhesion agent selected from the group comprising (i) heterocyclic compounds comprising at least one thiol moiety and (ii) quaternary ammonium polymers having the following general chemical formula: {N+(R3)(R4)—(CH2)a—N(H)—C(Y)—N(H)—(CH2)b—N+(R3)(R4)—R5}n2n X?, with R1, R2, R3, R4, R5, Y and X? being defined as claimed.
    Type: Application
    Filed: February 27, 2009
    Publication date: December 23, 2010
    Applicant: Atotech Deutschland GmbH
    Inventors: Christian Sparing, Dirk Tews, Norbert Luetzow, Martin Thoms
  • Publication number: 20100315476
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process forms interconnect wires on a thermal decomposable adhesive, and after positioning the wires at proper bond pad locations, releases the interconnect wires onto the bond pads.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Patent number: 7851013
    Abstract: A plurality of through holes having an equal size are formed in an underlay substrate. Positions of the plurality of through holes are suitably set according to the shape of a substrate sheet. Specifically, an equal number of through holes are formed in each of end blank corresponding regions that, when the substrate sheet and the underlay substrate are overlapped with each other, overlap with end blank regions of the substrate sheet, of the underlay substrate. In addition, the through holes are formed at equal spacing in portions excluding the end blank corresponding regions in a blank corresponding region, which overlaps with a blank region of the substrate sheet, of the underlay substrate.
    Type: Grant
    Filed: March 6, 2008
    Date of Patent: December 14, 2010
    Assignee: Nitto Denko Corporation
    Inventor: Takahiko Yokai
  • Patent number: 7849593
    Abstract: The invention provides a multi-layer circuit board sequentially having an insulating substrate, a first electrically conductive pattern arbitrarily formed, an insulating material layer and a second electrically conductive pattern formed by providing an electrically conductive material on a graft polymer pattern formed on the insulating material layer, and having an electrically conductive path which electrically connects the first electrically conductive pattern present on the insulating substrate and the second electrically conductive pattern. The graft polymer pattern includes a combination of a region where a graft polymer is present and a region where no graft polymer is present, or a combination of a region where a hydrophilic graft polymer is present and a region where a hydrophobic graft polymer is present.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: December 14, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Koichi Kawamura, Takeyoshi Kano
  • Patent number: 7851271
    Abstract: The present invention relates to a mold releasing film for printed circuit board production, which comprises a resin layer (P) containing (A) a polyphenylene ether-based resin in an amount of 50 wt % or more. According to the present invention, it is possible to provide a mold releasing film suitable for production of printed circuit boards, particularly flexible printed circuit boards, which is excellent in mold-releasing property, exhibits little heat shrinkage, hardly imparts wrinkles to printed circuit board products, itself hardly gets wrinkled, and is excellent in contamination resistance since no bleeding-out is observed, and which is also excellent in an anti-moisture absorbing property, shape-following property, less overflow of adhesive, adhesion between multilayer films and slipping property between films.
    Type: Grant
    Filed: April 15, 2004
    Date of Patent: December 14, 2010
    Assignee: Asahi Kasei Chemicals Corporation
    Inventors: Hiroshi Kamo, Yuuji Kusumi
  • Patent number: 7846502
    Abstract: A method of controlling both alignment and registration (lateral position) of lamellae formed from self-assembly of block copolymers, the method comprising the steps of obtaining a substrate having an energetically neutral surface layer comprising a first topographic “phase pinning” pattern and a second topographic “guiding” pattern; obtaining a self-assembling di-block copolymer; coating the self-assembling di-block copolymer on the energetically neutral surface to obtain a coated substrate; and annealing the coated substrate to obtain micro-domains of the di-block copolymer.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: December 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Ho-Cheol Kim, Charles T Rettner, Sang-Min Park
  • Patent number: 7837319
    Abstract: A method and apparatus a digital ink-jet printer are presented. A radiation-curable ink is continuously applies to successive locations on a substrate along a print line extending across the substrate. Concurrently with the continuous application of the radiation-curable ink along the print line, first curing radiation of a predetermined first intensity is continuously applied to the applied ink on the successive locations on the substrate along said print line, with a certain time delay, constant for all the locations on the substrate, between the applications of ink and the first curing radiation. Second curing radiation of a predetermined second intensity is applied to the locations on the substrate a certain time period, constant for all the locations on the substrate, after the application of the first curing radiation to said locations.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: November 23, 2010
    Assignee: Hewlett-Packard Singapore (Private) Ltd.
    Inventors: Gregory Rodin, Kobi Markovich
  • Patent number: 7833572
    Abstract: A dispensing apparatus includes a frame, a support coupled to the frame to receive electronic substrates, a first dispensing unit to dispense viscous material, a second dispensing unit to dispense viscous material, and a gantry coupled to the frame. The gantry includes a first Z drive mechanism to support the first dispensing unit and lower the first dispensing unit toward a first electronic substrate pattern when performing a dispense operation, and a second Z drive mechanism to support the second dispensing unit and lower the second dispensing unit toward a second electronic substrate pattern when performing a dispense operation. The second Z drive mechanism may be adjusted relative to the first Z drive mechanism a predetermined distance. A controller controls a dispense operation of the first dispensing unit on the first electronic substrate pattern and a dispense operation of the second dispensing unit on the second electronic substrate pattern.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: November 16, 2010
    Assignee: Illinois Tool Works, Inc.
    Inventor: Hugh R. Read
  • Patent number: 7833567
    Abstract: The apparatus forms an electric circuit on a construction member of a machine based on a set of three-dimensional data. The data defines a position and a profile of the construction member, a position of the electric circuit, and a shape of the electric circuit. The electric circuit is used for electrical connection between electric instruments mounted on the machine. The data is associated with a reference coordinate system provided in the machine, and the data includes coordinates of points for determining arrangement of the electric circuit, a distance between any two of the points adjacent to each other, and a cross-sectional area of the electric circuit associated extended between the two points.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: November 16, 2010
    Assignee: Yazaki Corporation
    Inventors: Hitoshi Ohashi, Kinya Horibe, Hitoshi Ushijima, Tatsuya Kato