Integrated Circuit, Printed Circuit, Or Circuit Board Patents (Class 427/96.1)
  • Patent number: 7632427
    Abstract: A conductive paste used for forming internal electrodes of a multilayer ceramic electronic device, used in combination with ceramic green sheets, each containing a butyral resin and having a thickness of 5 ?m or less, and including a conductive powder and an organic vehicle, a solvent in said organic vehicle having terpineol acetate as its main ingredient, whereby there is little change in viscosity along with time and no occurrence of sheet attack.
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: December 15, 2009
    Assignee: TDK Corporation
    Inventors: Kazuhiko Oda, Tetsuji Maruno, Shuichi Miura, Makoto Takahashi, Tatsuya Kojima
  • Patent number: 7629019
    Abstract: A method for forming a wiring pattern in which a plurality of electrical wirings deposited onto a substrate is conductively connected with each other through a plurality of conductive posts, the method including relatively moving a discharge head having a plurality of nozzles and a substrate in a predetermined direction while discharging droplets from predetermined nozzles among the plural nozzles to form the plural conductive posts, wherein, in the orthogonal direction of the above-referenced predetermined direction, the interval among the plural nozzles “a” and the interval among the plural conductive posts “b” satisfy an equation “b=m×a” (“m” may be any positive integer).
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: December 8, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Kazuaki Sakurada, Noboru Uehara, Tsuyoshi Shintate
  • Patent number: 7624500
    Abstract: The disclosure relates to circuits and methods for the manufacture of circuits, such as those which avoid the formation of undesirable short circuit paths. One such method maintains a layout area of a fluid composition receiving layer within a layout area of a dielectric layer. Another such method relates to the application of fluid composition receiving layers, conductive layers, and dielectric layers, such as in the provision of printed circuits.
    Type: Grant
    Filed: August 15, 2007
    Date of Patent: December 1, 2009
    Assignee: Lexmark International, Inc.
    Inventors: Xiaorong Cai, Michael John Dixon, Yimin Guan, Elios Klemo, Bryan Dale McKinley, Paul Sacoto, Jeanne Marie Saldanha Singh, George Nelson Woolcott, Frank Edward Anderson
  • Publication number: 20090289228
    Abstract: The present invention provides an RF powder having a characteristic to be used as a powder (powdery substance) which is composed of a large quantity of particles and has a collective form, wherein each of a large quantity of particles composing the powder is smaller in size as compared with a current IC tag chip and is used as a device having a function substantially equivalent to the IC tag chip, use form thereof is not individual device use but powder use, treatment is easy, a manufacturing cost is very low in respect of a unit cost of each particle, and a practical use is very high, and a method for manufacturing the same. An RF powder 11 is used in a powder form, wherein each particle 11a in the powder has an integrated circuit 13 formed on a substrate 12, an insulating layer 14 formed on the integrated circuit, and an antenna element 15 formed on the insulating layer.
    Type: Application
    Filed: May 22, 2008
    Publication date: November 26, 2009
    Inventor: Yuji Furumura
  • Patent number: 7611747
    Abstract: This invention provides a material for a multi-layer circuit board, excellent in insulating property and burying properties and free from occurrence of cracks, a production method, and a multi-layer circuit board using the insulating material. The invention provides an insulating material having a curable composition layer wherein the curable composition layer contains 0 to 50 pieces/cm2 of foreign matter having particle sizes falling within a range of 30 to 50 ?m, a production method, and a production method for a multi-layer circuit board using the insulating material.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: November 3, 2009
    Assignee: Zeon Corporation
    Inventors: Kazuyuki Onishi, Toshiyasu Matsui, Hiroshi Kurakata, Masahiko Sugimura
  • Patent number: 7608342
    Abstract: Photocurable, conductive, and transparent polymer coating compositions and methods of using the same are provided. The compositions include a photopolymer and an electrically conductive polymer dissolved or dispersed in a solvent system. Preferred photopolymers include water-miscible, multifunctional acrylates. Preferred electrically conductive polymers include poly(3,4-ethylenedioxythiophene)/poly(styrene sulfonate) (PEDOT-PSS). The compositions preferably also contain a photoinitiator and may contain a water-immiscible acrylate and/or a surfactant. The compositions are applied to substrates and exposed to actinic radiation such as ultraviolet (UV) light to form a cured, durable, conductive, and transparent coating.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 27, 2009
    Assignee: Brewer Science Inc.
    Inventor: Xing-Fu Zhong
  • Patent number: 7608326
    Abstract: Electromagnetic-energy absorbing materials are combined with thermally conductive materials, such as those used for thermal management in association with electronic equipment, thereby suppressing the transmission of electromagnetic interference (EMI) therethrough. Disclosed are materials and processes for combining EMI-absorbing materials with thermally conductive materials thereby improving EMI shielding effectiveness in an economically efficient manner. In one embodiment, a thermally conductive EMI absorber is prepared by combining an EMI-absorbing material (for example, ferrite particles) with a thermally conducting material (for example, ceramic particles), each suspended within an elastomeric matrix (for example, silicone).
    Type: Grant
    Filed: October 21, 2003
    Date of Patent: October 27, 2009
    Assignee: Laird Technologies, Inc.
    Inventor: Richard Norman Johnson
  • Patent number: 7608304
    Abstract: A substrate carrying method for removing the electrical charges on a substrate and then carrying the substrate includes forming a conductive layer with conductivity on a part of the surface of the substrate, and carrying the substrate while supporting a conductive layer-forming region of the substrate by a grounded substrate supporting unit with conductivity.
    Type: Grant
    Filed: February 14, 2006
    Date of Patent: October 27, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Minoru Koyama
  • Publication number: 20090256650
    Abstract: A filter with coupled resonator having a substrate; an acoustic mirror intended to support acoustic resonators, and to isolate these resonators from the substrate; a first structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; a second structure with an upper resonator and a lower resonator coupled to one another through at least one layer of acoustic coupling; the lower resonators of the first and second structure having the same electrodes. The first and second structures are connected via a fifth resonator for which electrodes and the piezoelectric layer of the lower resonators are of the first and second structure.
    Type: Application
    Filed: February 13, 2009
    Publication date: October 15, 2009
    Applicants: STMICROELECTRONICS S.A., Centre National de la Recherche Scientifique (C.N.R.S.)
    Inventors: Andrea Cathelin, Didier Belot, Alexandre Augusto Shirakawa, Eric Kerherve, Jean-Marie Pham, Pierre Jary
  • Patent number: 7601386
    Abstract: A liquid material is placed on a substrate as a droplet to form a film on the substrate. At least either one of a concentration of solids in the liquid material and a drying rate of the droplets is used as a parameter to control a form of a dried film of the droplets. Moreover, a first droplet is placed on a substrate, the first droplet is dried to form a dried film of a form in which a thickness of an edge is larger than that of a central part, and a second droplet is placed in a region surrounded by the edge section of a dried film of the first droplet to form a dried film of the second droplet. Furthermore, the liquid material is placed on the substrate as a droplet to form a film on the substrate, and a dried film of the droplet is formed by contracting the droplet.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: October 13, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Takashi Masuda
  • Patent number: 7597929
    Abstract: A method of manufacturing a wiring substrate of the present invention includes the steps of, preparing a laminated body having such a structure that a peelable metal foil in which a lower metal foil and an upper metal foil are laminated peelably and an opening portion is provided on a peripheral side is pasted onto a supporting body, forming a through hole having a diameter smaller than the opening portion by processing a portion of the supporting body on an inner side of the opening portion to obtain a reference hole having a projection portion in an inside, forming a resin layer on the peelable metal foil and the projection portion in the reference hole to cover a side surface of the opening portion, and then forming a build-up wiring on the resin layer, removing portions of the build-up wiring and the laminated body corresponding to an area containing the opening portion to expose a peeling boundary of the peelable metal foil, peeling the upper metal foil from the lower metal foil at a boundary to separate
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: October 6, 2009
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masahiro Kyozuka
  • Patent number: 7597928
    Abstract: The invention pertains to a material composition for packaging. The composition comprises (a) an epoxy resin and (b) a curing agent, wherein the mixing ratio of said epoxy resin to said curing agent is in the range of from 0.7 to 1.1. The invention also pertains to a method of using said material composition for packaging a light-sensitive component on a substrate.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: October 6, 2009
    Assignee: Eternal Chemical Co., Ltd.
    Inventors: Tsai-Fa Hsu, Fu-Lung Jeng
  • Patent number: 7594320
    Abstract: A solder resist comprising a thermosetting resin is printed on a surface of an insulating board (7) having a conductor circuit (6). The solder resist is then heat-cured to form an insulating film (1) having a low thermal expansion coefficient. A laser beam (2) is then applied to the portion of the insulating film in which an opening is to be formed, to burn off the same portion for forming an opening (10), whereby the conductor circuit (6) is exposed. This opening may be formed as a hole for conduction by forming a metal plating film on an inner surface thereof. It is preferable that an external connecting pad be formed so as to cover the opening. The film of coating of a metal is formed by using an electric plating lead, which is preferably cut off by a laser beam after the electric plating has finished.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: September 29, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Masaru Takada, Hiroyuki Kobayashi, Kenji Chihara, Hisashi Minoura, Kiyotaka Tsukada, Mitsuhiro Kondo
  • Patent number: 7585541
    Abstract: A printed circuit board is by formed by laminating an interlaminar insulating layer on a conductor circuit of a substrate, in which the conductor circuit is comprised of an electroless plated film and an electrolytic plated film and a roughened layer is formed on at least a part of the surface of the conductor circuit.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: September 8, 2009
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yoshinori Wakihara, Kazuhito Yamada
  • Patent number: 7585540
    Abstract: A method for manufacturing a wiring substrate includes the steps of: (a) patterning a surface-active agent on a substrate having first and second areas to be remained on the first area; (b) removing residues of the surface-active agent in the second area by wet-etching with an alkali; (c) patterning a catalyst to be remained on one of the second area of the substrate and the surface-active agent; and (d) depositing a metal layer on the catalyst to thereby form a wiring.
    Type: Grant
    Filed: March 28, 2005
    Date of Patent: September 8, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hidemichi Furiata, Satoshi Kimura, Minoru Marumo
  • Publication number: 20090218116
    Abstract: A chip on film (COF) structure includes a flexible circuit board and a chip. The flexible circuit board includes a flexible base film and a conductive layer. The flexible base film has a polyimide layer and an anisotropic conductive layer (ACL). The conductive layer is disposed on the flexible base film. The conductive layer and the ACL are separated by the polyimide layer. The chip is mounted with the conductive layer via interconnectors.
    Type: Application
    Filed: July 2, 2008
    Publication date: September 3, 2009
    Inventor: Chia-Hui Wu
  • Publication number: 20090186212
    Abstract: A non-volatile memory including a substrate, source/drain regions, a first insulating layer, a charge storage layer, a second insulating layer, and a conductive layer is provided. The source/drain regions are respectively disposed in the substrate apart from each other. The first insulating layer is disposed on the substrate between the source/drain regions. The charge storage layer is disposed on the first insulating layer. The second insulating layer is disposed on the charge storage layer, and a thickness of a peripheral region of the second insulating layer is greater than a thickness of an internal region of the second insulating layer. The conductive layer is disposed on the second insulating layer.
    Type: Application
    Filed: January 17, 2008
    Publication date: July 23, 2009
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Ming-Chang Kuo
  • Patent number: 7560050
    Abstract: It is an object of the present invention to provide a method for manufacturing a multi-layered unit for a multi-layered ceramic electronic component which can reliably prevent short circuit failure from occurring in a multi-layered ceramic electronic component and form an electrode layer in a desired manner.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: July 14, 2009
    Assignee: TDK Corporation
    Inventors: Shigeki Satou, Takeshi Nomura
  • Patent number: 7560141
    Abstract: A method of controlling both alignment and registration (lateral position) of lamellae formed from self-assembly of block copolymers, the method comprising the steps of obtaining a substrate having an energetically neutral surface layer comprising a first topographic “phase pinning” pattern and a second topographic “guiding” pattern; obtaining a self-assembling di-block copolymer; coating the self-assembling di-block copolymer on the energetically neutral surface to obtain a coated substrate; and annealing the coated substrate to obtain micro-domains of the di-block copolymer.
    Type: Grant
    Filed: November 11, 2008
    Date of Patent: July 14, 2009
    Assignee: International Business Machines Corporation
    Inventors: Ho-Cheol Kim, Charles T. Rettner, Sang-Min Park
  • Patent number: 7555836
    Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: July 7, 2009
    Assignee: FormFactor, Inc.
    Inventors: Gaetan L. Mathieu, Benjamin N. Eldridge, Gary W. Grube
  • Patent number: 7547370
    Abstract: A method for manufacturing a multilayer ceramic electronic element includes the steps of forming ceramic green sheets having superior surface smoothness and small variations in thickness at a high speed, in which defects such as pinholes are prevented from occurring, and providing internal electrodes and step-smoothing ceramic paste on the ceramic green sheets with high accuracy. The method includes the steps of applying ceramic slurry to a base film by a die coater followed by drying performed in a drying furnace for forming the ceramic green sheets, and performing gravure printing of conductive paste and ceramic paste onto the ceramic green sheets by using a first and a second gravure printing apparatus, respectively. Accordingly, the internal electrodes are formed, and the step-smoothing ceramic paste is provided in regions other than those in which the internal electrodes are formed.
    Type: Grant
    Filed: December 15, 2006
    Date of Patent: June 16, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shingo Okuyama, Hiroyoshi Takashima, Akira Hashimoto, Shinichi Kokawa
  • Publication number: 20090142477
    Abstract: A portable electronic device and a transferring method of a circuit element thereof are provided. The portable electronic device comprises a main body and a circuit element. The main body has a shell and a control element by a print way. The circuit element is integrated with the shell by transferring and is electrically connected with the control element.
    Type: Application
    Filed: September 16, 2008
    Publication date: June 4, 2009
    Applicant: ASUSTek COMPUTER INC.
    Inventors: Hung-Hsiang Chen, Yang-Po Chiu
  • Patent number: 7537713
    Abstract: It is an object of the present invention to provide a method for manufacturing a multi-layered unit for a multi-layered ceramic electronic component which can reliably prevent short circuit failure from occurring in a multi-layered ceramic electronic component and form an electrode layer in a desired manner.
    Type: Grant
    Filed: February 23, 2005
    Date of Patent: May 26, 2009
    Assignee: TDK Corporation
    Inventors: Shigeki Satou, Takeshi Nomura
  • Patent number: 7537668
    Abstract: A method of fabricating a high density printed circuit board by applying a strippable adhesive layer on a reinforced substrate (rigid substrate or carrier film) used as a base substrate, forming a metal foil on the adhesive layer by means of plating, lamination or sputtering, and forming a high density circuit on the metal foil serving as a seed layer by means of pattern plating. Specifically, the method of the current invention includes the steps of attaching adhesive means to one surface of a reinforced substrate (rigid substrate or carrier film), forming a seed layer on the adhesive means and forming a circuit pattern on the seed layer, laminating an insulating layer on the circuit pattern and removing the reinforced substrate (rigid substrate or carrier film), and removing the seed layer.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: May 26, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Ryoichi Watanabe
  • Publication number: 20090130298
    Abstract: High aspect ratio structures can be obtained by print-patterning masking features in feature stacks such that each feature has a lateral edge which is aligned in a plane roughly perpendicular to the plane of the substrate on which the features are formed. Due to the differential lateral spreading between features formed on a substrate and formed atop other features, the print head is indexed less than the radius of a droplet to a position where a droplet ejected by the print head forms an upper feature atop a lower feature such that the lateral edges of the upper and lower features are aligned in the plane roughly perpendicular to the plane of the substrate. Feature stacks of two or more features may provide a vertical (or re-entrant) sidewall mask for formation of high aspect ratio structures, by e.g., electroplating, etc.
    Type: Application
    Filed: November 20, 2007
    Publication date: May 21, 2009
    Applicant: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventors: Eric Shrader, Uma Srinivasan, Clark Crawford, Scott Limb
  • Publication number: 20090117325
    Abstract: Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of a magnetic material on a substrate, forming an oxide layer on the first layer of the magnetic material, forming at least one conductive structure on the first magnetic layer, forming a dielectric layer on the at least one conductive structure, forming a second layer of the magnetic material on the at least one conductive structure, and forming a magnetic via coupled to the first and second layers of the magnetic material, wherein the magnetic via comprises a shape to increase inductance of the inductive structure.
    Type: Application
    Filed: November 7, 2007
    Publication date: May 7, 2009
    Inventors: Donald Gardner, Gerhard Schrom, Peter Hazucha, Fabrice Paillet, Tanay Karnik
  • Patent number: 7523548
    Abstract: A process for producing a printed wiring board comprises the steps of depositing a base metal on at least one surface of an insulating film to form a base metal layer and further depositing copper or a copper alloy to form a conductive metal layer, then removing a surface metal layer, which is formed through the above step, by etching to form a wiring pattern, and then treating the base metal layer with a treating liquid capable of dissolving and/or passivating the metal that forms the base metal layer. The printed wiring board so provided comprises an insulating film and a wiring pattern formed on at least one surface of the insulating film, the wiring pattern including a base metal layer deposited on the insulating film surface and a conductive metal layer, the base metal layer for forming the wiring pattern protrudes in a widthwise direction more than the conductive metal layer for forming the wiring pattern.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: April 28, 2009
    Assignee: Mitsui Mining & Smelting Co., Ltd.
    Inventors: Tatsuo Kataoka, Yoshikazu Akashi, Yutaka Iguchi
  • Patent number: 7517553
    Abstract: The present invention provides an adhesive aid composition having excellent adhesive strength to polyimide films without decreasing mechanical properties and being useful in the field of electric materials. An adhesive aid composition of the present invention contains a phenolic hydroxyl group-containing polyamide and a solvent as essential components. The phenolic hydroxyl group-containing polyamide preferably has a segment represented by formula (1): (wherein R1 represents a divalent aromatic group, and n represents an average number of substituents and is a positive number of 1 to 4). The adhesive aid composition of the present invention is suitably used for bonding polyimide films.
    Type: Grant
    Filed: May 11, 2004
    Date of Patent: April 14, 2009
    Assignee: Nippon Kayaku Kabushiki Kaisha
    Inventors: Makoto Uchida, Toyofumi Asano
  • Patent number: 7514116
    Abstract: Horizontal carbon nanotubes may be used for on-die routing and other applications. In one example, a catalyst is applied to a plurality of different points on a substrate. Carbon nanotubes are then grown vertically on the plurality of different points to form a plurality of vertical carbon nanotube structures on the substrate. The vertical carbon nanotuhe structures are then rolled to form horizontal carbon nanotube structures.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventors: Devendra Natekar, Yoshihiro Tomita, Chi-Won Hwang
  • Patent number: 7507434
    Abstract: An approach is provided for laminating layers for a flexible printed circuit board. The approach includes a method and apparatus for providing a base substrate and the surface of the base substrate is treated by radiating ion beams using a gas mixture including oxygen and argon to improve adhesive strength and heat resistance. A tie layer can be formed on the based film to prevent a metal conductive layer from diffusion and to increase the adhesive strength.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 24, 2009
    Assignee: Toray Saehan Inc.
    Inventors: Jeong Cho, Young Kwan Lee, Young Seop Kim
  • Patent number: 7503993
    Abstract: A method for manufacturing a multilayer ceramic electronic element includes the steps of forming ceramic green sheets having superior surface smoothness and small variations in thickness at a high speed, in which defects such as pinholes are prevented from occurring, and providing internal electrodes and step-smoothing ceramic paste on the ceramic green sheets with high accuracy. The method includes the steps of applying ceramic slurry to a base film by a die coater followed by drying performed in a drying furnace for forming the ceramic green sheets, and performing gravure printing of conductive paste and ceramic paste onto the ceramic green sheets by using a first and a second gravure printing apparatus, respectively. Accordingly, the internal electrodes are formed, and the step-smoothing ceramic paste is provided in regions other than those in which the internal electrodes are formed.
    Type: Grant
    Filed: August 25, 2004
    Date of Patent: March 17, 2009
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shingo Okuyama, Hiroyoshi Takashima, Akira Hashimoto, Shinichi Kokawa
  • Publication number: 20090056102
    Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventors: Manabu SAKAMOTO, Tetsuya SHIRASU, Naoki IDANI
  • Patent number: 7491286
    Abstract: The present invention provides a method of forming a patterned thin film on a surface of a substrate having thereon a patterned underlayer of a self-assembled monolayer. The method comprises depositing a thin film material on the self-assembled monolayer to produce a patterned thin film on the surface of the substrate. The present invention further provides processes for preparing the self-assembled monolayer. The present invention still further provides solution-based deposition processes, such as spin-coating and immersion-coating, to deposit a thin film material on the self-assembled monolayer to produce a patterned thin film on the surface of the substrate.
    Type: Grant
    Filed: January 21, 2004
    Date of Patent: February 17, 2009
    Assignee: International Business Machines Corporation
    Inventors: Cherie R Kagan, Tricia Breen Carmichael, Laura Louise Kosbar
  • Patent number: 7487587
    Abstract: Methods of producing a composite substrate and devices made by the methods are disclosed. One of the methods comprises providing a flexible sacrificial layer, producing one or more patterned conducting layers on the flexible sacrificial layer, bending the sacrificial layer into a predetermined shape, providing a stretchable and/or flexible material on top of and in between features of the one or more patterned layers.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: February 10, 2009
    Assignees: Interuniversitair Microelektronica Centrum vzw (IMEC), Universiteit Gent
    Inventors: Jan Vanfleteren, Dominique Brosteaux, Fabrice Axisa
  • Publication number: 20090035453
    Abstract: A pattern forming system including a feeding reel for feeding a tape form substrate that is wound up, a winding reel for winding up the tape form substrate that is fed up, and a droplet discharge apparatus for discharging a droplet onto the tape form substrate, between the feeding reel and the winding reel, to form a pattern, wherein the droplet discharge apparatus includes a table that can move while sucking the tape form substrate, with a slack mechanism for the tape form substrate being placed on the both ends of the table in the longitudinal direction of the tape form substrate.
    Type: Application
    Filed: September 23, 2008
    Publication date: February 5, 2009
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kazuaki Sakurada, Noboru Uehara, Tsuyoshi Shintate
  • Publication number: 20090032293
    Abstract: A conductive bonding material having an improved preservation stability, and hardens when desired, preferably immediately hardens at a low temperature is provided. In one invention, the conductive bonding material comprises a conductive particle ingredient, an epoxy resin ingredient, and a hardening agent ingredient for said epoxy resin and the hardening agent ingredient for said epoxy resin further comprise a reforming agent having a thiol group. In another invention, a conductive bonding material comprising an epoxy resin hardening ingredient, wherein said epoxy resin hardening ingredient contains a sulfur-containing compound having an end group which can coordinate with a surface of the metallic particles, and the sulfur-containing compound comes to perform as a hardening agent for the epoxy resin by dissociating from the surface of the metallic particles. The conductive bonding material may contain fragrance.
    Type: Application
    Filed: March 22, 2006
    Publication date: February 5, 2009
    Inventors: Hidenori Miyakawa, Shigeaki Sakatani, Kumiko Sugiyama, Takayuki Higuchi, Atsushi Yamaguchi
  • Publication number: 20090029036
    Abstract: Methods and compositions for depositing a cobalt containing film on one or more substrates are disclosed herein. A cobalt precursor, which comprises at least one pentadienyl ligand coupled to the cobalt for thermal stability, is introduced into a reaction chamber containing one or more substrates, and the cobalt precursor is deposited to form a cobalt containing film onto the substrate.
    Type: Application
    Filed: May 21, 2008
    Publication date: January 29, 2009
    Inventor: Christian DUSSARRAT
  • Patent number: 7476412
    Abstract: The invention relates to a process for the metallization of an insulator and/or a dielectric, wherein the insulator is firstly activated, it is subsequently coated with another insulator and the latter is patterned, then the first is seeded and lastly metallized.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: January 13, 2009
    Assignee: Infineon Technologies AG
    Inventors: Klaus Lowack, Günter Schmid, Recai Sezi
  • Patent number: 7476422
    Abstract: The invention concerns a copper-based circuit having an electrically insulative substrate, a bond layer including silver formed over select portions of the substrate according to a desired shape of the circuit, and an electrically conductive layer including plastically deformed particles of copper deposited on the bond layer.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: January 13, 2009
    Assignee: Delphi Technologies, Inc.
    Inventors: Alaa A. Elmoursi, Frans P. Lautzenhiser, Albert B. Campbell, John R. Smith
  • Publication number: 20090000957
    Abstract: An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.
    Type: Application
    Filed: June 29, 2007
    Publication date: January 1, 2009
    Inventors: Valery M. Dubin, Nikolay Suetin
  • Patent number: 7469941
    Abstract: A wiring board comprises a substrate; a resin layer which is selectively formed on one main surface of the substrate and has fine metal particles contained or adhered to its surface; and a conductive metal layer which is formed on the resin layer with the fine metal particles interposed between them.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: December 30, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideo Aoki, Chiaki Takubo, Naoko Yamaguchi
  • Patent number: 7470380
    Abstract: A conductive composition consisting essentially of (a) 50-95 wt % finely divided particles of an electrically-conductive material dispersed in (b) a liquid vehicle, for use in the manufacture of an electrically-conductive pattern on a substrate for the use of reducing cross-sectional area and width while retaining conductivity and resistivity.
    Type: Grant
    Filed: March 23, 2004
    Date of Patent: December 30, 2008
    Assignee: E.I. Du Pont De Nemours and Company
    Inventor: Sarah Jane Mears
  • Publication number: 20080315901
    Abstract: The present invention provides a multilayer wiring board in which resistive elements each of whose error from a desired value is smaller than in a conventional case are built, a method for manufacturing the same, and a probe apparatus utilizing the multilayer wiring board. The present invention is based on a basic concept of forming a flat surface on a surface of a multilayer wiring layer on which a resistive element material is to be deposited and depositing the resistive element material on the flat surface.
    Type: Application
    Filed: April 8, 2008
    Publication date: December 25, 2008
    Applicant: Kabushiki Kaisha Nihon Micronics
    Inventors: Tatsuo INOUE, Osamu ARAI, Katsushi MIKUNI, Norihiro IMAI
  • Publication number: 20080299300
    Abstract: The present invention is a method for providing an integrated circuit assembly, the integrated circuit assembly including an integrated circuit and a substrate. The method includes mounting the integrated circuit to the substrate. The method further includes adding thermally conductive particles to a low processing temperature, at least near-hermetic, glass-based coating. The method further includes, during assembly of the integrated circuit assembly, applying a low processing temperature, at least near-hermetic, glass-based coating directly to at least one of the integrated circuit and the substrate. The method further includes curing the coating.
    Type: Application
    Filed: April 5, 2007
    Publication date: December 4, 2008
    Inventors: Ross K. Wilcoxon, Nathan P. Lower, Alan P. Boone
  • Patent number: 7458150
    Abstract: A method of producing a circuit board includes a step of providing a conductive paste including metal nano-particles at an insulating substrate, and a step of sintering the conductive paste so as to form a circuit conductor. In the sintering step, the conductive paste is sintered in a low-oxygen condition including alcohol such that the metal nano-particles are sintered.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: December 2, 2008
    Assignee: Denso Corporation
    Inventors: Masashi Totokawa, Yasunori Ninomiya
  • Publication number: 20080286587
    Abstract: An apparatus includes a first crystalline material layer, a second crystalline material layer positioned adjacent to the first crystalline material layer to form an electron gas, a first interface, and a first ferroelectric layer having ferroelectric domains that apply an electric field to portions of the first interface. A method of making the apparatus is also provided.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 20, 2008
    Applicant: Seagate Technology LLC
    Inventors: Joachim Walter Ahner, Florin Zavaliche
  • Publication number: 20080283973
    Abstract: An integrated circuit including a dielectric layer and a method for producing an integrated circuit. In one embodiment, a dielectric layer is deposited in a process atmosphere. The process atmosphere includes a first starting component at a first point in time, a second starting component at a second point in time and a third starting component at a third point in time. The third starting component includes a halogen.
    Type: Application
    Filed: April 17, 2008
    Publication date: November 20, 2008
    Applicant: QIMONDA AG
    Inventors: Lars Oberbeck, Jonas Sundqvist, Lothar Frey, Alejandro Avellan, Stefan Kudelka
  • Patent number: 7451540
    Abstract: Fabricating (100, 1300) a printed circuit board includes fabricating patterned conductive traces (305, 310, 1410, 1415) onto a foil, laminating the patterned conductive traces to a printed circuit board substrate (405, 1505) by pressing on the foil, such that the conductive traces are pressed into a dielectric layer of the printed circuit board, and removing the foil to expose a co-planar surface of conductive trace surfaces and dielectric surfaces. Removal may be done by peeling (125) and/or etching (130, 1315).
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: November 18, 2008
    Assignee: Motorola, Inc.
    Inventors: Jaroslaw A. Magera, Gregory J. Dunn, Jovica Savic
  • Publication number: 20080280054
    Abstract: A coating film forming apparatus that holds a substrate upon a spin chuck and forms a coating film by supplying a chemical liquid upon a top surface of said substrate comprises: an outer cup provided detachably to surround the spin chuck; an inner cup provided detachably to surround a region underneath the substrate held upon the chuck; a cleaning nozzle configured to supply a cleaning liquid for cleaning a peripheral edge part of the substrate, such that the cleaning liquid is supplied to a peripheral part of a bottom surface of the substrate; a cutout part for nozzle mounting, the cutout part being provided to the inner cup to engage with the cleaning nozzle; and a cleaning liquid supply tube connected to the cleaning nozzle, the cleaning nozzle being detachable to the cutout part in a state in which the cleaning liquid supply tube is connected.
    Type: Application
    Filed: April 21, 2008
    Publication date: November 13, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Nobuhiro OGATA, Hiroichi Inada, Taro Yamamoto, Akihiro Fujimoto
  • Publication number: 20080268138
    Abstract: Disclosed are metal plating compositions and methods. The metal plating compositions provide good leveling performance and throwing power.
    Type: Application
    Filed: April 2, 2008
    Publication date: October 30, 2008
    Applicant: Rohm and Haas Electronic Materials LLC
    Inventors: Erik Reddington, Gonzalo Urrutia Desmaison, Zukhra I. Niazimbetova, Donald E. Cleary, Mark Lefebvre