Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Publication number: 20120220066
    Abstract: The present invention relates to coated binary and ternary nanoparticle chalcogenide compositions that can be used as copper zinc tin chalcogenide precursor inks. In addition, this invention provides processes for manufacturing copper zinc tin chalcogenide thin films and photovoltaic cells incorporating such thin films.
    Type: Application
    Filed: May 21, 2010
    Publication date: August 30, 2012
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventor: Yanyan Cao
  • Patent number: 8252704
    Abstract: This disclosure relates to compositions that include (a) at least one substituted or unsubstituted cyclic alkene, and (b) an antioxidant composition including at least one compound of Formula (I): R1 through R4 in Formula (I) are described in the specification.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 28, 2012
    Assignee: Fujifilm Electronic Materials U.S.A., Inc.
    Inventors: Daniel J. Teff, John L. Chagolla
  • Publication number: 20120208375
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Publication number: 20120208373
    Abstract: A method for depositing an amorphous carbon layer on a substrate includes the steps of positioning a substrate in a chamber, introducing a hydrocarbon source into the processing chamber, introducing a heavy noble gas into the processing chamber, and generating a plasma in the processing chamber. The heavy noble gas is selected from the group consisting of argon, krypton, xenon, and combinations thereof and the molar flow rate of the noble gas is greater than the molar flow rate of the hydrocarbon source. A post-deposition termination step may be included, wherein the flow of the hydrocarbon source and the noble gas is stopped and a plasma is maintained in the chamber for a period of time to remove particles therefrom.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: Applied Materials, Inc.
    Inventors: DEENESH PADHI, Hyoung-Chan Ha, Sudha Rathi, Derek R. Witty, Chiu Chan, Sohyun Park, Ganesh Balasubramanian, Karthik Janakiraman, Martin Jay Seamons, Visweswaren Sivaramakrishnan, Bok Hoen Kim, Hichem M'Saad
  • Publication number: 20120208367
    Abstract: A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using CxHy gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.
    Type: Application
    Filed: June 15, 2011
    Publication date: August 16, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Tai Ho KIM
  • Patent number: 8242004
    Abstract: A method of forming a semiconductor device includes the following processes. A groove is formed in a semiconductor substrate. A first spin-on-dielectric layer is formed over a semiconductor substrate. An abnormal oxidation of the first spin-on-dielectric layer is carried out. A surface of the first spin-on-dielectric layer is removed. A second spin-on-dielectric layer is formed over the first spin-on-dielectric layer. A non-abnormal oxidation of the first and second spin-on-dielectric layers is carried out to modify the second spin-on-dielectric layer without modifying the first spin-on-dielectric layer.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: August 14, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Jiro Miyahara
  • Patent number: 8244482
    Abstract: A process system adapted for processing of or with a material therein. The process system includes: a sampling region for the material; an infrared photometric monitor constructed and arranged to transmit infrared radiation through the sampling region and to responsively generate an output signal correlative of the material in the sampling region, based on its interaction with the infrared radiation; and process control means arranged to receive the output of the infrared photometric monitor and to responsively control one or more process conditions in and/or affecting the process system.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: August 14, 2012
    Assignee: Advanced Technology Materials, Inc.
    Inventor: Jose I. Arno
  • Patent number: 8242033
    Abstract: Methods for making and/or treating articles of semiconducting material are disclosed. In various methods, a first article of semiconducting material is provided, the first article of semiconducting material is heated sufficiently to melt the semiconducting material, and the melted semiconducting material is solidified in a direction substantially parallel to a shortest dimension of the melted article of semiconducting material. Articles of semiconducting materials made by methods described herein are also disclosed.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: August 14, 2012
    Assignee: Corning Incorporated
    Inventors: Glen Bennett Cook, Prantik Mazumder, Balram Suman, Natesan Venkataraman
  • Patent number: 8242031
    Abstract: A method of depositing a silicon and nitrogen containing film on a substrate. The method includes introducing silicon-containing precursor to a deposition chamber that contains the substrate, wherein the silicon-containing precursor comprises at least two silicon atoms. The method further includes generating at least one radical nitrogen precursor with a remote plasma system located outside the deposition chamber. Moreover, the method includes introducing the radical nitrogen precursor to the deposition chamber, wherein the radical nitrogen and silicon-containing precursors react and deposit the silicon and nitrogen containing film on the substrate. Furthermore, the method includes annealing the silicon and nitrogen containing film in a steam environment to form a silicon oxide film, wherein the steam environment includes water and acidic vapor.
    Type: Grant
    Filed: September 27, 2010
    Date of Patent: August 14, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Abhijit Basu Mallick, Srinivas D. Nemani, Ellie Yieh
  • Publication number: 20120199912
    Abstract: Electron mobility and hole mobility is improved in long channel semiconductor devices and resistors by employing complementary stress liners. Embodiments include forming a long channel semiconductor device on a substrate, and forming a complementary stress liner on the semiconductor device. Embodiments include forming a resistor on a substrate, and tuning the resistance of the resistor by forming a complementary stress liner on the resistor. Compressive stress liners are employed for improving electron mobility in n-type devices, and tensile stress liners are employed for improving hole mobility in p-type devices.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Jan Hoentschel, Thilo Scheiper
  • Patent number: 8237216
    Abstract: Lanthanum-metal oxide dielectrics and methods of fabricating such dielectrics provide an insulating layer in a variety of structures for use in a wide range of electronic devices and systems. In an embodiment, a lanthanum-metal oxide dielectric is formed using a trisethylcyclopentadionatolanthanum precursor and/or a trisdipyvaloylmethanatolanthanum precursor. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: August 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8236670
    Abstract: A method of applying a pattern of metal, metal oxide, and/or semiconductor material on a substrate, a pattern created by that method, and uses of that pattern.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: August 7, 2012
    Assignees: Sony Deutschland GmbH, Forschungszentrum Juelich GmbH
    Inventors: Jurina Wessels, Akio Yasuda, Zoi Karipidou, Akos Schreiber, Marc Riedel, Daniel Schwaab, Dirk Mayer, Andreas Offenhaeusser
  • Patent number: 8236705
    Abstract: Embodiments of the invention provide methods and systems for depositing a viscous material on a substrate surface. In one embodiment, the invention provides a method of depositing a viscous material on a substrate surface, the method comprising: applying a pre-wet material to a surface of a substrate; depositing a viscous material atop the pre-wet material; rotating the substrate about an axis to spread the viscous material along the surface of the substrate toward a substrate edge; and depositing additional pre-wet material in a path along the surface and adjacent the spreading viscous material.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nitin H. Parbhoo, Spyridon Skordas
  • Patent number: 8236692
    Abstract: Efficient cleaning is possible although the film qualities and thicknesses of a reaction tube and a gas supply nozzle are different. There is provided a method of manufacturing a semiconductor device. The method includes forming a film on a substrate, performing a first cleaning process to remove a first deposition substance attached to an inner wall of a gas introducing part, and performing a second cleaning process to remove a second deposition substance attached to an inside of a process chamber and having a chemical composition different from that of the first deposition substance. In the first cleaning process, cleaning conditions are set according to the accumulated supply time of a first source gas supplied to the inside of the process chamber through the gas introducing part, and in the second cleaning process, cleaning conditions are set according to the accumulated thickness of a film formed on the substrate.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: August 7, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Tomohide Kato
  • Patent number: 8232182
    Abstract: A transfer layer includes a transparent substrate. A buffer layer is formed on the transparent substrate that comprises PbO, GaN, PbTiO3, La0.5Sr0.5CoO3 (LSCO), or LaxPb1-xCoO3 (LPCO) so that separation between the buffer layer and the transparent substrate occurs at substantially high temperatures.
    Type: Grant
    Filed: September 7, 2005
    Date of Patent: July 31, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Il-Doo Kim, Harry L. Tuller, Yong Woo Choi, Akintunde I. Akinwande
  • Publication number: 20120190211
    Abstract: In a film forming method, firstly, a processing target substrate W as a base of a semiconductor device is held on a mounting table 34 by an electrostatic chuck. Then, a film forming gas is adsorbed onto the processing target substrate W (a gas adsorption process) ((A) of FIG. 6). Thereafter, the inside of the processing chamber 32 is evacuated in order to remove residues of the film forming gas ((B) of FIG. 6). Upon the completion of the first exhaust process, a plasma process using microwave is performed ((C) of FIG. 6). Upon the completion of the plasma process, the inside of the processing chamber 32 is evacuated in order to remove an unreacted reactant gas and the like ((D) of FIG. 6). These series of steps (A) to (D) are repeated in this sequence until a desired film thickness is obtained.
    Type: Application
    Filed: September 9, 2010
    Publication date: July 26, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hirokazu Ueda, Yusuke Ohsawa, Masahiro Horigome
  • Publication number: 20120190185
    Abstract: A method of forming a semiconductor device is disclosed. Nitrogen layers of an IPD stack are deposited using silane and a nitrogen plasma to yield a nitride layer plasma treated through its entire thickness. In addition to nitriding the bottom nitride layer of the stack, the middle nitride layer may also be nitrided. Depositing silicon from silane in a nitrogen plasma may be accomplished using high density plasma, ALD, or remote plasma processes. Elevated temperature may be used during deposition to reduce residual hydrogen in the deposited layer.
    Type: Application
    Filed: January 16, 2012
    Publication date: July 26, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Matthew Scott Rogers
  • Patent number: 8227357
    Abstract: Methods of fabricating a silicon oxide layer using an inorganic silicon precursor and methods of fabricating a semiconductor device using the same are provided. The methods of fabricating a semiconductor device include forming a tunnel insulating layer and a charge storage layer on a substrate; forming a dielectric layer structure on the charge storage layer using an atomic layer deposition (ALD) method, the dielectric layer structure including a first dielectric layer formed of silicon oxide, a second dielectric layer on the first dielectric layer formed of a material different from the material forming the first dielectric layer, and a third dielectric layer formed of the silicon oxide on the second dielectric layer; and forming a control gate on the dielectric layer structure.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Sun Yi, Ki-Hyun Hwang, Jin-Tae Noh, Jae-Young Ahn, Si-Young Choi
  • Patent number: 8227346
    Abstract: Disclosed is a producing method of a semiconductor device comprising a first step of supplying a first reactant to a substrate to cause a ligand-exchange reaction between a ligand of the first reactant and a ligand as a reactive site existing on a surface of the substrate, a second step of removing a surplus of the first reactant, a third step of supplying a second reactant to the substrate to cause a ligand-exchange reaction to change the ligand after the exchange in the first step into a reactive site, a fourth step of removing a surplus of the second reactant, and a fifth step of supplying a plasma-excited third reactant to the substrate to cause a ligand-exchange reaction to exchange a ligand which has not been exchange-reacted into the reactive site in the third step into the reactive site, wherein the first to fifth steps are repeated predetermined times.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: July 24, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hironobu Miya, Kazuyuki Toyoda, Norikazu Mizuno, Taketoshi Sato, Masanori Sakai, Masayuki Asai, Kazuyuki Okuda, Hideki Horita
  • Patent number: 8222162
    Abstract: A batch processing method for forming a structure including an amorphous carbon film includes performing a preliminary treatment of removing water from a surface of the underlying layer by heating the inside of the reaction chamber at a preliminary treatment temperature of 800 to 950° C. and supplying a preliminary treatment gas selected from the group consisting of nitrogen gas and ammonia gas into the reaction chamber while exhausting gas from inside the reaction chamber; and, then performing main CVD of forming an amorphous carbon film on the underlying layer by heating the inside of the reaction chamber at a main process temperature and supplying a hydrocarbon gas into the reaction chamber while exhausting gas from inside the reaction chamber.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: July 17, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Mitsuhiro Okada, Yukio Tojo
  • Publication number: 20120178253
    Abstract: The inventive concept provides porous, low-k dielectric materials and methods of manufacturing and using the same. In some embodiments, porous, low-k dielectric materials are manufactured by forming a porogen-containing dielectric layer on a substrate and then removing at least a portion of said porogen from the layer.
    Type: Application
    Filed: September 23, 2011
    Publication date: July 12, 2012
    Inventors: Sang-Hoon Ahn, Kyu-Hee Han, Kyoung-Hee Kim, Gil-Heyun Choi, Byung-Hee Kim, Sang-Don Nam
  • Patent number: 8216861
    Abstract: Methods for the repair of damaged low k films are provided. Damage to the low k films occurs during processing of the film such as during etching, ashing, and planarization. The processing of the low k film causes water to store in the pores of the film and further causes hydrophilic compounds to form in the low k film structure. Repair processes incorporating ultraviolet (UV) radiation and carbon-containing compounds remove the water from the pores and further remove the hydrophilic compounds from the low k film structure.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Thomas Nowak, Bo Xie, Alexandros T. Demos
  • Publication number: 20120168957
    Abstract: A method of forming a device is disclosed. The method includes providing a substrate prepared with a dielectric layer having first and second regions. The first region comprises wide features and the second region comprises narrow features. A depth delta exists between bottoms of the wide and narrow features. A non-conformal layer is formed on the substrate and it lines the wide and narrow trenches in the first and second regions. The non-conformal layer is removed. Removing the non-conformal layer reduces the depth delta between the bottoms of the wide and narrow features in the first and second region.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicants: GLOBALFOUNDRIES SINGAPORE PTE. LTD., INTERNATIONAL BUSINESS MACHINES CORPORATION, TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., ADVANCED MICRO DEVICES CORPORATION
    Inventors: Ravi Prakash SRIVASTAVA, Oluwafemi O. OGUNSOLA, Craig CHILD, Muhammed Shafi Kurikka Valappil PALLACHALIL, Habib HICHRI, Matthew ANGYAL, Hideshi MIYAJIMA
  • Patent number: 8206788
    Abstract: In the manufacture of electronic devices that use porous dielectric materials, the properties of the dielectric in a pristine state can be altered by various processing steps. In a method for restoring and preserving the pristine properties of a porous dielectric layer, a substrate is provided with a layer of processed porous dielectric on top, whereby the processed porous dielectric is at least partially exposed. A thin aqueous film is formed at least on the exposed parts of the processed porous dielectric. The exposed porous dielectric with the aqueous film is exposed to an ambient containing a mixture comprising at least one silylation agent and dense CO2, resulting in the restoration and preservation of the pristine properties of the porous dielectric.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: June 26, 2012
    Assignee: IMEC
    Inventors: Fabrice Sinapi, Jan Alfons B. Van Hoeymissen
  • Publication number: 20120156373
    Abstract: Methods and compositions for depositing rare earth metal-containing layers are described herein. In general, the disclosed methods deposit the precursor compounds comprising rare earth-containing compounds using deposition methods such as chemical vapor deposition or atomic layer deposition. The disclosed precursor compounds include a cyclopentadienyl ligand having at least one aliphatic group as a substituent and an amidine ligand.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 21, 2012
    Applicant: American Air Liquide, Inc.
    Inventors: Venkateswara R. PALLEM, Christian DUSSARRAT, Wontae NOH
  • Patent number: 8202806
    Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: June 19, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P.S. Thakur, Ravi Iyer, Howard Rhodes
  • Patent number: 8202805
    Abstract: A method for processing a substrate including a processing target layer and an organic film, include: a deposition/trimming process of forming a reinforcement film on a surface of the organic film and, at the same time, trimming a line width of a line portion of the organic film constituting an opening pattern. The deposition/trimming process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto the surface of the organic film and an oxidation process in which the line width of the organic film is trimmed while the adsorbed silicon-containing gas is converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Masato Kushibiki, Eiichi Nishimura
  • Publication number: 20120149213
    Abstract: Provided are novel methods of filling gaps with a flowable dielectric material. According to various embodiments, the methods involve performing a surface treatment on the gap to enhance subsequent bottom up fill of the gap. In certain embodiments, the treatment involves exposing the surface to activated species, such as activated species of one or more of nitrogen, oxygen, and hydrogen. In certain embodiments, the treatment involves exposing the surface to a plasma generated from a mixture of nitrogen and oxygen. The treatment may enable uniform nucleation of the flowable dielectric film, reduce nucleation delay, increase deposition rate and enhance feature-to-feature fill height uniformity.
    Type: Application
    Filed: December 7, 2011
    Publication date: June 14, 2012
    Inventors: Lakshminarayana Nittala, Karena Shannon, Nerissa Draeger, Megha Rathod, Harald Te Nijenhuis, Bart Van Schravendijk, Michael Danek
  • Publication number: 20120149189
    Abstract: An integrated circuit with a passivation trapping layer. An integrated circuit with a hydrogen or deuterium releasing layer underlying a passivation trapping layer. Method for forming an integrated circuit having a hydrogen or deuterium releasing layer. Method for forming an integrated circuit having a passivation trapping layer.
    Type: Application
    Filed: February 14, 2012
    Publication date: June 14, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Gul B. Basim, Scott R. Summerfelt, Ted S. Moise
  • Patent number: 8193102
    Abstract: A method of assembling composite structures from objects in fluid includes providing a plurality of objects, each having a preselected size, shape, and spatial distribution of surface structural features characterizing a surface roughness; dispersing the objects into the fluid; and introducing a depletion agent. The depletion agent includes a plurality of particles having a size distribution preselected causing an attractive force arising from a depletion attraction between at least a first object and second object of the plurality in at least one relative position and orientation based on the preselected spatial distribution of surface structural features on the first and second objects, and the depletion attraction between the first and second objects forms at least one rigid bond or slippery bond at or proximate to respective surface portions based on the preselected spatial distribution of surface structural features on the first and second objects to form a two-object composite structure.
    Type: Grant
    Filed: November 14, 2008
    Date of Patent: June 5, 2012
    Assignee: The Regents of the University of California
    Inventors: Thomas G. Mason, Kun Zhao
  • Publication number: 20120135596
    Abstract: A method for forming a semiconductor structure includes providing a semiconductor layer, forming nanocrystals over the semiconductor layer, and using a solution comprising pure water, hydrogen peroxide, and ammonium hydroxide to remove at least a portion of the nanocrystals. A ratio by volume of pure water to ammonium hydroxide of the solution may be equivalent to or less than a ratio by volume of 10:1 of pure water to ammonium hydroxide when ammonium hydroxide has a concentration of 29% ammonia by weight. The step of using the solution to remove the at least a portion of the nanocrystals may be performed at a temperature of 50 degrees Celsius or more.
    Type: Application
    Filed: January 30, 2008
    Publication date: May 31, 2012
    Inventors: Sung-Taeg Kang, Jinmiao J. Shen
  • Publication number: 20120135611
    Abstract: A method includes forming an insulating film over a substrate by introducing a cyclic siloxane compound having a cyclic siloxane as a skeleton and having at least one volatile hydrocarbon group bonded to a side chain, and a silicon-containing compound into a plasma, and converting the insulating film to a porous insulating film by adding energy to the insulating film. The silicon-containing compound is decomposed using less energy as compared with the skeleton of the cyclic siloxane compound, the volatile hydrocarbon group, and the bond between the cyclic siloxane compound and the volatile hydrocarbon group.
    Type: Application
    Filed: February 1, 2012
    Publication date: May 31, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Fuminori ITO, Yoshihiro HAYASHI
  • Publication number: 20120135612
    Abstract: A film forming method is disclosed in which a thin film comprising manganese is formed on an object to be processed which has, on a surface thereof, an insulating layer constituted of a low-k film and having a recess. The method comprises a hydrophilization step in which the surface of the insulating layer is hydrophilized to make the surface hydrophilic and a thin-film formation step in which a thin film containing manganese is formed on the surface of the hydrophilized insulating layer by performing a film forming process using a manganese-containing material gas on the surface of the hydrophilized insulating layer. Thus, a thin film comprising manganese, e.g., an MnOx film, is effectively formed on the surface of the insulating layer constituted of a low-k film, which has a low dielectric constant.
    Type: Application
    Filed: June 16, 2010
    Publication date: May 31, 2012
    Applicants: NATIONAL UNIVERSITY CORPORATION TOHOKU UNIVERSITY, TOKYO ELECTRON LIMITED
    Inventors: Kenji Matsumoto, Hitoshi Itoh, Hidenori Miyoshi, Shigetoshi Hosaka, Hiroshi Sato, Koji Neishi, Junichi Koike
  • Publication number: 20120135610
    Abstract: A substrate processing system including a cleaning equipment; a resist coating equipment forming a resist layer on a surface of a substrate; an edge exposure equipment that exposes to light an edge portion of the resist layer formed on a peripheral edge of the substrate; a substrate transport mechanism; and a system controller. The system controller includes a waiting time monitor and a process controller. The waiting time monitor monitors a waiting time that is a time interval between the formation of the resist layer and start of the exposure of the edge portion of the resist layer. The process controller causes the substrate transport mechanism to transport the substrate into the cleaning equipment when the monitored waiting time exceeds a prescribed limit, removing the resist layer from the substrate. The process controller then causes the substrate transport mechanism to transport the substrate into the resist coating equipment.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 31, 2012
    Applicant: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Toshiyuki IDE
  • Patent number: 8187973
    Abstract: A method for manufacturing a semiconductor device which includes: alternately supplying a silicon source and an oxidant to deposit a silicon oxide film on a surface of a semiconductor substrate, wherein the silicon source is supplied under a supply condition where an adsorption amount of molecules of the silicon source on the semiconductor substrate is increased without causing an adsorption saturation of the molecules of the silicon source on the semiconductor substrate, and wherein the oxidant is supplied under a supply condition where impurities remain in the molecules of the silicon source adsorbed on the semiconductor substrate.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuyuki Sekine, Kazuhei Yoshinaga
  • Patent number: 8183166
    Abstract: A method for fabricating a dielectric layer structure includes providing a substrate, blanketly forming a low-k dielectric layer of an interlayer dielectric (ILD) layer, the low-k dielectric layer covering at least a first metal interconnect structure on the substrate, blanketly forming a single tensile film of the ILD layer having a thickness of 200-1500 angstroms on the low-k dielectric layer, and performing a moisture preventing treatment on the single tensile film. The single tensile layer possesses a stress comparative to a stress of the low-k dielectric layer and a hydrophobic characteristic that prevents itself from absorbing moisture.
    Type: Grant
    Filed: November 18, 2010
    Date of Patent: May 22, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chin-Hsiang Lin
  • Publication number: 20120122320
    Abstract: Provided are methods for re-incorporating carbon into low-k films after processes which result in depletion of carbon from the films. Additionally, methods for replenished depleted carbon and capping with tantalum nitride are also described.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 17, 2012
    Applicant: Applied Materials, Inc.
    Inventors: Annamalai Lakshmanan, Zhenjiang Cui, Mehul Naik, See-Eng Phan, Jennifer Shan, Paul F. Ma
  • Publication number: 20120108052
    Abstract: Electronic apparatus and methods of forming the electronic apparatus include a lanthanide yttrium aluminum oxide dielectric film on a substrate for use in a variety of electronic systems. The lanthanide yttrium aluminum oxide film may be structured as one or more monolayers. The lanthanide yttrium aluminum oxide film may be formed by a monolayer or partial monolayer sequencing process such as using atomic layer deposition.
    Type: Application
    Filed: January 9, 2012
    Publication date: May 3, 2012
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 8168546
    Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is has in its backbone, side chains, or both backbone and side chains, multiple secondary or tertiary amide groups that are represented by the following acetamide structure: >N—C(?O)—. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: May 1, 2012
    Assignee: Eastman Kodak Company
    Inventor: David H. Levy
  • Patent number: 8163647
    Abstract: An electronic device having a structure of an ohmic connection to a carbon element cylindrical structure body, wherein a metal material is positioned inside the junction part of a carbon element cylindrical structure body joined to a connection objective and the carbon element cylindrical structure body and the connection objective are connected by an ohmic contact. Methods for producing such an electronic device are also disclosed. Further, a method for growing a carbon nanotube is disclosed.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Akio Kawabata, Mizuhisa Nihei
  • Patent number: 8158536
    Abstract: While a fine porous diamond particle film has been known as a high heat resistant and low dielectric constant film and also has high mechanical strength and heat conductivity, and is expected as an insulating film for multi-layered wirings in semiconductor integrated circuit devices, it is insufficient in current-voltage characteristic and has not yet been put into practical use. According to the invention, by treating the fine porous diamond particle film with an aqueous solution of a salt of a metal such as barium and calcium, the carbonate or sulfate of which is insoluble or less soluble, and a hydrophobic agent such as hexamethyl disilazane or trimethyl monochlolo silane, as well as a reinforcing agent containing one of dichlorotetramethyl disiloxane or dimethoxytetramethyl disiloxane, thereby capable of putting the dielectric breakdown voltage and the leak current within a specified range of a practical standard.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 17, 2012
    Assignee: Rorze Corporation
    Inventors: Toshio Sakurai, Takayuki Takahagi, Hiroyuki Sakaue, Shoso Shingubara, Hiroyuki Tomimoto
  • Patent number: 8158209
    Abstract: Method and apparatus for coating a surface of a work with a thin resin or plastic film suitable for use in imprinting a pattern by impressing a master pattern on a transfer surface of a mold on the coated resin film. A curable resin liquid is coated on a work by the use of an inkjet feed means having a plural number of inkjet nozzle holes in a row or rows on a nozzle assembly, in association with actuators to propel droplets of resin liquid from the respective inkjet nozzle holes in controlled timings while moving the inkjet feed means and the work relative to each other.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 17, 2012
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Hideaki Kataho, Hiroshi Okada, Kenya Wada, Hisayoshi Ichikawa
  • Patent number: 8158201
    Abstract: A bi- or multi-layer coating is deposited upon a substrate using a low temperature process. The bi-layer is a lower layer of a SAM coating, which is overlaid with a hard coating. The hard coating can be made of materials such as: polymer, Si3N4, BN, TiN, Si02, Al203, Zr02, YSZ, and other ceramic materials, and the underlying, compliant, SAM coating can comprise substances containing long chain molecules that chemically bond to the substrate. This bi-layer provides both environmental and hermetical protection to electronic hardware and MEMS systems, without employing expensive packaging materials and processes. Multiple bi-layers may be combined to form multi-layer coatings. A protective polymer or other material may optionally be formed as an outside layer.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 17, 2012
    Assignee: The Research Foundation of State
    Inventors: Junghyun Cho, Scott Oliver, Wayne Jones, Bahgat Sammakia
  • Patent number: 8153537
    Abstract: There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 10, 2012
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Sai Hooi Yeong, Tao Wang, Shesh Mani Pandey, Chia Ching Yeo, Ying Keung Leung, Elgin Kiok Boone Quek
  • Patent number: 8154059
    Abstract: An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by forming a silicon oxide nitride film between the semiconductor layer of the TFT and a substrate, wherein the silicon oxide nitride film ranges from 0.3 to 1.6 in a ratio of the concentration of N to the concentration of Si.
    Type: Grant
    Filed: October 22, 2010
    Date of Patent: April 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masahiko Hayakawa, Mitsunori Sakama, Satoshi Toriumi
  • Patent number: 8153529
    Abstract: A chemical vapor deposition method such as an atomic-layer-deposition method for forming a patterned thin film includes applying a deposition inhibitor material to a substrate. The deposition inhibitor material is a hydrophilic polymer that is a neutralized acid having a pKa of 5 or less, wherein at least 90% of the acid groups are neutralized. The deposition inhibitor material is patterned simultaneously or subsequently to its application to the substrate, to provide selected areas of the substrate effectively not having the deposition inhibitor material. A thin film is substantially deposited only in the selected areas of the substrate not having the deposition inhibitor material.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 10, 2012
    Assignee: Eastman Kodak Company
    Inventor: David H. Levy
  • Patent number: 8153534
    Abstract: An oxidation method for performing direct oxidation includes respectively supplying an oxidizing gas and a deoxidizing gas to the process field, and directly oxidizing a surface target substrates by use of oxygen radicals and hydroxyl group radicals generated by a reaction between the oxidizing gas and the deoxidizing gas. The oxidizing gas is supplied through an oxidizing gas nozzle extending over a vertical length corresponding to the process field and is spouted from a plurality of gas spouting holes formed on the oxidizing gas nozzle and arrayed over the vertical length corresponding to the process field. The deoxidizing gas is supplied through a plurality of deoxidizing gas nozzles having different heights respectively corresponding to a plurality of zones of the process field arrayed vertically and is spouted from gas spouting holes respectively formed on the deoxidizing gas nozzles each at height of a corresponding zone.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: April 10, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Hisashi Inoue, Masataka Toiya, Yoshikatsu Mizuno
  • Patent number: 8148229
    Abstract: Disclosed is a method for manufacturing a semiconductor light-receiving device having high reproducibility and reliability. Specifically disclosed is a semiconductor light-receiving device 100 with a mesa structure wherein a light-absorbing layer 6, an avalanche multiplication layer 4 and an electric-field relaxation layer 5 are formed on a semiconductor substrate 2. The light-absorbing layer 6, avalanche multiplication layer 4 and electric-field relaxation layer 5 exposed in the side wall of the mesa structure are protected by an SiNx film or an SiOyNz film. The hydrogen concentration in the side wall surface of the electric-field relaxation layer 5 is set at not more than 15%, preferably not more than 10% of the carrier concentration of the electric-field relaxation layer 5.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: April 3, 2012
    Assignee: NEC Corporation
    Inventors: Kazuhiro Shiba, Kikuo Makita, Takeshi Nakata
  • Patent number: 8148197
    Abstract: A method of forming a material. The method comprises conducting an ALD layer cycle of a first metal, the ALD layer cycle comprising a reactive first metal precursor and a co-reactive first metal precursor. An ALD layer cycle of a second metal is conducted, the ALD layer cycle comprising a reactive second metal precursor and a co-reactive second metal precursor. An ALD layer cycle of a third metal is conducted, the ALD layer cycle comprising a reactive third metal precursor and a co-reactive third metal precursor. The ALD layer cycles of the first metal, the second metal, and the third metal are repeated to form a material, such as a GeSbTe material, having a desired stoichiometry. Additional methods of forming a material, such as a GeSbTe material, are disclosed, as is a method of forming a semiconductor device structure including a GeSbTe material.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: April 3, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Eugene P. Marsh
  • Publication number: 20120074535
    Abstract: The present disclosure provides a dielectric material including a low dielectric constant material and an additive. The additive includes a compound having a Si—X—Si bridge, where X is a number of carbon atoms between 1 and 8. The additive may include terminal Si—CH3 groups. The dielectric material including the additive may be used as an inter-layer dielectric (ILD) layer of a semiconductor device. The dielectric material including the additive may be formed using a CVD or sol-gel process. One example of the additive is bis(triethoxysilyl)ethene.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., ("TSMC")
    Inventors: Hsin-Yen Huang, Ching-Yu Lo, Hai-Ching Chen, Tien-I Bao