Insulative Material Deposited Upon Semiconductive Substrate Patents (Class 438/778)
  • Publication number: 20120077322
    Abstract: To provide a dielectric film having good crystallinity while suppressing an influence of the size effects and preventing the dielectric film from being divided by an Al-doped layer although there is provided the Al-doped layer for improving the leakage characteristics in the dielectric film of a capacitor, the dielectric film has at least one Al-doped layer, and an area density of Al atoms in one layer of the Al-doped layer is smaller than 1.4E+14? atoms/cm2. Further, to achieve the area density, there is employed a combination of formation of a dielectric film using a general ALD method and Al doping using an adsorption site blocking ALD method including adsorbing a blocker molecule restricting an adsorption site of an Al source, adsorbing the Al source, and introducing a reaction gas for reaction.
    Type: Application
    Filed: September 26, 2011
    Publication date: March 29, 2012
    Applicants: TOKYO ELECTRON LIMITED, ELPIDA MEMORY, INC.
    Inventors: Toshiyuki HIROTA, Takakazu KIYOMURA, Yuichiro MOROZUMI, Shingo HISHIYA
  • Patent number: 8143145
    Abstract: A method of producing, at atmospheric pressure, an n-type semiconductive indium sulfide thin film on a substrate using an indium-containing precursor, hydrogen sulfide as a reactive gaseous precursor, and an inert carrier gas stream includes cyclically repeating first and second steps so as to produce an indium sulfide thin film of a desired thickness. The first method phase includes converting the indium-containing precursor to at least one of a dissolved and a gaseous phase, heating the substrate to a temperature in a range of 100° C. to 275° C., directing the indium containing precursor onto the substrate and supplying hydrogen sulfide to the indium-containing precursor in a mixing zone in an amount so as to provide an absolute concentration of hydrogen sulfide that is greater than zero and no greater than 1% by volume. The indium concentration of the indium-containing precursor is set so as to produce a compact In(OHx,Xy,Sz)3 film, where X=halide and x+y+2z=1 with z?0.
    Type: Grant
    Filed: March 14, 2009
    Date of Patent: March 27, 2012
    Assignee: Helmholtz-Zentrum Berlin fuer Materialien und Energie GmbH
    Inventors: Nicholas Allsop, Christian-Herbert Fischer, Sophie Gledhill, Martha Christina Lux-Steiner
  • Patent number: 8143174
    Abstract: A method for providing a dielectric film having enhanced adhesion and stability. The method includes a post deposition treatment that densifies the film in a reducing atmosphere to enhance stability if the film is to be cured ex-situ. The densification generally takes place in a reducing environment while heating the substrate. The densification treatment is particularly suitable for silicon-oxygen-carbon low dielectric constant films that have been deposited at low temperature.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: March 27, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Li-Qun Xia, Frederic Gaillard, Ellie Yieh, Tian H. Lim
  • Patent number: 8143142
    Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: March 27, 2012
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Young-Soo Park, Gi-Jung Kim, Won-Je Park, Jae-Sik Bae
  • Patent number: 8138101
    Abstract: The present invention is provided in order to remove contamination due to contaminant impurities of the interfaces of each film which forms a TFT, which is the major factor that reduces the reliability of TFTs. By connecting a washing chamber and a film formation chamber, film formation can be carried out without exposing TFTs to the air during the time from washing step to the film formation step and it becomes possible to maintain the cleanliness of the interfaces of each film which form the TFT.
    Type: Grant
    Filed: April 17, 2007
    Date of Patent: March 20, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Shunpei Yamazaki
  • Publication number: 20120064732
    Abstract: According to one embodiment, a method is disclosed for determining position of an auxiliary pattern on a photomask. The method can include generating a first set for each of three or more imaging positions of an exposure optical system. The method can include generating a second set for each of the three or more imaging positions by inverse Fourier transforming each of the first set. The method can include calculating a second order differential with respect to the imaging position of an index indicating amplitude of light belonging to the second set. In addition, the method can include extracting a position where the second order differential assumes an extremal value on an imaging plane of the exposure optical system. At least part of positions on the photomask each corresponding to the position assuming the extremal value on the imaging plane is used as a formation position of the auxiliary pattern.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Inventors: Yasunobu Kai, Katsuyoshi Kodera
  • Patent number: 8129555
    Abstract: Aminosilane precursors for depositing silicon-containing films, and methods for depositing silicon-containing films from these aminosilane precursors, are described herein. In one embodiment, there is provided an aminosilane precursor for depositing silicon-containing film comprising the following formula (I): (R1R2N)nSiR34-n??(I) wherein substituents R1 and R2 are each independently chosen from an alkyl group comprising from 1 to 20 carbon atoms and an aryl group comprising from 6 to 30 carbon atoms, at least one of substituents R1 and R2 comprises at least one electron withdrawing substituent chosen from F, Cl, Br, I, CN, NO2, PO(OR)2, OR, SO, SO2, SO2R and wherein R in the at least one electron withdrawing substituent is chosen from an alkyl group or an aryl group, R3 is chosen from H, an alkyl group, or an aryl group, and n is a number ranging from 1 to 4.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 6, 2012
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Hansong Cheng, Manchao Xiao, Gauri Sankar Lal, Thomas Richard Gaffney, Chenggang Zhou, Jinping Wu
  • Patent number: 8129289
    Abstract: Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: March 6, 2012
    Assignee: Micron Technology, Inc.
    Inventors: John A. Smythe, Gurtej S. Sandhu, Brian J. Coppa, Shyam Surthi, Shuang Meng
  • Publication number: 20120045904
    Abstract: Embodiments of the disclosure generally provide methods of forming a hydrogen free silicon containing layer in TFT devices. The hydrogen free silicon containing layer may be used as a passivation layer, a gate dielectric layer, an etch stop layer, or other suitable layers in TFT devices, photodiodes, semiconductor diode, light-emitting diode (LED), or organic light-emitting diode (OLED), or other suitable display applications. In one embodiment, a method for forming a hydrogen free silicon containing layer in a thin film transistor includes supplying a gas mixture comprising a hydrogen free silicon containing gas and a reacting gas into a plasma enhanced chemical vapor deposition chamber, wherein the hydrogen free silicon containing gas is selected from a group consisting of SiF4, SiCl4, Si2Cl6, and forming a hydrogen free silicon containing layer on the substrate in the presence of the gas mixture.
    Type: Application
    Filed: August 20, 2011
    Publication date: February 23, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventor: Soo Young Choi
  • Patent number: 8119510
    Abstract: Provided is a manufacturing method of a semiconductor device including a gate insulating film which can be formed into a thin film and of which film composition is easy to be controlled. The manufacturing method includes: forming a manganese oxide film for serving as a gate insulating film on a semiconductor substrate, on which a transistor is formed; forming a conductive film for serving as a gate electrode on the manganese oxide film; and forming a gate electrode and a gate insulating film by processing the conductive film and the manganese oxide film.
    Type: Grant
    Filed: February 16, 2010
    Date of Patent: February 21, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Sato, Kenji Matsumoto, Hitoshi Itoh
  • Patent number: 8119541
    Abstract: Some example embodiments of the invention provide a method to improve the performance of MOS devices by increasing the stress in the channel region. An example embodiment for a NMOS transistor is to form a tensile stress layer over a NMOS transistor. A heavy ion implantation is performed into the stress layer and then an anneal is performed. This increases the amount of stress from the stress layer that the gate retains/memorizes thereby increasing device performance.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: February 21, 2012
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lee Wee Teo, Elgin Quek
  • Patent number: 8119540
    Abstract: A method for forming a stressed passivation film. In one embodiment, the method includes depositing a silicon nitride film over an integrated circuit structure on a substrate and embedding oxygen into a surface of the silicon nitride film by exposing the silicon nitride film to a process gas containing an oxygen-containing or an oxygen- and nitrogen-containing gas excited by plasma induced dissociation based on microwave irradiation via a plane antenna member having a plurality of slots, wherein the plane antenna member faces the substrate surface containing the silicon nitride film. The method further includes heat-treating the oxygen-embedded silicon nitride film to form a stressed silicon oxynitride film.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: February 21, 2012
    Assignee: Tokyo Electron Limited
    Inventor: Robert D Clark
  • Publication number: 20120040535
    Abstract: A semiconductor process of the present invention is described as follows. A substrate is provided, and a material layer is deposited on the substrate using an organic precursor as a reactant gas. A plasma treatment is conducted immediately after depositing the material layer, wherein plasma is continuously supplied during depositing the material layer and the plasma treatment. A pump-down step is conducted.
    Type: Application
    Filed: August 13, 2010
    Publication date: February 16, 2012
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chun Wang, Chun-Feng Chen
  • Patent number: 8114784
    Abstract: Integrated circuits (ICs) commonly contain pre-metal dielectric (PMD) liners with compressive stress to increase electron and hole mobilities in MOS transistors. The increase is limited by the thickness of the PMD liner. The instant invention is a multi-layered PMD liner in an integrated circuit which has a higher stress than single layer PMD liners. Each layer in the inventive PMD liner is exposed to a nitrogen-containing plasma, and which has a compressive stress higher than 1300 MPa. The PMD liner of the instant invention is composed of 3 to 10 layers. The hydrogen content of the first layer may be increased to improve transistor properties such as flicker noise and Negative Bias Temperature Instability (NBTI). An IC containing the inventive PMD liner and a method for forming same are also claimed.
    Type: Grant
    Filed: October 14, 2010
    Date of Patent: February 14, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Che-Jen Hu, Rajesh Khamankar
  • Patent number: 8114739
    Abstract: Methods are provided for fabricating a transistor. An exemplary method involves depositing an oxide layer overlying a layer of semiconductor material, forming an oxygen-diffusion barrier layer overlying the oxide layer, forming a layer of high-k dielectric material overlying the oxygen-diffusion barrier layer, forming a layer of conductive material overlying the layer of high-k dielectric material, selectively removing portions of the layer of conductive material, the layer of high-k dielectric material, the oxygen-diffusion barrier layer, and the oxide layer to form a gate stack, and forming source and drain regions about the gate stack. When the conductive material is an oxygen-gettering conductive material, the oxygen-diffusion barrier layer prevents diffusion of oxygen from the deposited oxide layer to the oxygen-gettering conductive material.
    Type: Grant
    Filed: September 28, 2009
    Date of Patent: February 14, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Murshed M. Chowdhury, James K. Schaeffer
  • Publication number: 20120034792
    Abstract: The present invention supplies a solvent to a front surface of a substrate while rotating the substrate. The substrate is acceleratingly rotated to a first number of rotations, and a resist solution is supplied to a central portion of the substrate during the accelerating rotation and the rotation at a first number of rotations. The substrate is deceleratingly rotated to a second number of rotations, and after the number of rotations of the substrate reaches the second number of rotations, the resist solution is discharged to the substrate. The substrate is then acceleratingly rotated to a third number of rotations higher than the second number of rotations so that the substrate is rotated at the third number of rotations. According to the present invention, consumption of the resist solution can be suppressed and a high in-plane uniformity can be obtained for the film thickness of the resist film.
    Type: Application
    Filed: September 20, 2011
    Publication date: February 9, 2012
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kousuke YOSHIHARA, Tomohiro Iseki
  • Publication number: 20120032309
    Abstract: There is provided an ink composition for forming a light shielding film in an organic semiconductor device which is capable of stably forming a fine pattern when forming a finely patterned light shielding film by the letterpress reverse printing method or microcontact printing method, which can be baked at a temperature equal to or less than the substrate heatproof temperature, and which is also capable of providing light shielding property and mechanical strength, the ink composition for forming a light shielding film in an organic semiconductor device which is an ink composition for forming a light shielding film in an organic semiconductor device comprising a black pigment; a resin component; a surface energy modifier; a quick-drying organic solvent; a slow-drying organic solvent; and a mold releasing agent, wherein the resin component comprises a solid resin that is in a solid state at 200° C. or less and a liquid resin that is in a liquid state at 10 to 50° C. at a ratio (solid resin/liquid resin) of 0.
    Type: Application
    Filed: April 26, 2010
    Publication date: February 9, 2012
    Applicant: DIC Corporation
    Inventors: Hideki Etori, Hiroshi Isozumi, Masanori Kasai
  • Publication number: 20120032280
    Abstract: A method of forming an integrated circuit (IC) having at least one MOS device includes forming a SiON gate dielectric layer on a silicon surface. A gate electrode layer is deposited on the SiON gate layer and then patterning forms a gate stack. Exposed gate dielectric sidewalls are revealed by the patterning. A supplemental silicon oxide layer is formed on the exposed SiON sidewalls followed by nitriding. After nitriding, a post nitridation annealing (PNA) forms an annealed N-enhanced SiON gate dielectric layer including N-enhanced SiON sidewalls, wherein along lines of constant thickness a N concentration at the N-enhanced SiON sidewalls is ? the N concentration in a bulk of the annealed N-enhanced SiON gate layer ?2 atomic %. A source and drain region on opposing sides of the gate stack are formed to define a channel region under the gate stack.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 9, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian K. Kirkpatrick, James Joseph Chambers
  • Patent number: 8110435
    Abstract: A method and apparatus for manufacturing a semiconductor device is disclosed, which is capable of realizing an extension of a cleaning cycle for a processing chamber, the method comprising preheating a substrate; placing the preheated substrate onto a substrate-supporting unit provided in a susceptor while the preheated substrate is maintained at a predetermined height from an upper surface of the susceptor provided in a processing chamber; and forming a thin film on the preheated substrate, wherein a temperature of the preheated substrate is higher than a processing temperature for forming the thin film in the processing chamber.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: February 7, 2012
    Assignee: Jusung Engineering Co., Ltd.
    Inventors: Sang Ki Park, Seong Ryong Hwang, Geun Tae Cho
  • Patent number: 8110891
    Abstract: Methods for forming dielectric layers, and structures and devices resulting from such methods, and systems that incorporate the devices are provided. The invention provides an aluminum oxide/silicon oxide laminate film formed by sequentially exposing a substrate to an organoaluminum catalyst to form a monolayer over the surface, remote plasmas of oxygen and nitrogen to convert the organoaluminum layer to a porous aluminum oxide layer, and a silanol precursor to form a thick layer of silicon dioxide over the porous oxide layer. The process provides an increased rate of deposition of the silicon dioxide, with each cycle producing a thick layer of silicon dioxide of about 120 ? over the layer of porous aluminum oxide.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: February 7, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Chris W Hill, Garo J Derderian
  • Publication number: 20120025303
    Abstract: In one embodiment, a field effect transistor has a semiconductor body, a drift region of a first conductivity type and a gate electrode. At least one trench extends into the drift region. A field plate is arranged at least in a portion of the at least one trench. A dielectric material at least partially surrounds both the gate electrode and the field plate. The field plate includes a first semiconducting material.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 2, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Franz Hirler, Walter Rieger, Andrew Wood, Mathias Born, Ralf Siemieniec, Jan Ropohl, Martin Poelzl, Oliver Blank, Uli Hiller, Oliver Haeberlen, Rudolf Zelsacher, Maximilian Roesch, Joachim Krumrey
  • Publication number: 20120028474
    Abstract: A method for forming a conductive thin film includes depositing a metal oxide thin film on a substrate by an atomic layer deposition (ALD) process. The method further includes at least partially reducing the metal oxide thin film by exposing the metal oxide thin film to a reducing agent, thereby forming a seed layer. In one arrangement, the reducing agent comprises one or more organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO, and —COOH. In another arrangement, the reducing agent comprises an electric current.
    Type: Application
    Filed: June 3, 2011
    Publication date: February 2, 2012
    Inventors: Juhana Kostamo, Pekka J. Soininen, Kai-Erik Elers, Suvi Haukka
  • Publication number: 20120028382
    Abstract: A semiconductor device having a semiconductor chip having an active surface with flip-chip contacts and a passive surface is disclosed. In one embodiment, the flip-chip contacts are surrounded by an electrically insulating layer as underfill material, the layer having a UV B-stageable material. The UV B-stageable material is applied on the active surface of the semiconductor wafer.
    Type: Application
    Filed: October 11, 2011
    Publication date: February 2, 2012
    Applicant: Infineon Technologies AG
    Inventors: Michael Bauer, Edward Fuergut
  • Publication number: 20120025392
    Abstract: When forming complex metallization systems, a sensitive material, such as a ULK material, may be deposited on a silicon-containing dielectric material, such as an etch stop material, with superior adhesion by performing a surface treatment on the basis of fluorine radicals. Due to the fluorine treatment, silicon-fluorine bonds are generated, which are then broken up upon interacting with the chemically active component during the further deposition process. Consequently, the subsequent material layer is chemically bonded to the underlying material, thereby imparting superior stability to the interface, which in turn may result in superior robustness and reliability of the metallization system upon performing reflowing processes and operating complex packaged semiconductor devices.
    Type: Application
    Filed: May 25, 2011
    Publication date: February 2, 2012
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Christof Streck, Hartmut Ruelke, Heinz-Juergen Voss
  • Patent number: 8105957
    Abstract: Disclosed is a producing method of a semiconductor device comprising a first step of supplying a first reactant to a substrate to cause a ligand-exchange reaction between a ligand of the first reactant and a ligand as a reactive site existing on a surface of the substrate, a second step of removing a surplus of the first reactant, a third step of supplying a second reactant to the substrate to cause a ligand-exchange reaction to change the ligand after the exchange in the first step into a reactive site, a fourth step of removing a surplus of the second reactant, and a fifth step of supplying a plasma-excited third reactant to the substrate to cause a ligand-exchange reaction to exchange a ligand which has not been exchange-reacted into the reactive site in the third step into the reactive site, wherein the first to fifth steps are repeated predetermined times.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: January 31, 2012
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Hironobu Miya, Kazuyuki Toyoda, Taketoshi Sato, Masayuki Asai, Norikazu Mizuno, Masanori Sakai, Kazuyuki Okuda, Hideki Horita
  • Patent number: 8105947
    Abstract: Methods for improving post etch in via or trench formation in semiconductor devices. A preferred embodiment comprises forming a re-capping layer over a dielectric film following an initial etch to form a feature in the dielectric film, followed by additional etch and etch back processing steps. The re-capping method provides protection for underlying films and prevents film damage post etch. Uniform feature profiles are maintained and critical dimension uniformity is obtained by use of the methods of the invention. The time dependent dielectric breakdown performance is increased.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: January 31, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shwang-Ming Jeng, Kin-Weng Wang, Hsin-Yi Tsai, Keng-Chu Lin, Chung-Chi Ko
  • Publication number: 20120021587
    Abstract: A method of forming (and apparatus for forming) a metal oxide layer, preferably a dielectric layer, on a substrate, particularly a semiconductor substrate or substrate assembly, using a vapor deposition process and ozone with one or more metal organo-amine precursor compounds.
    Type: Application
    Filed: September 30, 2011
    Publication date: January 26, 2012
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Brian A. Vaartstra, Timothy A. Quick
  • Publication number: 20120003841
    Abstract: A method of manufacturing a semiconductor device includes: a step of forming a porous dielectric film on a substrate; a step of disposing the substrate having the porous dielectric film formed thereon inside a chamber; a step of introducing siloxane into the chamber in which the substrate is disposed and heating the substrate to a first temperature; and a step heating the substrate to which the introduced siloxane adheres to a second temperature higher than the first temperature. A pressure inside the chamber is maintained to be equal to or lower than 1 kPa. In the present embodiment, the first temperature is equal to or higher than a temperature at which the pressure inside the chamber is a saturated vapor pressure of the siloxane, and is equal to or lower than a temperature at which a polymerization between the porous dielectric film and the siloxane starts.
    Type: Application
    Filed: March 18, 2010
    Publication date: January 5, 2012
    Applicant: ULVAC, INC.
    Inventors: Shinichi Chikaki, Takahiro Nakayama
  • Patent number: 8089138
    Abstract: A surface-hydrophobicized film is provided which is in contact with an insulating film, and has a higher hydrophobicity than the insulating film at the time of the contact, and which is in contact, on an opposite side of the surface-hydrophobicized film, with wiring, and contains at least one atom selected from the group consisting of sulfur atoms, phosphorus atoms and nitrogen atoms. Semiconductor devices with wiring layers having a low leakage current, a high EM resistance and a high TDDB resistance can be manufactured by using the film.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata
  • Publication number: 20110318942
    Abstract: A mechanically robust semiconductor structure with improved adhesion strength between a low-k dielectric layer and a dielectric-containing substrate is provided. In particular, the present invention provides a structure that includes a dielectric-containing substrate having an upper region including a treated surface layer which is chemically and physically different from the substrate; and a low-k dielectric material located on a the treated surface layer of the substrate. The treated surface layer and the low-k dielectric material form an interface that has an adhesion strength that is greater than 60% of the cohesive strength of the weaker material on either side of the interface. The treated surface is formed by treating the surface of the substrate with at least one of actinic radiation, a plasma and e-beam radiation prior to forming of the substrate the low-k dielectric material.
    Type: Application
    Filed: September 9, 2011
    Publication date: December 29, 2011
    Applicant: International Business Machines Corporation
    Inventors: Qinghuang Lin, Terry A. Spooner, Darshan D. Gandhi, Christy S. Tyberg
  • Publication number: 20110318941
    Abstract: A solar cell includes a first electrode located over a substrate, at least one p-type semiconductor absorber layer located over the first electrode, the p-type semiconductor absorber layer comprising a copper indium selenide (CIS) based alloy material, an n-type semiconductor layer located over the p-type semiconductor absorber layer, an insulating aluminum zinc oxide layer located over the n-type semiconductor layer, the insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm and a second electrode over the insulating aluminum layer, the second electrode being transparent and electrically conductive. The insulating aluminum zinc oxide having an aluminum content of 100 ppm to 5000 ppm, may be deposited by pulsed DC, non-pulsed DC, or AC sputtering from an aluminum doped zinc oxide having an aluminum content of 100 ppm to 5000 ppm.
    Type: Application
    Filed: September 1, 2011
    Publication date: December 29, 2011
    Inventors: Chris Schmidt, Bruce Hachtmann
  • Patent number: 8084373
    Abstract: A manufacturing method of a semiconductor device is provided which can uniformly form a good and thin silicon oxide film or the like at a relatively low temperature. In step 1, a semiconductor substrate is exposed to monosilane (SiH4). Then, in step 2, the remaining monosilane (SiH4) is emitted. In step 3, the semiconductor substrate is exposed to nitrous oxide plasma. A desired silicon oxide film is formed by repeating one cycle including steps 1 to 3 until a necessary thickness of the film is obtained.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 27, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsunori Murata, Yoshihiro Miyagawa
  • Patent number: 8084370
    Abstract: Electronic apparatus and methods may include a hafnium tantalum oxynitride film on a substrate for use in a variety of electronic systems. The hafnium tantalum oxynitride film may be structured as one or more monolayers. The hafnium tantalum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a hafnium tantalum oxynitride film.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: December 27, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Leonard Forbes, Kie Y. Ahn, Arup Bhattacharyya
  • Patent number: 8084371
    Abstract: Field effect transistors, methods of fabricating a carbon insulating layer using molecular beam epitaxy and methods of fabricating a field effect transistor using the same are provided, the methods of fabricating the carbon insulating layer include maintaining a substrate disposed in a molecular beam epitaxy chamber at a temperature in a range of about 300° C. to about 500° C. and maintaining the chamber in vacuum of 10?11 Torr or less prior to performing an epitaxy process, and supplying a carbon source to the chamber to form a carbon insulating layer on the substrate. The carbon insulating layer is formed of diamond-like carbon and tetrahedral amorphous carbon.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: December 27, 2011
    Assignees: Samsung Electronics Co., Ltd., The Board of Trustees of the Leland Stanford Junior University
    Inventors: David Seo, Jai-kwang Shin, Sun-ae Seo
  • Publication number: 20110308603
    Abstract: A method of passivating a silicon surface is disclosed. In one aspect, the method includes cleaning the silicon surface by subjecting the silicon surface to a sequence of steps wherein the final step is a chemical oxidation step resulting in a hydrophilic silicon surface. The method may also include drying the cleaned silicon surface using an advanced drying technique, and/or depositing an oxide layer on the silicon surface.
    Type: Application
    Filed: June 17, 2011
    Publication date: December 22, 2011
    Applicants: Katholieke Universiteit Leuven, IMEC
    Inventors: Bart Vermang, Aude Rothschild, Twan Bearda
  • Publication number: 20110312190
    Abstract: A coating method based on such a technique includes a prewetting step of supplying a prewetting liquid to the center of a substrate (W) and rotating the substrate thereby spreading the prewetting liquid over the whole surface of a first substrate, and a coating film forming step of supplying a coating solution (e.g., a resist solution) to the substrate supplied with the prewetting liquid and drying the coating solution thereby forming a coating film on the surface of the first substrate. The prewetting liquid used is a mixed liquid obtained by mixing a solvent capable of dissolving components of the coating film (e.g., components of resist) and a high surface tension liquid having a surface tension higher than that of the solvent, the mixed liquid having a surface tension higher than that of the coating solution.
    Type: Application
    Filed: June 16, 2011
    Publication date: December 22, 2011
    Applicant: Tokyo Electron Limited
    Inventors: Katsunori Ichino, Kentaro Yoshihara, Kousuke Yoshihara
  • Patent number: 8080483
    Abstract: A method of forming a nanoporous film is disclosed. The method comprises forming a coating solution including clusters, surfactant molecules, a solvent, and one of an acid catalyst and a base catalyst. The clusters comprise inorganic groups. The method further comprises aging the coating solution for a time period to select a predetermined phase that will self-assemble and applying the coating solution on a substrate. The method further comprises evaporating the solvent from the coating solution and removing the surfactant molecules to yield the nanoporous film.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: December 20, 2011
    Assignee: Purdue Research Foundation
    Inventors: Hugh W. Hillhouse, Vikrant N. Urade, Ta-Chen Wei, Michael P. Tate
  • Patent number: 8080466
    Abstract: Embodiments described herein generally relate to apparatus and methods for forming Group III-V materials by metal-organic chemical vapor deposition (MOCVD) processes and hydride vapor phase epitaxial (HVPE) processes. In one embodiment, a method for fabricating a nitrogen-face (N-face) polarity compound nitride semiconductor device is provided. The method comprises depositing a nitrogen containing buffer layer having N-face polarity over one or more substrates using a metal organic chemical vapor deposition (MOCVD) process to form one or more substrates having N-face polarity and depositing a gallium nitride (GaN) layer over the nitrogen containing buffer layer using a hydride vapor phase epitaxial (HVPE) deposition process, wherein the nitrogen containing buffer layer and the GaN layer are formed without breaking vacuum and exposing the one or more substrates to atmosphere.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: December 20, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Jie Su, Olga Kryliouk, Yuriy Melnik
  • Publication number: 20110297963
    Abstract: A silicon carbide semiconductor device is provided that includes a semiconductor layer made of silicon carbide and having a surface with a trench having a sidewall formed of a crystal plane tilted at an angle in a range of not less than 50° and not more than 65° relative to the {0001} plane, and an insulating film formed to contact the sidewall of the trench. A maximum value of the nitrogen concentration in a region within 10 nm from the interface between the sidewall of the trench and the insulating film is not less than 1×1021 cm?3, and the semiconductor device has a channel direction in a range of ±10° relative to the direction orthogonal to the <?2110> direction in the sidewall of the trench. A method of manufacturing the silicon carbide semiconductor device is also provided.
    Type: Application
    Filed: January 27, 2010
    Publication date: December 8, 2011
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Misako Honaga, Shin Harada
  • Patent number: 8067315
    Abstract: A nitrogen-containing silicon carbide material may be deposited on the basis of a single frequency or mixed frequency deposition recipe with a high internal compressive stress level up to 1.6 GPa or higher. Thus, this dielectric material may be advantageously used in the contact level of sophisticated integrated circuits, thereby providing high strain levels while not unduly contributing to signal propagation delay.
    Type: Grant
    Filed: March 2, 2009
    Date of Patent: November 29, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marcus Stadel, Sven Auerswald
  • Patent number: 8066806
    Abstract: A sintered silicon oxide for film vapor deposition having a density of 1.0 to 2.0 g/cm3, three-point flexural strength of at least 50 g/mm2, and a BET specific surface area of 0.1 to 20 m2/g is provided. When this sintered silicon oxide is used for evaporation source of a film, pin holes and other defects of the film caused by the problematic splash phenomenon can be reliably prevented and stable production of a reliable package material having excellent gas barrier property is been enabled. This invention also provides a method for producing such sintered silicon oxide, and this method can be used in a large scale production without requiring any special technology, and therefore, this method is capable of supplying the market with the sintered silicon oxide at reduced cost.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 29, 2011
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventors: Hirofumi Fukuoka, Meguru Kashida, Toshio Ohba
  • Publication number: 20110284801
    Abstract: The invention relates to a process of preparing functional layers, like protection, encapsulation and alignment layers, on an electronic device by a low energy particle beam deposition process, to functional layers obtainable by said process, and to electronic devices comprising such functional layers.
    Type: Application
    Filed: November 18, 2009
    Publication date: November 24, 2011
    Applicant: Merck Patent Gesellschaft Mit Beschrankter Haftung
    Inventors: Michael Coelle, Owain Llyr Parri, David Sparrowe, Oleg Yaroshchuk, Eugene Telesh
  • Publication number: 20110284079
    Abstract: A method of manufacturing a solar cell having an effective minority charge carrier lifetime (?eff) of at least 500 ?s, said method comprising: providing a semiconductor wafer; and passivating a surface of said wafer by ALD-depositing a metal oxide layer on said surface by sequentially and alternatingly: (iii) exposing said surface to a first precursor, resulting in a coverage of the surface with the first precursor, and (iv) exposing said surface to a second precursor, resulting in a coverage of the surface with the second precursor, wherein at least one of steps (i) and (ii) is stopped before the coverage of the surface reaches a saturation level.
    Type: Application
    Filed: May 20, 2011
    Publication date: November 24, 2011
    Inventor: Dieter Pierreux
  • Patent number: 8058183
    Abstract: A method for restoring the dielectric constant of a low dielectric constant film is described. A porous dielectric layer having a plurality of pores is formed on a substrate. The plurality of pores is then filled with an additive to provide a plugged porous dielectric layer. Finally, the additive is removed from the plurality of pores.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: November 15, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, May Yu, Alexandros T. Demos, Mehul Naik
  • Publication number: 20110275226
    Abstract: The invention concerns a process to treat a structure of semiconductor-on-insulator type structure of a carrier substrate, an oxide layer and a thin layer of a semiconductor material, wherein the structure having a peripheral ring in which the oxide layer is exposed, and the process includes the application of a main thermal treatment in a neutral or controlled reducing atmosphere. The method includes a step to cover at least an exposed peripheral part of the oxide layer, prior to the main thermal treatment, this latter treatment being conducted under controlled time and temperature conditions so as to urge at least part of the oxygen in the oxide layer to diffuse through the thin semiconductor layer, leading to controlled reduction of the thickness of the oxide layer.
    Type: Application
    Filed: December 30, 2009
    Publication date: November 10, 2011
    Inventors: Didier Landru, Fabrice Gritti, Eric Guiot, Oleg Kononchuk, Christelle Veytizou
  • Publication number: 20110275166
    Abstract: The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).
    Type: Application
    Filed: May 6, 2011
    Publication date: November 10, 2011
    Inventors: Eric J. Shero, Petri I. Raisanen, Sung-Hoon Jung, Chang-Gong Wang
  • Patent number: 8053375
    Abstract: An ultra low k dielectric film, including a silicon film containing porosity deriving from a porogen, as formed from a precursor silane and a porogen, wherein the precursor silane has a water content below 10 ppm, based on total weight of the precursor silane, and/or the porogen has a water content below 10 ppm, based on total weight of the porogen. In one implementation, the precursor silane is diethoxymethylsilane, and the porogen is bicyclo[2.2.1]-hepta-2,5-diene having a trace water content below 10 ppm, based on total weight of said bicyclo[2.2.1]-hepta-2,5-diene. These super-dry reagents are unexpectedly polymerization-resistant during their delivery and deposition in the formation of ultra low k films, and are advantageously employed to produce ultra low k films of superior character.
    Type: Grant
    Filed: October 27, 2007
    Date of Patent: November 8, 2011
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Chongying Xu, Jeffrey F. Roeder, Thomas H. Baum, Steven M. Bilodeau, Scott Battle, William Hunks, Tianniu Chen
  • Publication number: 20110266660
    Abstract: An object is to provide an insulating film for a semiconductor device which has characteristics of a low permittivity, a low leakage current, and a high mechanical strength, undergoes less change in these characteristics with the elapse of time, and has an excellent water resistance, as well as to provide a process and an apparatus for producing the insulating film for a semiconductor device, a semiconductor device, and a process for producing the semiconductor device.
    Type: Application
    Filed: June 25, 2009
    Publication date: November 3, 2011
    Applicants: MITSUBISHI ELECTRIC CORPORATION, MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Hidetaka Kafuku, Toshihito Fujiwara, Toshihiko Nishimori, Tadashi Shimazu, Naoki Yasuda, Hideharu Nobutoki, Teruhiko Kumada, Takuya Kamiyama, Tetsuya Yamamoto, Shinya Shibata
  • Publication number: 20110266684
    Abstract: Additive processes are employed for electrically insulating selected surface regions on a stack of die; and methods for electrically interconnecting die in a stack of die, include additive processes for electrically insulating selected surface regions of the die. Regions that are not insulated according to the invention are available for electrical connection using electrically conductive material applied in flowable form to make electrically conductive traces.
    Type: Application
    Filed: October 27, 2010
    Publication date: November 3, 2011
    Applicant: Vertical Circuits, Inc.
    Inventor: Jeffrey S. Leal
  • Publication number: 20110260223
    Abstract: The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.
    Type: Application
    Filed: April 27, 2010
    Publication date: October 27, 2011
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ru-Shang HSIAO, Nai-Wen CHENG, Chung-Te LIN, Chien-Hsien TSENG, Shou-Gwo WUU