Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

Abstract: Systems and methods are provided for causing display of a graphical user interface for designing at least one visualization, receiving data defining a first visualization control, receiving a least one data model defining at least one data source related to the first visualization control, and receiving at least one calculation module defining calculation details for the first visualization control. Further, the systems and methods are provided for generating an analytical instance for the at least one visualization comprising the first visualization control, the at least one data model, and the at least one calculation module, and uploading to a server system a specification associated with the analytical instance.

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.

Abstract: A system includes a runtime generator implemented in programmable circuitry of an integrated circuit, wherein the runtime generator is parameterizable at runtime of the integrated circuit to perform at least one of detecting a symbol pattern within a data stream or generating pseudo random number binary sequences. The system can include a processor configured to execute program code, wherein the processor is configured to provide first parameterization data to the runtime generator. In response to receiving the first parameterization data from the processor at runtime of the integrated circuit, the runtime generator implements a first automaton circuit configured to perform the at least one of the detecting the symbol pattern or the generating the pseudo random number binary sequences.

Abstract: A method, system, and apparatus provide the ability to design a circuit. A behavior of the circuit is authored by dragging nodes from side panels and connecting them in an authoring canvas. Multiple circuit designs that satisfy the behavior are generated. A data grid table is generated and displays the circuit designs with each row representing a design, and the table is sortable based on columns that represent computed metrics. Upon selection of a design in the table, a computer generated circuit diagram is rendered. Interactive assembly instructions are generated and displayed. The interactive assembly instructions provide a text-based step-by-step guide to wire the circuit. Further, upon selection of an assembly instruction step, a corresponding element in the computer generated circuit diagram is highlighted.

Abstract: A cell-aware defect characterization method includes partitioning a multibit cell netlist file into multiple single-bit partition netlist files, and then generating a cell-aware test model for each partition netlist file. Partitioning is performed such that each partition netlist file includes a corresponding flip-flop along with input, output and control pins that are operably coupled to the input, output and control terminals of the corresponding flip-flop, and all active, passive and parasitic circuit elements that are coupled in the signal paths extending between the corresponding flip-flop and the input/output/control pins. Shared resources (e.g., clock or scan select pins and associated signal lines) that are utilized by two or more flip-flops are included in each associated partition. The partitioning process is performed using either a structural back-tracing approach or a logic simulation approach.

Abstract: A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

Abstract: Digital logic circuitry includes a plurality of logic blocks and memories that execute a method to stitch images. The method includes capturing the images with a plurality of pixel sensors, providing blocks of intensity values captured by the pixel sensors to input/output (I/O) pins of the digital logic circuitry, processing the intensity values with the digital logic circuitry, and stitching the processed images into a stitched image.

Abstract: A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering operation on a plurality of pins in a first cell of the cells, based on physical information regarding the pins in the first cell, wherein the physical information is determined based on the placement of the cells, performing a routing operation on the cells after the pin reordering operation, and manufacturing the integrated circuit, based on a layout produced by the routing operation.

Abstract: A memory system (e.g. a solid state drive) includes one or more non-volatile memory die, a controller in communication with the memory die and a compute engine inside the memory system that is near the location of the data and can be used to perform common data manipulation operations.

Abstract: An integrated circuit having programmable logic fabric, as well as system and method for computer aided design using such integrated circuit, are disclosed. This integrated circuit includes: a configurable bypassable flip-flop circuit configured to transfer information from programmable internal routing to an input bus of a programmable logic circuit; a loopback branch connected to the input bus to bypass the programmable logic circuit; and a multiplexer having a first input port connected to the loopback branch, a second input port connected to an output bus of the programmable logic circuit, and an output port connected to routing switches of the programmable internal routing. The multiplexer is configured to electrically couple either the first input port or the second input port to the output port.

Abstract: This application discloses a computing system to select a design block in a circuit design of an electronic device for functional verification result reuse based on isolating operational characteristics of the design block. The computing system can determine whether the selected design block was previously simulated with input stimulus. When the selected design block was previously simulated with the input stimulus, the computing system can bypass the simulation of the design block and utilize an output generated in the previous simulation of the selected design block in response to the input stimulus as a result for the simulation of the design block. When the selected design block was not previously simulated with the input stimulus, the computing system can simulate the selected design block with the input stimulus, and storing an output generated in the simulation of the selected design block for functional verification result reuse.

Abstract: Creating by a computer an integrated circuit with non-linear variations, the computer identifies an integrated circuit design; identifies a timing model associated with the identified integrated circuit design; defines one or more static single sided variables; defines one or more regions of the defined one or more static single sided variables that are treated linearly; defines one or more multi-sided variables based on the defined one or more regions of the defined one or more static single sided variables; identifies one or more timing paths within the identified integrated circuit design; performs a statistical static timing analysis on the identified timing model for the identified one or more timing paths within the identified integrated circuit design utilizing the defined one or more multi-sided variables; provides one or more timing quantities that project within a multi-parameter space based on the performed statistical static timing analysis.

Abstract: A method for building, optimizing, and maintaining a computing infrastructure on a cloud computing environment is provided. A user provides a high-level declaration to a cloud environment operating system, specifying the details of the infrastructure that is intended to be built on the cloud. A cloud environment operating system converts the high level declaration to a lower level declaration and then to a series of instructions that can be executed by the cloud to build the desired infrastructure. The cloud environment operating system can also continuously monitor the infrastructure once it is built on the cloud. If the cloud environment operating system notices any discrepancies between the user's original specification and the infrastructure as built on the cloud, the operating system can work to modify the existing infrastructure on the cloud to conform to the infrastructure specified by a user.

Abstract: A method includes receiving a first circuit design, deriving circuit design revisions based on the first circuit design, receiving revision information for each of the circuit design revisions that is output as a result of compilation of the circuit design revisions, extracting location information, timing information, or both for resources from the revision information, for each of the circuit design revisions, mapping the resources into a chip view based on the location information, the timing information, or both. The chip view includes a virtual visualization of an actual physical chip and the resources are mapped to their actual locations on the virtual visualization as they would be implemented on the actual physical chip. The method also includes generating the chip view of the circuit design revisions that displays a report specific to one or more properties of the circuit design revisions.

Abstract: A circuit modeling system includes a store a first net list. The first net list includes a plurality of semiconductor devices, a first power distribution network (PDN) connected to the plurality of semiconductor devices, and a signal network connected to the plurality of semiconductor devices that transmits signals to the plurality of semiconductor devices. A circuit simulation unit is configured to identify first semiconductor devices and second semiconductor devices from among the plurality of semiconductor devices. The first semiconductor devices are activated by receiving a signal through the signal network, and the second semiconductor devices are inactive. The circuit simulation unit is configured to reduce the first PDN to a second PDN based on the identified first semiconductor devices, and to generate a second net list including the signal network, the second PDN, and the first semiconductor devices.

Abstract: Various embodiments of systems and methods are disclosed for determining a thermal power envelope. One method comprises determining a set of component and operating point combinations for a plurality of components in a portable computing device. Each component and operating point combination in the set defines an available operating point for each of the plurality of components. The portable computing device is iteratively set to each of the component and operating point combinations in the set. At each of the component and operating point combinations, power consumption data and skin temperature data is collected from a plurality of temperature sensors. An enhanced thermal power envelope is generated comprising the power consumption data and the skin temperature data for each of the component and operating point combinations.

Abstract: Structures for an on-chip capacitor and methods of forming an on-chip capacitor. A metal terminal is formed that has a side edge. Metal fingers are formed that have a parallel arrangement. Floating islands comprised of a metal are formed and are electrically isolated from the metal fingers. Each of the metal fingers has an end and extends from the side edge of the metal terminal toward the end. Each of the floating islands is arranged in a spaced relationship with the end of a respective one of the metal fingers.

Abstract: A method comprises forming a grid provided with a plurality of macro nodes. The grid comprises a plurality of meandering electrically conductive circuit paths through the plurality of macro nodes. The method comprises identifying a candidate macro node in the grid which includes only parallel micro node segments and selecting the candidate macro node. The method includes re-arranging the parallel micro node segments of the plurality of micro node meandering electrically conductive circuit paths in the candidate macro node of the grid such that at least one micro node segment is changed electrically to a non-parallel micro node segment in relation to other micro node segments in the candidate macro node to generate data representative of re-arranged meandering electrically conductive circuit paths for the grid. The method includes forming the re-arranged meandering electrically conductive circuit paths for the grid. A computing device and a computer program product for performing the method are also provided.

Abstract: In certain embodiments, multiple user tools each comprise a script program implementing an operation for addition to a respective compiled software program deployed within a computing environment. A memory module stores control code for insertion into computer code of a particular user tool. The control code implements a common control layer, implementing control modules across the user tools. The control modules include access control for controlling access to the user tool, change control for controlling modification of the user tool, and version control for controlling use of an appropriate version of the user tool. A processor receives the particular user tool; to create a controlled particular user tool, automatically modifies, the computer code of the particular user tool to add the control code; and deploys the controlled particular user tool for use in the computing environment in a manner controlled by the control code of the controlled particular user tool.

Abstract: Systems and techniques are described for determining a resistance of a conducting structure. The conducting structure can be partitioned into a set of polygons based on (1) equipotential lines and (2) boundaries of the conducting structure. Next, a matrix equation can be constructed, wherein for at least one polygon in the set of polygons, electric potentials of boundary elements on the boundaries of the polygon are represented by linear combinations of electric potentials of two or more equipotential lines. The resistance of the conducting structure can then be determined by solving the matrix equation.

Abstract: A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

Abstract: Power consumption of an integrated circuit (IC) clock mesh can be managed by a method of clock mesh design. Clock mesh data, including a location of a set of circuit elements and gating information of the set of circuit elements of the clock mesh, can be retrieved. A portion of the clock mesh, known as a local clock mesh, can be identified by analyzing the clock mesh data. The local clock mesh can include a subset of circuit elements having substantially similar clock gating characteristics, and which satisfy a placement density threshold. Mesh clock gating (MCG) cells can be added to wires surrounding the perimeter of the local mesh. MCG cells can be configured to enable and disable clock loads and clock mesh wires within the local clock mesh.

Abstract: Aspects of the disclosure include a threat detecting apparatus. The threat detecting apparatus can include an interface circuit, an opcode detector, and a pattern analyzer. The interface circuit is configured to receive a data stream. The opcode detector can be configured to identify an opcode sequence embedded in the data stream based on a first model graph that includes a plurality of interconnected token nodes. Each token node is representative of an occurrence or a non-occurrence of a token. The pattern analyzer may be configured to identify an opcode signature embedded in the identified opcode sequence based on a second model graph, and to output a signal indicative of the successful identification of the opcode signature. The second model graph can include a plurality of interconnected opcode nodes, and each opcode node can be representative of an occurrence or a non-occurrence of a predetermined combination of one or more opcodes.

Abstract: Disclosed herein are systems and methods to reduce wirelength and congestion in an integrated circuit (IC) design. The systems and methods disclosed herein may be implemented during a detailed placement stage of IC design to identify and select a cell for relocation and determine an area of interest to which the cell can be relocated. The systems and methods may identify one or more potential locations within the area of interest where the cell can be relocated to, and then determine a cost based upon the wirelength and/or congestion for the selected cell, at each of the one or more potential locations. Upon determining that a potential location may have a lower cost compared to the original location of the selected cell, the systems and methods may relocate the selected cell to the potential location.

Abstract: Aspects of the disclosed technology relate to techniques of full-chip assessment of time-dependent dielectric breakdown. A layout design is analyzed to identify matching patterns that match a pre-calculated pattern in a pattern database. Each of pre-calculated patterns in the pattern database has a time-to-failure characteristic value pre-computed based on a model of electric current path generation and evolution. Time-to-failure characteristic values are then determined for the matching patterns based on the pre-computed time-to-failure characteristic values and electric attributes of geometric elements in each of the matching patterns. Based on the time-to-failure characteristic values, matching patterns most susceptible to time-dependent dielectric breakdown are identified and fixed.

Abstract: A controller changes a droplet number larger than a second maximum droplet number among droplet numbers in first droplet data for each ink color to the second maximum droplet number. The controller, for each of certain pixels with a droplet number of black decreased to the second maximum droplet number, performs at least one of a first processing or a second processing. The first processing includes distributing a droplet number subtracted to decrease the droplet number of black to pixels surrounding the certain pixel in the first droplet data for black. The second processing includes adding the subtracted droplet number to a droplet number for the certain pixel in the first droplet data for a color other than black.

Abstract: A system and method for simulating behavior of a spin transfer torque magnetic random access memory (STT-MRAM) device includes a hardware processor (HP) and logic instructions (LI) stored in memory. The LI are executed by the HP to configure a library of functional blocks (FBs) to capture physical phenomenon of at least one element of the STT-MRAM configured in the form of a magnetic stack. Selected elements of the stack are mapped into a set of selected FBs (SFBs). The mapping converts the stack to a spin device circuit (SDC) represented by the SFBs. The SFBs are assembled to form the SDC replicating the stack. The SDC includes an electron spin transport, a magnet-dynamics, a magnetic coupling and a coupled electron transport+magnet-dynamics FBs. A set of output parameters simulating the STT-MRAM is generated by the SFBs in response to receiving a set of input parameters.

Abstract: A routing architecture for fast interconnections between Look-Up Tables (LUTs) in a group of Basic Logic Elements (BLEs), whereby a size of the group ranges from 1 to k+1, where k is the number of inputs of a LUT, and LUTs in the group are indexed from 1 to k+1, and whereby (a) an output of a LUTi, 1?i?k, connects to one of the inputs of routing multiplexers of LUTj, i<j?k+1, hence creating a fast interconnection between LUTs, each routing multiplexer of LUTm, 2?m?k+1, has only one input that is connected to the output of an other LUT, the output of LUT(k+1) being devoid of any connection to any one of the inputs of the routing multiplexers; (b) a subset of the inputs of LUT1 are connected to the outputs of other LUTs by means of fast interconnections, leaving the remaining inputs of LUT1 free of any fast interconnection, whereby for LUTp, 2?p?k+1, p?1 inputs of the LUTp are connected to the outputs of LUTq, 1?q?j, by means of fast interconnections; and (c) a cluster-based logic block contains at least one

Abstract: Technology for relative timing characterization enabling use of clocked electronic design automation (EDA) tool flows is disclosed. In an example, a method can include a EDA tool identifying a relative timing constraint (RTC) of a cell in a circuit model between a point of divergence (pod) event and two point of convergence (poc) events, wherein the two poc events include a first poc event (poc0) and a second poc event (poc1). The EDA tool can generate a maximum target delay for a first poc event path between the pod event and the first poc event. The EDA tool can generate a minimum target delay for a second poc event path between the pod event and the second poc event. The EDA tool can then optimize the circuit model using the maximum target delay and the minimum target delay.

Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.

Abstract: A processor-memory system, a stacked-wafer processor-memory system, and a method of fabricating a processor-memory system are disclosed. In an embodiment, the invention provides a processor-memory system comprising a memory area, a multitude of specialized processors, and a management processor. The specialized processors are embedded in the memory area, and each of the specialized processors is configured for performing a specified set of operations using an associated memory domain in the memory area. The management processor is provided to control operations of an associated set of the specialized processors. In one embodiment, each of the specialized processors controls a respective one associated memory domain in the memory area. In an embodiment, the processor-memory system further comprises a specialized processor wafer. The specialized processor wafer includes the memory area, and the multitude of specialized processors are embedded in the specialized processor wafer.

Abstract: A planned schematic for an electronic system is hierarchically divided into base-level schematic blocks which may be designed individually. In accordance with a plurality of sets of design requirements, variant overlays are designed for each base-level schematic block, each overlay including variant parameter values which may replace corresponding parameter values of the schematic blocks. The schematic blocks are integrated to generate a system-level schematic, and the variant overlays for a given set of design requirements are merged to generate a system variant overlay. Parameter values of the system variant overlay may then replace corresponding parameter values of the system-level schematic to generate a variant schematic for the given set of design requirements.

Abstract: Implementing a circuit design may include, responsive to a user input selecting a design, executing an implementation script of the design using the processor. Executing the implementation script may generate instructions for generating a circuit design from the design. Responsive to the instructions and using the processor, cores of the design may be automatically instantiated and connected.

Abstract: Methods and systems of an electronic circuit design system described herein provide a new abutment tool in which a chain post-processing function is called once per resultant chain of abutted instances after each chain is fully formed in a layout. In an embodiment, a process design kit (PDK) abutment update function is enhanced to support a new chain processing event that facilitates a creation of new top level figures in a cell view in which the chain lives, and further facilitate adjustment of parameters of instances of programmable cells in the chain.

Abstract: A method for performing timing analysis on calibrated paths includes performing static timing analysis on the calibrated paths to obtain delay and margin information. The delay and margin information are utilized to emulate operations performed during calibration.

Abstract: A computer implemented system comprises a processor programmed to analyze a circuit to determine a response of the circuit to an input radio frequency (RF) signal, for at least one of designing, manufacturing, and testing the circuit. An interposer model is tangibly embodied in a non-transitory machine readable storage medium to be accessed by the processor. The interposer model is processed by the computer to output data representing a response of a though substrate via (TSV) to the radio frequency (RF) signal. The interposer model comprises a plurality of TSV models. Each TSV model has a respective three-port network. One of the ports of each three-port network is a floating node. The floating nodes of each of the three-port networks are connected to each other.

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one AA-short-related failure mode.

Abstract: Performance analysis for an electronic system includes determining, using a processor, data traffic patterns stored within a core library of an electronic design automation system, wherein the data traffic patterns are part of cores stored within the core library. The determined data traffic patterns are displayed using a display as modeling options. A user input selecting a displayed data traffic pattern is received; and the selected data traffic pattern is executed as part of modeling the electronic system.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention includes updating the coverage schema, wherein the updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generating constraints used to satisfy requirements for meeting the first set of events and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated coverage schema.

Abstract: The invention relates to a method for determining by optimization a multi-core architecture and a way of implementing an application on the architecture for a given application, the method comprising: providing a parallelized application and candidate architectures comprising different hardware blocks, defining a first exploration space whose elements are the different ways of implementing the application on each of the candidate architectures, selecting, in the first exploration space, the elements verifying a criterion to obtain a second exploration space, determining, in the second exploration space, the elements verifying a criterion to obtain a third exploration space, computing the number of data exchanged between the hardware blocks for each of the elements of the third exploration space to obtain a fourth exploration space, and optimizing the elements of the fourth exploration space according to a criterion.

Abstract: Embodiments of a die stacking apparatus are provided. The die stacking apparatus includes a storage device configured to contain a top wafer and an interposer wafer. The top wafer has a number of top dies, and the interposer wafer has a number of interposer dies. The die stacking apparatus also includes a carrier device configured to carry the interposer wafer, and a transferring device configured to transfer the interposer wafer to the carrier device and to dispose the top dies on the interposer dies. The die stacking apparatus further includes a process module configured to control the transferring device. The process module controls the transferring device to transfer the interposer wafer to the carrier device, and controls the transferring device to dispose the top dies on the interposer dies of the interposer wafer, which is stacked on the carrier device.

Abstract: A microcontroller system is organized into power domains. A power manager of the microcontroller system can change the power configuration of a power domain in response to event from an event generating module without activating a processor of the microcontroller system.

Abstract: The circuit simulating method according to an embodiment includes obtaining a first electrical characteristic value of a circuit element that operates under a predetermined operational condition. The circuit simulating method includes correcting the first electrical characteristic value based on a period in which application of an electrical stress equal to or higher than a reference value is stopped during operation of the circuit element.

Abstract: A user specified high level design selects a plurality of IP cores for placement in a customized system on a chip. A single integrated service automatically performs each of a design integration phase, specification phase, and verification phase for the user specified high level design to generate an integration file specifying stitching between a plurality of pins of each of the plurality of IP cores, a specification file specifying one or more characteristics of the customized system on a chip based on the user specified high level design, and a verification testbench for verification of the user specified high level design.

Abstract: A method for designing a dual-mode logic circuit which is selectably operational in static and dynamic modes is performed as follows. A basis library with a DML inverter and dual-mode logic (DML) bicells is provided. Each DML bicell includes a type-A DML logic gate with a clock input and a type-B DML logic gate with an inverted clock input. A pseudo-static library is formed from the basis library by modifying each bicell of the basis library and specifying at least one dynamic timing parameter. A dynamic library is formed from the basis library by specifying dynamic timing parameters for the basis library DML inverter and bicells. Logic behavior of the required logic circuit is defined. An initial logic circuit design synthesized from the pseudo-static library and the defined logic behavior. Finally, a dynamic circuit design is formed by replacing modified bicells with corresponding bicells from the dynamic library.

Abstract: The present invention relates to a field of semiconductor design technologies. The present invention implements a sweep simulation method in which process corners are continuously swept in a simulation job, and a process corner a field is used as an independent variable, so that a simulation program outputs a waveform chart using the parameter values of the device model under various process corner conditions or performance response values of a testbench circuit under various process corner conditions as dependent variables.

Abstract: An RF front-end with on-chip transmitter/receiver isolation using a gyrator is presented herein. The RF front end is configured to support full-duplex communication and includes a gyrator and a transformer. The gyrator includes two transistors that are configured to isolate the input of a low-noise amplifier (LNA) from the output of a power amplifier (PA). The gyrator is further configured to isolate the output of the PA from the input of the LNA. The gyrator is at least partially or fully capable of being integrated on silicon-based substrate.

Abstract: A method includes generating a first set of configurations of a layout of semiconductor components. The configurations of the first set of configurations each satisfy a first sub-set of a set of design rules. The method also includes generating a second set of configurations of the layout of semiconductor components. The second set of configurations are generated by eliminating one or more configurations of the first set of configurations based on a determination that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the set of design rules. The method further includes manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second set of configurations.

Abstract: A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit, and receiving a user selection of at least one of a computer-aided design (CAD) tool format and a PCB layout tool format. The method also includes receiving a user selection to include footprints for the components used in the schematic content or PCB layout and exporting at least one of the schematic content, and PCB layout as well as the PCB footprints to one or more files in accordance with the selected CAD and/or PCB layout tool format.